This application claims the benefit and priority of Great Britain Patent Application No. 1319921.1 filed Nov. 12, 2013. The entire disclosure of the above application is incorporated herein by reference.
The present disclosure relates to a method and control system for controlling a power converter by modulating switching signals in a switching device of the power converter.
A sinusoidal output current can be created at AC output 103 by a combination of switching states of the six switches. However, the inverter 100 must be controlled so that the two switches in the same phase are never switched on at the same time, so that the DC supply 101 is not short circuited. Thus, if 200a is on, 200b must be off and vice versa; if 300a is on, 300b must be off and vice versa; and if 400a is on, 400b must be off and vice versa. This results in eight possible switching vectors for the inverter, as shown in Table 1. In Table 1, the vector values are the states of the three upper switches 200a, 300a, 400a, with the three lower switches 200b, 300b, 400b necessarily taking the opposite state to avoid shorting out the DC supply.
At low output frequencies (such as output frequencies less than around 2 Hz) the switch control timing patterns change relatively slowly and the temperature of each individual switch 200a, 200b, 300a, 300b, 400a, 400b can become excessive even if the current delivered by the drive is less than the inverter rated output current as each individual switch may be on for a period of time sufficient to cause excessive temperature of the switch.
Because of this, and other, problems, the control of switching power converters is an area of increasing interest.
It is an object of the described technique to provide an improved method and control system for a power converter.
A method of driving a power conversion system is provided, the power conversion system comprising a DC source and an inverter coupled to the DC source and configured to receive DC power from the DC source, the inverter comprising one or more AC terminals for supplying AC power at an output frequency and an inverter switching network comprising a plurality of inverter switches for converting the DC power to the AC power. According to an embodiment, the method comprises: applying control signals to the inverter switching network in accordance with a selected switching sequence, wherein a switching sequence is applied corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin; storing a plurality of simultaneous switching schemes in which, for a single switching cycle, a switch in each of at least two phases of the inverter switching network is switched substantially simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network being in a given state and in which the switch in each of the at least two phases is switched substantially simultaneously from the second state to the first state with the switch in the at least one other phase being in the given state; and at low output frequency, applying a simultaneous switching sequence by applying a first of the simultaneous switching schemes in dependence on the position of the demand vector in relation to the stationary active vectors.
The magnitudes of the voltages in each phase may be the same for a given simultaneous switching scheme but may differ between simultaneous switching schemes.
At low output frequency, a simultaneous switching sequence may be applied by applying a first and a second of the simultaneous switching schemes in dependence on the position of the demand vector in relation to the stationary active vectors. The method may further comprise alternating between the first and the second simultaneous switching schemes. A sequence of application of the first and second simultaneous switching schemes may be read from stored information, such as in a look up table.
The simultaneous switching scheme applied may be that for a stationary vector preceding the current demand vector.
In the present disclosure, low output frequency means an output frequency between 0 Hz and 10 Hz and more particularly between 0 Hz and 2 Hz.
In one embodiment, the power conversion system is a three-phase power conversion system, and each phase of the inverter switching network comprises two inverter switches. There are six stationary active vectors around the periphery and two stationary zero vectors at an origin and there are six simultaneous switching schemes.
For each simultaneous switching scheme, phase voltages of equal magnitude may be generated. Different magnitudes of phase voltages may be applied between different simultaneous switching schemes.
A power conversion system is also provided comprising: a DC source; an inverter coupled to the DC source and configured to receive the DC power, the inverter comprising one or more AC terminals for supplying AC power at an output frequency and an inverter switching network comprising a plurality of inverter switches for converting the DC power to the AC power; and a switch controller arranged to apply control signals to the inverter switching network in accordance with a selected switching sequence, wherein the switch controller is arranged to apply a switching sequence corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin; wherein the switch controller is arranged to store simultaneous switching schemes in which, for a single switching cycle, a switch in each of at least two phases of the inverter switching network is switched simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network being in a given state and the switch in each of the at least two phases is switched simultaneously from the second state to the first state with the switch in the at least one other phase being in the given state; and wherein the switch controller is arranged, at low frequency, to apply a simultaneous switching sequence by applying a first of the simultaneous switching schemes in dependence on the position of the demand vector in relation to the stationary active vectors.
A switch controller for a power conversion system is also provided, the power conversion system comprising a DC source and an inverter coupled to the DC source and configured to receive the DC power, the inverter comprising one or more AC terminals for supplying AC power at an output frequency and an inverter switching network comprising a plurality of inverter switches for converting the DC power to the AC power; the switch controller being arranged, in use, to apply control signals to an inverter switching network in accordance with a selected switching sequence, wherein the switch controller is arranged to apply a switching sequence corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin; wherein the switch controller is arranged to store simultaneous switching schemes in which, for a single switching cycle, a switch in each of at least two phases of the inverter switching network is switched simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network being in a given state and the switch in each of the at least two phases is switched simultaneously from the second state to the first state with the switch in the at least one other phase being in the given state; and wherein the switch controller is arranged, at low frequency, to apply a simultaneous switching sequence by applying a first of the simultaneous switching schemes in dependence on the position of the demand vector in relation to the stationary active vectors. Features and advantages described in relation to one aspect of the described technique may also be applicable to another aspect of the described technique.
Prior art arrangements have already been described with reference to accompanying
The technique will now be further described, by way of example only, with reference to accompanying
For power converters, such as that shown in
Simultaneous switching vector angles will now be described. At low output frequencies i.e. those in the order of tens of Hertz or less (e.g. less than around 2 Hz), the output voltage angle can be quantised to positions in the wave where no single switch (e.g. an IGBT) is under peak stress. This aims to avoid vectors where a switch in one phase conducts for longer than a switch in the other phases, including the angle where the voltage is aligned with a particular phase where the ON time of the particular phase switch can be up to twice that of the other phases.
For symmetrical switching (where t—0 equals t—3 in
There are six “simultaneous switching” vector timing patterns per electrical cycle as there are three phase switching orders each of which can have either t—1 or t—2 equal to zero.
In the technique described, the magnitude of Vs is controlled by the ratio of V0 (or V7) and the magnitudes of Vu, Vv and Vw are equal (although they may be of different signs).
Thus, neglecting dead-times, two upper switches (200a, 300a, 400a) and one lower switch (200b, 300b, 400b) will switch simultaneously and the other one upper switch and two lower switches will switch simultaneously. This results in similar stress on each set of three IGBTs (given the reduced effect of current lag at very low output frequency).
As will be appreciated, the switching timing pattern for each upper switch 200a, 300a, 400a may be the inverse of the switching patterns shown and the switching function for each lower switch 200b, 300b, 400b will be the inverse of the corresponding upper switch.
Thus the switch controller 108 is arranged to store simultaneous switching schemes comprising, for a single switching cycle, an active period in which at least two phases are in a first state and at least one phase is in a second state, and in which the at least two phases are switched substantially simultaneously from the first state to the second state with the at least one phase remaining in the second state and in which the at least two phases are switched substantially simultaneously from the second state to the first state with the at least one phase remaining in the second state (as shown in
Thus a plurality of simultaneous switching schemes are stored in which a switch in each of at least two phases of the inverter switching network is switched substantially simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network not being switched at the same time and in which the switch in each of the at least two phases is switched simultaneously from the second state to the first state with the switch in the at least one other phase not being switched at the same time.
These simultaneous switching schemes are applied at low frequency, with the magnitudes of the voltages in each phase being the same for a given simultaneous switching scheme, so providing balanced switch conduction times. Control signals are applied to the inverter switching network in accordance with a selected switching sequence, wherein a switching sequence is applied corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin.
Three related methods are presented in this document that all share the same basic principal. All methods use the “simultaneous switching” vector timing patterns but have varying computational requirements and angular quantisation.
Method One—Simple Selection Method with Largest Angle of Quantisation
This method requires the lowest amount of computation but results in the largest quantisation steps in the output voltage vector position and hence a trapezoidal voltage which can result in a large current and torque ripple.
As the demand vector angle rotates, the actual output voltage vector moves from one of the six “simultaneous switching” vectors to the next. The change occurs only when the demand passes the “simultaneous switching” vector to avoid oscillation at standstill (0 Hz). For instance, when the demand vector angle is between 1 and 60 degrees, the control signal to the inverter switching network is as shown in
The method may be extended to extra low frequency (<0.1 Hz) and at 0 Hz to reduce the conduction time of individual IGBTs. This may be achieved by omitting the “simultaneous switching” vectors during which the hottest IGBT would be switched for longer than its complementary lower IGBT. This method may result in a changing voltage vector output, even at zero demand frequency, as different IGBTs become the hottest. A time constant (e.g. one second) and a temperature hysteresis may be used.
According to this first embodiment, at low frequencies the switching patterns shown in
Method Two—Enhanced Vector and Pattern Selection Based on Time Slots
This method requires a medium amount of computation and reduces the size of the angular quantisation steps.
According to this second embodiment, an average voltage vector angle is produced between the “simultaneous switching” vectors while still only using voltage “simultaneous switching” vector timing patterns. This is achieved by using an alternating pattern to select between the two “simultaneous switching” vectors bounding the 60 degree sector in which the demand output vector angle is situated.
The alternating pattern is provided over a set period with the ratio of the number of each of the two boundary “simultaneous switching” vectors being proportional to the output vector angle within the 60 degree sector.
According to this second embodiment, the output vector is alternated between two of the “simultaneous switching” vectors. The ratio of the number of each of the two boundary “simultaneous switching” vectors applies is proportional to the output vector angle within the 60 degree sector.
Consider the simple case shown in
In contrast to the first embodiment discussed in relation to
The “simultaneous switching” vectors used can be selected as the demand vector passes a “simultaneous switching” vector, which is similar to the first method described above. The pattern of alternating “simultaneous switching” vectors and the size compensation can be provided using a simple look up table.
The quantisation of the additional vectors which can be produced by this method depends on the PWM switching period and the time period over which the additional vectors are produced. For example, at a 16 kHz switching frequency (PWM Period=62.5 us) there are 16 cycles in a 1 ms pattern period where the output vector is alternated between two of the “simultaneous switching” vectors. So (for a switching cycle of 16 kHz) that there are 8 of each in the 1 ms period.
According to this second embodiment, at low frequencies two consecutive simultaneous switching patterns (for instance those shown in
An embodiment might use a pattern that spends the smallest amount of consecutive switching period slices on either of the “simultaneous switching” vectors to reduce the ripple. For instance, when the output vector angle is 30 degrees between vector 1 and vector 2 (as shown in
Alternatively, if the temperature of one of the switches is significantly higher than the temperature of the other switches, the way in which the timing patterns are applied may be changed accordingly. For instance, say the upper switch in phase U is hotter than the other switches. In the active period t—2 of the switching pattern shown in
The pattern of alternating “simultaneous switching” vectors and the size compensation can be provided using a simple look up table. The level of quantisation may also be selected and a relevant look up table used.
In this second embodiment, an average voltage vector angle is produced between the “simultaneous switching” vectors while still only using voltage “simultaneous switching” vector timing patterns. This is achieved by using an alternating pattern to select between the two “simultaneous switching” vectors bounding the 60 degree sector in which the demand output vector angle is situated. The magnitudes of the “simultaneous switching” vectors are identical.
Method Three—Enhanced Vector and Pattern Selection Based on Ratio of Vector Lengths
This method requires the highest amount of computation but can provide a very small quantisation step in the average output voltage vector.
According to this third embodiment, alternating “simultaneous switching” vectors are used with unequal magnitudes to produce an average vector of an angle between the “simultaneous switching” vectors used.
The method uses one of the “simultaneous switching” vectors to define a d-axis to reduce computation. The other “simultaneous switching” vector is thus at 60 degree to this defined d-axis.
The demand vector is converted into the d and q components. These components are then used to provide magnitudes for the two “simultaneous switching” vectors, R and S which are applied as discussed above in relation to the second embodiment.
The equations above produce the vector length (i.e. magnitude) for the alternating “simultaneous switching” vectors, R and S. The d-axis is set to the angle of vector R. The table below gives the “simultaneous switching” vector magnitudes in steps of one degree through the sector bounded by the “simultaneous switching” vectors R and S.
For instance, if the demand vector is at an angle of 51 degrees from the switching vector R, then the control 108 applies switching vector S with phase magnitude of 1.79 and switching vector R with phase magnitude of 0.36. Simultaneous switching vectors R and S may be applied once each or may be applied in an alternating pattern e.g. R-S-R-S-R-S-R-S etc. with the appropriate phase voltage magnitudes. This information may be stored and the sequence of application of the first and second simultaneous switching schemes may be read from stored information. For instance, a per unit look-up table can be used to reduce computation.
The technique as described herein aims to provide thermal control based on the space vector selection. This thermal control is provided to postpone the current rating reduction necessary at low output frequencies. The technique uses specific output voltage vectors (called the “simultaneous switching” vectors) which result in an output voltage angle quantised to vector positions where the semiconductor switches stresses are the most balanced. For each simultaneous switching vector (or simultaneous switching scheme), the magnitude of voltage in each phase is the same in a given PWM switching cycle i.e. the magnitude of voltage in phase U is the same as that in phase V and is the same as in phase W.
Prior art methods simply reduce the current rating when the drive is supply a low output frequency. The technique postpones, or removes, the requirement to reduce the current rating at low output frequencies. Ultimately, the technique reduces the probability of the drive tripping as a result of excessive inverter temperature.
The techniques describes involves the storing of a plurality of simultaneous switching schemes in which a switch in each of at least two phases of the inverter switching network is switched substantially simultaneously from a first state to a second state (allowing for dead time to prevent short-circuiting). Not all of the phases are switched simultaneously. At the time of switching the switches in the at least two phases from a first state to a second state, at least one other phase of the inverter switching network is in a given state i.e. the other phase is not switched at the same time. Similarly when the switch in each of the at least two phases are switched simultaneously from the second state to the first state the switch in the at least one other phase is in a given state.
In the foregoing specification, techniques have been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the scope of the technique. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
It is to be noted that the methods as described have actions being carried out in a particular order. However, it would be clear to a person skilled in the art that the order of any actions performed, where the context permits, can be varied and thus the ordering as described herein is not intended to be limiting.
It is also to be noted that where a method has been described it is also intended that protection is also sought for a device arranged to carry out the method and where features have been claimed independently of each other these may be used together with other claimed features.
Embodiments have been described herein in relation to IGBT switches. However the method and apparatus described are not intended to be limited to these types of switches but may be applicable to other switches.
Number | Date | Country | Kind |
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1319921.1 | Nov 2013 | GB | national |