Modulation/demodulation apparatus using matrix and anti-matrix

Abstract

When a narrow-band digital filter is used for demodulating a signal which has been modulated by using a plenty of sub-carriers, the number of stages is increased, analysis requires a long time, the transmission speed is not increased, and the circuit size is increased. The modulation circuit operation is considered as multiplication.

Description

DETAILED DESCRIPTION OF INVENTION

[0001] [Engineering Field of this Invention]

[0002] This invention use the carrier of which reflection is not so strong, and is applied to the modulation and demodulation apparatus using quadrature magnitude modulation of many number of sub-carrier and transmit the digital data from each other.

[0003] [Conventional Engineering]

[0004] Such method as transmitting the data using many number of sub-carriers which are modulated by quadrature magnitude modulation is applied to QAM of digital cable TV or to DSL of metal twist-pair and so on. These method concentrate on the frequency of each carriers and demodulate the signal by applying digital filter or FFT using impulse response result as coefficient of filter. For this reason it takes comparatively long time to detect the amplitude of a carrier because of looking until it seems as same continuous wave form.

[0005] [Target to Solve by this Invention]

[0006] To detect accurate result from modulated signal, demodulation circuit such as digital filter or FFT concentrate on frequency of each sub-carrier independently and increase the number of wave form to make difficulty of transmission speed. To make transmission speed high, for example, is to increase the number of carriers and reach so high frequency as to decrease transmission distance greatly.

[0007] [Method to Solve these Difficulty by this Invention]

[0008] By this invention, demodulation circuit do not concentrate on frequency of each sub-carrier independently but pay attention the modulated data consisted by the amount of quadrature amplitude modulation of each sub-carriers, and this construction is seemed to be simultaneous linear equation defining amplitude of each sub-carriers as unknown, so can get the result of amplitude of each sub-carrier by solving this simultaneous linear equation. As simultaneous linear equation can be solved in case of the number of unknown equal to the number of each equation, ideally so as to be able to exchange the number of data by equal number of modulated data. This invention is aimed to build the circuit method by taking the simultaneous linear equation and solving in modulation and demodulation circuit. To take amount of quadrature modulation of many sub-carriers is described using matrix mathematics as following.

[0009] This matrix is square and is constructed equal number of line and column which is two times number of sub-carrier frequency and mean sine wave and cosine wave using one frequency. The elements of this matrix called as modulation matrix are value of trigonometric function, and line means number of sampling of which interval is equal to DA converter frequency, and column means sub-carrier which is sine or cosine of a carrier frequency. The product of this modulation matrix and modulation data matrix of one column responding each sub-carrier is named as the modulated data matrix and is converted by DA converter to analog output respectively. As the lines of modulation matrix are arranged according to DA converting number and is the sine or cosine value of carrier frequency, the product of this modulation matrix and one column modulation data matrix means sum of product of the sine or cosine value at every line and modulation data specified to the sub-carrier, and become modulated data for DA converter input of its every interval. These show that quadrature modulation is described as the simultaneous linear equation.

[0010] From the view of demodulation side about this equation, it seams for modulated data to be the received data detected by AD converter, and modulation data as unknown. As there are modulation data as unknown of two times number kinds of carrier frequency, so there are equations of two times number of carrier frequency. Therefore this simultaneous linear equation can be solved. At demodulation side, the sampling frequency of AD converter is adjusted to the sampling frequency of DA converter of modulation side, and similar data as modulated data is got from AD converter, and demodulated data is got as the product of received data matrix from AD converter and inverse matrix of modulation matrix called demodulation matrix. And more, over-sampling is implemented to this concept, the numbers of over-sampling modulation matrix are created, and the numbers of demodulation matrix, which are the inverse matrix of modulation matrix, become as the numbers of over-sampling. And the over-sampling modulation matrix is composed by inserting each line in over-sampling order position, and the over-sampling demodulation matrix is composed by similar method of insertion. When modulation uses this over-sampling modulation matrix and demodulation uses this over-sampling demodulation matrix, then over-sampling number times demodulated data is got. When modulation uses this over-sampling modulation matrix and demodulation uses individual inverse matrices, then the same numbers of over-sampling demodulated data are got.

[0011] In following, these theory is described by using mathematical equation.

[0012] About the modulation matrix which is the base of this theory,

[0013] Line number: i i=1˜2αn

[0014] Column number: j j=1˜2n

[0015] About above definition

[0016] Number of carrier frequency: n

[0017] Number of over-sampling: α

[0018] According to these definition

[0019] Carrier frequency number: p p=0˜(n−1)

[0020] Original sampling order (without over-sampling): q q=0˜(2n−1)

[0021] Order of over-sampling: r r=1˜α

[0022] Kind of wave: s s=1 indicate cosine wave s=2 indicate sine wave

[0023] About relation of these parameter to line number i and column number j

i=αq+r q= 0˜(2n−1) r=1˜α therefore i=1˜2αn

j= 2p+s p=0(n−1) s=1 or 2 therefore j=1˜2n

[0024] the element of line number i and column number j is Fj(i) and is defined as

F j (i)=F2p+s(αq+r)

[0025] Frequency of frequency number p: fp

[0026] Angle velocity of frequency number p: ωp

[0027] Number of original sampling in one complete wave form: ρ

[0028] interval time of over-sampling: Ts1$\begin{array}{c}{\omega }_p=2\pi f_p\\ T_s=\frac{1}{\rho \times \alpha \times f_0}\end{array}$

[0029] and, the angle of sine and cosine in the element of line number i 2${\omega }_p\times T_s\times i=\frac{2\pi f_p}{\rho \times \alpha \times f_0}\times \left(\alpha q+r\right)$

[0030] Therefore, the element of modulation matrix Fj(i) is described following. 3$\begin{array}{c}{F}_j\left(i\right)=F_{2p+s}\left(\alpha q+r\right)=\cos \left\{\frac{2\pi \mathrm{fp}}{\rho \times \alpha \times f_0}\times \left(\alpha q+r\right)\right\}\mathrm{In}\mathrm{case}\mathrm{of}s=1\\ =\sin \left\{\frac{2\pi \mathrm{fp}}{\rho \times \alpha \times f_0}\times \left(\alpha q+r\right)\right\}\mathrm{In}\mathrm{case}\mathrm{of}s=2\end{array}$

[0031] The size of modulation matrix is 2αn lines and 2n columns. The size of modulation data matrix is 2n lines and one column, and of which element is described as xj because the line number of modulation data matrix is related to the column number of modulation matrix for the reason of relating each modulation data to the sub-carrier of sine and cosine individually. Equation of quadrature modulation is described as the product of the modulation matrix and modulation data matrix. The size of modulated data matrix, which is the product of the modulation matrix and modulation data matrix, is 2αn lines and one column, and the element of modulated data matrix is described as di according to line number of modulation matrix. As the element of modulated data matrix di is the amount of quadrature modulation of each sub-carrier at every sampling time, the equation of modulation is described by matrix as following

(Fj(i))×(xj)=(di)

[0032] and this equation is described by elements as following 4$\left(\begin{array}{c}{F}_1\left(1\right),F_2\left(1\right),F_3\left(1\right),\cdots F_{2n-1}\left(1\right),F_{2n}\left(1\right),\\ F_1\left(2\right),F_2\left(2\right),F_3\left(2\right),\cdots F_{2n-1}\left(2\right),F_{2n}\left(2\right),\\ F_1\left(3\right),F_2\left(3\right),F_3\left(3\right),\cdots F_{2n-1}\left(3\right),F_{2n}\left(3\right),\\ ⋮\\ F_1\left(2\alpha n\right),F_2\left(2\alpha n\right),F_3\left(2\alpha n\right),\cdots F_{2n-1}\left(2\alpha n\right),F_{2n}\left(2\alpha n\right),\end{array}\right)\times \left(\begin{array}{c}{x}_1\\ x_2\\ ⋮\\ x_j\\ ⋮\\ x_{2n}\end{array}\right)=\left(\begin{array}{c}{d}_1\\ d_2\\ ⋮\\ d_i\\ ⋮\\ d_{2\alpha n}\end{array}\right)$

[0033] And this equation is described by simultaneous linear equation is as following

F 1 (1)x1+F2(1)x2+F3(1)x3+ . . . +F2n−1(1)x2n−1+F2n(1)x2n=d1

F 1 (2)x1+F2(2)x2+F3(2)x3+ . . . +F2n−1(2)x2n−1+F2n(2)x2n=d2

F 1 (3)x1+F2(3)x2+F3(3)x3+ . . . +F2n−1(3)x2n−1+F2n(3)x2n=d2

F 1 (2αn)x1+F2(2αn)x2+F3(2αn)x3+ . . . +F2n−1(2αn)x2n−1+F2n(2αn)x2n=d2αn

[0034] Depend on this simultaneous linear equation, the product of initially determined Fj(i) and modulation data xj related by j, summed together through all j resulting to dj as the input data of DA converter at sampling number i, and is converted to analog output. dj can be got by multiplying and accumulating in every sampling interval. Following is described about the treatment in receiving side. The matrix of which elements Fr0,j(g) is picked up from modulation matrix by implementing the over-sampling order number r=r0, then is represented as following. 5$\begin{array}{c}\begin{array}{c}{F}_{\mathrm{r0},2p+s}(q)=\cos \left\{\frac{2\pi f_p}{\rho \times \alpha \times f_0}\times \left(\alpha q+r_0\right)\right\}\mathrm{in}\mathrm{case}\mathrm{of}s=1\\ \sin \left\{\frac{2\pi f_p}{\rho \times \alpha \times f_0}\times \left(\alpha q+r_0\right)\right\}\mathrm{in}\mathrm{case}\mathrm{of}s=2\end{array}\\ q=0\sim \left(2n-1\right)\end{array}$

[0035] The first line of this matrix is first r0 line of modulation matrix, and the other line is picked up from modulation matrix every α line from r0 to constructing 2n lines. The first line of related modulated data matrix is first r0 line of modulated data matrix and the other line is picked up from modulated data matrix every α line from r0 to constructing 2n lines, and of which element is described as dr0,q as following.

d r0,q =d (αq+r 0 )

[0036] The modulation equation of above matrix picking up by sampling order r0 is described by matrix as following

(Fr0,2p+s(q))×(x2p+s)=(dr0,q)

[0037] and this equation is described by elements as following 6$\left(\begin{array}{c}{F}_{r0,1}\left(0\right),F_{r0,2}\left(0\right),F_{r0,3}\left(0\right),\cdots F_{r0,2n-1}\left(0\right),F_{r0,2n}\left(0\right)\\ F_{r0,1}\left(1\right),F_{r0,2}\left(1\right),F_{r0,3}\left(1\right),\cdots F_{r0,2n-1}\left(1\right),F_{r0,2n}\left(1\right)\\ ⋮\\ \begin{array}{c}{F}_{r0,1}\left(2n-1\right),F_{r0,2}\left(2n-1\right),F_{r0,3}\left(2n-1\right),\cdots \\ F_{r0,2n-1}\left(2n-1\right),F_{r0,2n}\left(2n-1\right),\end{array}\end{array}\right)\times \left(\begin{array}{c}{x}_1\\ x_2\\ ⋮\\ x_j\\ ⋮\\ x_{2n}\end{array}\right)=\left(\begin{array}{c}{d}_{r0,0}\\ d_{r0,1}\\ ⋮\\ ⋮\\ ⋮\\ d_{r0,2\alpha n}\end{array}\right)$

[0038] And this equation is described by simultaneous linear equation as following

F r0,1 (0)x1+Fr0,2(0)x2+Fr0,3(0)x3+ . . . Fr0,2n−1(0)x2n−1+Fr0,2n(0)x2n=dr0,0

F r0,1 (1)x1+Fr0,2(1)x2+Fr0,3(1)x3+ . . . Fr0,2n−1(1)x2n−1+Fr0,2n(1)x2n=dr0,1

F r0,1 (2n−1)x1+Fr0,2(2n−1)x2+Fr0,3(2n−1)3+ . . Fr0,2n−1(2n−1)x2n−1+Fr0,2n(2n−1)x2n=dr0,2n−1

[0039] In this simultaneous linear equation, dr0,0˜dr0,2n−1 are similarly got as receiving data by AD converter. For the demodulation side to detect the modulation data x1˜x2n, the inverse matrix of the modulation matrix of which element is (Fr0,2p+s) is applied to solving this simultaneous linear equation. The element of inverse matrix of modulation matrix is described as Gr0,j(q) 7$\left(\begin{array}{c}{G}_{r0,1}\left(0\right),G_{r0,2}\left(0\right),G_{r0,3}\left(0\right),\cdots G_{r0,2n-1}\left(0\right),G_{r0,2n}\left(0\right)\\ G_{r0,1}\left(1\right),G_{r0,2}\left(1\right),G_{r0,3}\left(1\right),\cdots G_{r0,2n-1}\left(1\right),G_{r0,2n}\left(1\right)\\ ⋮\\ G_{r0,1}\left(2n-1\right),G_{r0,2}\left(2n-1\right),G_{r0,3}\left(2n-1\right),\cdots \\ G_{r0,2n-1}\left(2n-1\right),G_{r0,2n}\left(2n-1\right),\end{array}\right)\times \left(\begin{array}{c}{d}_{r0,0}\\ d_{r0,1}\\ ⋮\\ d_{r0,2n-1}\end{array}\right)=\left(\begin{array}{c}{x}_1\\ x_2\\ ⋮\\ x_{2n}\end{array}\right)$

[0040] And this equation is described by simultaneous linear equation as following

G r0,1 (0)dr0,0+Gr0,2(0)dr0,1+Gr0,3(0)dr0,2+ . . . Gr0,2n−1(0)dr0,2n−2+Gr0,2n(0)dr0,2n−1=x1

G r0,1 (1)dr0,0+Gr0,2(1)dr0,1+Gr0,3(1)dr0,2+ . . . Gr0,2n−1(1)dr0,2n−2+Gr0,2n(0)dr0,2n−1=x2

G r0,1 (2n−1)dr0,0+Gr0,2(2n−1)dr0,1+Gr0,3(2n−1)dr0,2+ . . Gr0,2n−1(2n−1)dr0,2n−2+Gr0,2n(2n−1)dr0,2n−1=x2n

[0041] According to this simultaneous linear equation, the inverse matrix of the matrix which is picked up the same over-sampling number line from the over-sampling modulation matrix, and the receiving data coming from AD converter at every r0 sampling interval, are multiplied and summed together by two times number of carrier frequency accumulators, continuously until the end of one frame of modulation, and then the demodulated data of all sub-carriers are got.

[0042] Mathematically, the size of receiving data matrix is one column matrix, and about the construction of inverse matrix, the line number is relating to column number of modulation matrix, and the column number is relating to line number of modulation matrix and it look like exchange the line and column.

[0043] As the number of over-sampling is α, the number of α inverse matrix are created from modulation matrix and are got the number of α kind of demodulated data by this operation. When demodulation starts from the first line of demodulation matrix synchronizing to the receiving data of the first line of modulation matrix, α kind of demodulated data are equal one after another because of only one kind of modulation data. When demodulation starts from several sampling later than the first line of demodulation matrix but not over a sampling, the number of same demodulation data decrease according to the number of several sampling delay. When demodulation starts from over a sampling after the first line of demodulation matrix, no same demodulation data is got because the one frame time belonging to the one operation of demodulation matrix spread two frame time belonging to first modulated data matrix and of next modulated data matrix and the receiving data are constructed by first modulation data and next modulation data. This property is applied to synchronization of modulation and demodulation. The matrix, of which column is picked up from one column of demodulation matrix and is constructed other column by shifting one over-sampling interval from each other to the end of the line number of demodulation matrix, is created, and demodulation operation is applied to any receiving data from AD converter by this shifted matrix, and synchronize point is found by the columns number of same demodulated data.

[0044] The meaning of demodulation, which use the matrix composed the lines from over-sampling number of inverse matrix placed at over-sampling proper timing under the condition of synchronizing with modulation, is that there are over-sampling number of simultaneous linear equation, and over-sampling number of same modulated data are solved. The products of over-sampling demodulation matrix and receiving data matrix from AD converter are summed together, and over-sampling number times of similar modulated data are got, and this contribute the reduction of electrical circuits of multiplier and accumulator.

[0045] Next explaining the adjusting method in following

[0046] The distortion, which is created by the parameter of line such as twist-pair between terminals, which is created by sampling timing difference between DA converter and AD converter, should be adjusted to get the correct demodulated data. Before the practical communication under the circumstance of decided parameter of line or DA or AD converter, test communication is done to get the parameter of adjustment.

[0047] Modulation data of sub-carrier frequency number p are x2p+1 for cosine and x2p+2 for sine and the phase of these wave is shifted θp in the receiving data by the parameter of communication line or sampling timing difference of DA and AD converter.

[0048] The phase shifted form of the wave described as following.

x 2p+1 cos(ωpt+θp)=x2p+1 cos θp cos ωpt−x2p+1 sin θp sin ωpt

x 2p+2 sin(ωpt+θp)=x2p+2 cos θp sin ωpt−x2p+2 sin θp cos ωpt

[0049] In demodulation side, the amount of these wave is got as the receiving data, and practical demodulated data β2p+1, for cosine and β2p+2 for sine, which is demodulated by the operation of receiving data and demodulation matrix about cosine and sine independently, are got as coefficient of cos ωpt and sin ωpt. And practical demodulated data is described mathematically as following.

β2p+1=x2p+1 cos θp+x2p+2 sin θp

β2p+2=−x2p+1 sin θp+x2p+2 cos θp

[0050] Practical demodulated data of each sampling index r are described as βr,2p+1 and βr,2p+2, which is detected by the operation of partial demodulation matrix and partial receiving data matrix of each sampling index. This demodulated data are described by use of raff equal symbol because of being distorted by noise and phase shift. And equation is described as following.

β r,2p+1 ≈x 2p+1 cos θp+x2p+2 sin θp

βr,2p+2≅−x2p+1 sin θp+x2p+2 cos θp

[0051] Difference is took in spite of raff equal symbol, and amount of square of these difference is described as δp2 and is differentiated by θp to apply minimum square method. 8$\begin{array}{c}\frac{\partial }{\partial {\theta }_p}{\delta }_p^2=2\left(x_{2p+1}\sin {\theta }_p-x_{2p+2}\cos {\theta }_p\right)\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}+\\ 2\left(x_{2p+1}\cos {\theta }_p+x_{2p+2}\sin {\theta }_p\right)\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}\end{array}$

[0052] The modulation data of the test communication before practical communication is described following

x 2p+1 =x 2p+2 =x test ≢0

[0053] To get θp by applying minimum square method 9$\frac{\partial }{\partial {\theta }_p}{\delta }_p^2=0$

[0054] and get the result for θp in following 10$\tan {\theta }_p=\frac{\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}-\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}}{\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}+\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}}$

[0055] And cos θp or sinθp is calculated by tanθp.

[0056] As modulation data is determined as the mean value of over-sampling number of practical demodulation data, so is described following 11$\begin{array}{c}{x}_{2p+1}\cong \cos {\theta }_p\times \left\{\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}\right\}-\sin {\theta }_p\left\{\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}\right\}\\ x_{2p+2}\cong \sin {\theta }_p\times \left\{\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}\right\}+\cos {\theta }_p\left\{\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}\right\}\end{array}$

[0057] The modulation data xtest before the practical communication is already known at receiving side and described as following.

[0058] In the column number 2p+1

x test ≅cos θp×{overscore (D)}2p+1(test)−sin θp×{overscore (D)}2p+2(test)

[0059] In the column number 2p+2

x test ≅sin θp×{overscore (D)}2p+1(test)+cos θp×{overscore (D)}2p+2(test)

[0060] In these equation 12$\begin{array}{c}{\stackrel{\_}{D}}_{2p+1}=\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+1}\\ {\stackrel{\_}{D}}_{2p+2}=\frac{1}{\alpha }\sum _{r=1}^{\alpha }{\beta }_{r,2p+2}\end{array}$

[0061] {overscore (D)} followed by (test) mean the practical demodulated data in test communication and mean value of a demodulated data.

[0062] The demodulated data differ from the modulation data in demodulation side, and is adjusted by the way that ratio of amplitude of test communication and practical communication is equal, and adjustment equation is as following. 13$\begin{array}{c}{x}_{2p+1}->\frac{x_{\mathrm{test}}\times \left(\cos {\theta }_p\times {\stackrel{\_}{D}}_{2p+1}-\sin {\theta }_p{\stackrel{\_}{D}}_{2p+2}\right)}{\cos {\theta }_p\times {\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)-\sin {\theta }_p\times {\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)}\\ x_{2p+2}->\frac{x_{\mathrm{test}}\times \left(\sin {\theta }_p\times {\stackrel{\_}{D}}_{2p+1}+\cos {\theta }_p{\stackrel{\_}{D}}_{2p+2}\right)}{\sin {\theta }_p\times {\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)+\cos {\theta }_p\times {\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)}\end{array}$

[0063] Therefore demodulation data is adjusted from such influence of communication line.

[0064] FIG. 1 is block diagram of total system of modulation and demodulation. In modulation side, the data of modulation matrix ROM, of which address is specified by the address counter for modulation, and the modulation data are multiplied responding to cosine and sine of all sub-carrier frequency individually and are added all product to the data of DA converter.

[0065] In demodulation side, analog signal is converted by the AD converter to digital signal and is multiplied with the data of demodulation matrix ROM1, of which address is specified by the address counter for demodulation, about cosine and sine of all sub-carrier frequency individually in every sampling interval and are accumulated until the end of one modulation block, and adjusted every end of block about phase shift to the adjusted demodulated data.

[0066] About the synchronization between the address counter for modulation and address counter for demodulation, ROM named as ROM2 is picked up the memory data belonging to one carrier frequency from the demodulation ROM1, and the data of the other block of memory are moved some address each other to the end of memory address. The receiving data from AD converter is multiplied and accumulated with the memory data of cosine and sine individually in numbers of shift, and at the end of one modulation block, is adjusted about the phase shift and sent to synchronization circuit. In the synchronization circuit, the demodulated data is arranged according to the order of address shift, and the first data of same data series nearly as a is found out, and reset the address counter for demodulation adjusting the delay between the address counter and the number of shift.

[0067] FIG. 2 is block diagram of modulation. The maximum number of address counter for modulation is 2αn. Address of modulation ROM is 2αn wide and number of data buss is 2nW(word) wide. 1W of modulation ROM store Fj(i). This ROM send the data of 2nW wide responding i, which is specified as the index of sampling, to the modulation data of 2n. In every clock, the product of each modulation data and specified Fj(i) of 1W wide are summed together for all number of modulation data and is converted by DA converter to analog to the communication line. Before the practical communication, the test communication is made by the modulation data xtest

[0068] FIG. 3 is the block diagram of demodulation to get the demodulated data before adjustment of phase. Maximum address of address counter for demodulation is 2αn. Address of demodulation ROM1 is 2αn wide and data of it is 2nW wide (number of 2n of 1W wide ROM). The data of 1W of demodulation ROM1 is specified Gj(i). The analog signal from communication line is converted to digital by AD converter at same sampling interval as the clock of DA converter in modulation side.

[0069] 2nW wide data is read out from demodulation ROM1 at every clock, and every 1W related to cosine or sine of sub-carrier frequency individually is multiplied with the receiving data at this moment, and is accumulated individually until the number of 2αn, and is divided by α as the demodulated data {overscore (D)}2p+1, {overscore (D)}2p+2 before adjustment of phase.

[0070] Using the mean value of demodulated data of cosine and sine of same carrier of number p as {overscore (D)}2p+1, {overscore (D)}2p+2 drawn in FIG. 3 block diagram, FIG. 4 shows the adjustment circuit diagram of phase and magnitude.

[0071] About the basic circuit operation in FIG. 4, when the system is reset or is happen to change the parameter of adjustment according the condition of communication line, by the modulation data xtest which is determined to exchange at initial test communication by both modulation side and demodulation side, the parameter of adjustment is set. And after this operation, practical communication start and use this parameter for adjustment calculation.

[0072] The mean value of demodulation data {overscore (D)}2p+1 and {overscore (D)}2p+2 are squared by block of multiplyer1 and multiplyer2 and are added each other by adder2 and are stored by DFF1 at the end of initial test communication after system reset. And this data is sent to DFF1, DFF2 and DFF3 at only one time after initial test communication by one clock in the transmission unit frame time as 2n α as numbers conversions of DA and AD, and stored until next reset after first one.

[0073] And by the similar operation, the added value of {overscore (D)}2p+1 and {overscore (D)}2p+2 is stored in DFF2 and difference value of {overscore (D)}2p+1 and {overscore (D)}2p+2 is stored in DFF3. These three stored data and xtest of initial test data of communication are stored as the parameter of adjustment until next system reset.

[0074] As the parameter of adjustment for multiplier.7 and multiplier.8 are as following.

xtest

[0075] data stored in DFF1{overscore (D)}2p+12(test)+{overscore (D)}2p+22(test)

data stored in DFF2{overscore (D)}2p+1(test)+{overscore (D)}2p+2(test)

data stored in DFF3{overscore (D)}2p+1 (test)−{overscore (D)}2p+2(test)

[0076] In practical communication after the initial test communication, the mean value of demodulated data in every one frame {overscore (D)}2p+1 is stored in DFF4 and {overscore (D)}2p+2 is stored in DFF5 and is renewed at the interval of 2n α number of clock.

[0077] Stored data in some operation blocks is as following.

multiplier.3 ({overscore (D)}2p+1(test)+{overscore (D)}2p+2(test))×{overscore (D)}2p+1

multiplier.4 ({overscore (D)}2p+1(test)+{overscore (D)}2p+2(test))×{overscore (D)}2p+2

multiplier.5 ({overscore (D)}2p+1(test)−{overscore (D)}2p+2(test))×{overscore (D)}2p+1

multiplier.6 ({overscore (D)}2p+1(test)−{overscore (D)}2p+2 (test))×{overscore (D)}2p+2

[0078] and

difference.2 ({overscore (D)}2p+1(test)+{overscore (D)}2p+2 (test))×{overscore (D)}2p+1−({overscore (D)}2p+1(test)−{overscore (D)}2p+2 (test))×{overscore (D)}2p+2

adder.3 ({overscore (D)}2p+1(test)+{overscore (D)}2p+2(test))×{overscore (D)}2p+2+({overscore (D)}2p+1(test)−{overscore (D)}2p+2(test))×{overscore (D)}2p+1

[0079] and modulation data in test communication xtest is took in place 14$\begin{array}{cc}{x}_{\mathrm{test}}\times \left\{\begin{array}{c}\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+1}-\\ \left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)-{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+2}\end{array}\right\}& \mathrm{multiplier}.7\\ x_{\mathrm{test}}\times \left\{\begin{array}{c}\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+2}+\\ \left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)-{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+1}\end{array}\right\}& \mathrm{multiplier}.8\end{array}$

[0080] finally, the amount of squared mean value of demodulated data is took in place 15$\begin{array}{cc}\frac{x_{\mathrm{test}}\times \left\{\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+1}-\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)-{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+2}\right\}}{{\stackrel{\_}{D}}_{2p+1}^2\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}^2\left(\mathrm{test}\right)}->x_{2p+1}& \mathrm{divider}.1\\ \frac{x_{\mathrm{test}}\times \left\{\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+2}-\left({\stackrel{\_}{D}}_{2p+1}\left(\mathrm{test}\right)-{\stackrel{\_}{D}}_{2p+2}\left(\mathrm{test}\right)\right)\times {\stackrel{\_}{D}}_{2p+1}\right\}}{{\stackrel{\_}{D}}_{2p+1}^2\left(\mathrm{test}\right)+{\stackrel{\_}{D}}_{2p+2}^2\left(\mathrm{test}\right)}->x_{2p+2}& \mathrm{divider}.2\end{array}$

[0081] Therefore, the demodulated data is adjusted.

[0082] Demodulation data is got at every 2αn number of data from AD converter which is the frame of one modulation. And phase adjustment of {overscore (D)}2p+1, {overscore (D)}2p+2 in every carrier may be done at 2αn clock interval. To increase the efficiency of usage of circuit, the amount of circuit decrease by using a time sharing phase adjustment circuit.

[0083] The time sharing phase adjustment circuit is represented in FIG. 5. {overscore (D)}2p+1 and {overscore (D)}2p+2 detect and store demodulated data before phase adjustment, and sent one block by selector o to phase adjustment circuit at every one frame. In time sharing phase adjustment circuit, number of n registers in spite of DFF1, DFF2 and DFF3 which are represented in phase adjustment circuit FIG. 4 for one sub-carrier frequency, are selected one by one by selector 1 synchronized to selector 0, and are stored as the parameter of every sub-carrier in one round of selector 1 when the parameter is decided in system.

[0084] In practical communication, the parameters responding to the index of sub-carrier are selected by the selector 2 synchronizing to the selector 0 in spite of operation DFF4 and DFF5. The calculation in the circuit is done ideally by the pip-line operation. Therefore phase adjusted demodulation data are sent from the time sharing phase adjustment circuit continuously.

[0085] Demodulation circuit block diagram for synchronization is represented in FIG. 6. Address counter for demodulation is used for this circuit and output 2αn addresses. Demodulation ROM2 has 2αn addresses and 4nW wide data bus. ROM2 pick up the memory data G2p+1(i) and G2p+2(i) belonging to one carrier frequency p from the demodulation ROM1 and the data of the other block of memory are moved a address each other to the end of memory address. Data of this ROM2 is 4nW wide which is 2nW numbers of cosine data and 2nW number of sine data. In one clock interval, demodulation ROM2 output 4nW wide data, with which the data from AD converter is multiplied and accumulated by a number individually and selected as {overscore (D)}2p+1 and {overscore (D)}2p+2 to the time sharing phase adjustment circuit. Time sharing phase adjustment circuit is operated not by the half clock but by two times clock of address counter. At least, one out put of the time sharing adjustment circuit is sent to synchronization circuit represented in FIG. 7 to detect frame synchronized signal. Serise of adjusted demodulated data for synchronization are shifted by equal or less than α number of DFF, and each shifted data are compared, and synchronization signal is output in case of all equal data. This synchronization signal is shifted as long as the delay between synchronization circuit and address counter for demodulation, and reset the counter for demodulation to synchronize the counter for demodulation with the counter for modulation of the other side terminal.

[0086] About method of sub-carrier frequency determination described in claim 2, the cosine and sine wave equation of sub-carrier number p are 16$\begin{array}{c}\cos \left\{\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}\left(\alpha q+r\right)\right\}\\ \sin \left\{\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}\left(\alpha q+r\right)\right\}\end{array}$

[0087] and following equation for sub-carrier frequency reference 17$\sum _{q=0}^{\left(2n-1\right)}{\cos }^2\left\{\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}\left(\alpha q+r\right)\right\}=\sum _{q=0}^{\left(2n-1\right)}{\sin }^2\left\{\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}\left(\alpha q+r\right)\right\}$

[0088] and this equation is solved by many ƒp by which is made matrix and inverse matrix. And the difference of range in the inverse matrix elements are not so wide or so near to zero that the proper ƒp are selected.

[0089] The transmission speed is as following

[0090] The sampling clock of DA converter is CLK and most high frequency of sub-carrier is ƒ0 and ρ is sampling numbers in one wave of most high frequency of sub-carrier

CLK=ρ×α׃0=ραƒ0

[0091] The number of sampling of one frame in modulation is same as the number of address of modulation ROM, that is 2αn. The bits wide of modulation data are specified as A, then the total bits wide of modulation data are 2nA. Therefore the transmission speed is following. 18$\frac{\mathrm{CLK}}{2\alpha n}\times 2\mathrm{nA}=\mathrm{CLK}\times \frac{A}{\alpha }$

[0092] Another method of synchronization block diagram is represented in FIG. 8. Although the modulation data are same in first two round address for modulation and same in second two round address of modulation, the modulation data of the sub-carrier which is specified as the use of synchronization should be different in first two round address from in second two round address. The data of demodulation ROM1 which is used for synchronization is called as synchronization ROM. The address of synchronization ROM is connected to the continuous address counter.

[0093] The product of the data from AD converter and the data of synchronization ROM is accumulated for the one round address of demodulation circuit, and the accumulator, which start accumulation from every address for one round addresses to output result continuously, is installed in synchronization circuit. These value of the accumulator after multiplying are not different from each other for the term of same modulation data, but are different from each other for the term of the different modulation data. In synchronization circuit, this property contribute to make synchronization signal which is output by the comparator indication the equality or the difference between two series adjusted demodulated data. Multiplier and accumulator starting from every address is represented in FIG. 9.

[0094] The data from AD converter and the data of synchronization ROM are multiplied by the circuit of multiplier, and send to the circuit of accumulator. The output of accumulator is sent to DFF6 by every clock, and is returned to accumulator to be added with next data one after another.

[0095] The carry-out signal, which is output at every one round of address counter, reset DFF6, and another DFF7 store the last accumulated value as the data of accumulation. This accumulating operation is same as in demodulation circuit.

[0096] Until next accumulation from previous this one, the accumulator, which start accumulation from every address for one round addresses, is operated as following. The accumulated data until this time of previous round in DFF8 is subtracted from the previous accumulated data in DFF7 and is added by newly accumulated data until this time in DFF6, and putout this data at every address.

[0097] To achieve this operation, dual-port RAM, of which highest write address bit is connected through TFF to carry-out of address counter and the lower address is connected to address counter output, and of which read address is similar to write address with inverted highest address, output the previous round data, which are accumulated and stored in DFF8, and above subscription is got.

[0098] Watching whether the number of address counter for demodulation is continuous or not at synchronization, the demodulation data is adjusted in case of over-ride by subscripting the product and incase of less number adding the product.

EXAMPLE

[0099] Number of carrier frequency n=4

[0100] Number of over-sampling α=4

[0101] Kind of wave s s=1 indicate cosine wave s=2 indicate sine wave

[0102] about modulation matrix

[0103] number of line i i=1˜32

[0104] number of column j j=1˜8

[0105] sub-carrier frequency number p p=0˜3

[0106] Original sampling order q q=0˜7

[0107] Order of over-sampling r r=1˜4

i=αq+r= 4q+r

j= 2p+s

[0108] the elements of matrix

F i (i)=F2p+s(4q+r)

[0109] Number of original sampling in one complete wave form ρ=2.399 19$\begin{array}{cc}{F}_{2p+s}\left(4q+r\right)=\cos \left\{\frac{2\pi f_p}{9.596f_0}\left(4q+r\right)\right\}& \mathrm{in}\mathrm{case}\mathrm{of}s=1\\ \sin \left\{\frac{2\pi f_p}{9.596f_0}\left(4q+r\right)\right\}& \mathrm{in}\mathrm{case}\mathrm{of}s=2\end{array}$

[0110] f0=1.0423 MHz

[0111] f1=0.7809 MHz

[0112] f2=0.6255 MHz

[0113] f3=0.4684 MHz

[0114] basic sampling interval 383.7 nSec

[0115] over-sampling interval 95.9 nSec

demodulation ROM2(conbined ROM for synchronization)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	r	i	1	2	3	4	5	6	7	8
0	1	1	9D62	8CD2	8CD2	AC89	AC89	9C5E	9C5E	7AA0
	2	2	97C8	97FB	97FB	9FE6	9FE6	AA6B	AA6B	6DA9
	3	3	8C8B	9D6B	9D6B	8E22	8E22	B0DB	B0DB	650B
	4	4	8051	9AE3	9AE3	7B6D	7B6D	AE2A	AE2A	6216
1	1	5	8CD2	AC89	AC89	9C5E	9C5E	7AA0	7AA0	AF18
	2	6	97FB	9FE6	9FE6	AA6B	AA6B	6DA9	6DA9	A655
	3	7	9D6B	8E22	8E22	B0DB	B0DB	650B	650B	9945
	4	8	9AE3	7B6D	7B6D	AE2A	AE2A	6216	6216	89E8
2	1	9	AC89	9C5E	9C5E	7AA0	7AA0	AF18	AF18	7BD9
	2	10	9FE6	AA6B	AA6B	6DA9	6DA9	A655	A655	7DB4
	3	11	8E22	B0DB	B0DB	650B	650B	9945	9945	80A2
	4	12	7B6D	AE2A	AE2A	6216	6216	89E8	89E8	8461
3	1	13	9C5E	7AA0	7AA0	AF18	AF18	7BD9	7BD9	85E0
	2	14	AA6B	6DA9	6DA9	A655	A655	7DB4	7DB4	81E8
	3	15	B0DB	650B	650B	9945	9945	80A2	80A2	7EA6
	4	16	AE2A	6216	6216	89E8	89E8	8461	8461	7C62
4	1	17	7AA0	AF18	AF18	7BD9	7BD9	85E0	85E0	9D62
	2	18	6DA9	A655	A655	7DB4	7DB4	81E8	81E8	97C8
	3	19	650B	9945	9945	80A2	80A2	7EA6	7EA6	8C8B
	4	20	6216	89E8	89E8	8461	8461	7C62	3E98	EE06
5	1	21	AF18	7BD9	7BD9	85E0	85E0	9D62	9D62	8CD2
	2	22	A655	7DB4	7DB4	81E8	81E8	97C8	97C8	97FB
	3	23	9945	80A2	80A2	7EA6	7EA6	8C8B	8C8B	9D6B
	4	24	89E8	8461	8461	7C62	3E98	EE06	8051	9AE3
6	1	25	7BD9	85E0	85E0	9D62	9D62	8CD2	8CD2	AC89
	2	26	7DB4	81E8	81E8	97C8	97C8	97FB	97FB	9FE6
	3	27	80A2	7EA6	7EA6	8C8B	8C8B	9D6B	9D6B	8E22
	4	28	8461	7C62	3E98	EE06	8051	9AE3	9AE3	7B6D
7	1	29	85E0	9D62	9D62	8CD2	8CD2	AC89	AC89	9C5E
	2	30	81E8	97C8	97C8	97FB	97FB	9FE6	9FE6	AA6B
	3	31	7EA6	8C8B	8C8B	9D6B	9D6B	8E22	8E22	B0DB
	4	32	3E98	EE06	8051	9AE3	9AE3	7B6D	7B6D	AE2A

[0116]

demodulation ROM2(conbined ROM for synchronization)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	r	i	1	2	3	4	5	6	7	8
0	1	1	9D62	8CD2	8CD2	AC89	AC89	9C5E	9C5E	7AA0
	2	2	97C8	97FB	97FB	9FE6	9FE6	AA6B	AA6B	6DA9
	3	3	8C8B	9D6B	9D6B	8E22	8E22	B0DB	B0DB	650B
	4	4	8051	9AE3	9AE3	7B6D	7B6D	AE2A	AE2A	6216
1	1	5	8CD2	AC89	AC89	9C5E	9C5E	7AA0	7AA0	AF18
	2	6	97FB	9FE6	9FE6	AA6B	AA6B	6DA9	6DA9	A655
	3	7	9D6B	8E22	8E22	B0DR	B0DB	650B	650B	9945
	4	8	9AE3	7B6D	7B6D	AE2A	AE2A	6216	6216	89E8
2	1	9	AC89	9C5E	9C5E	7AA0	7AA0	AF18	AF18	7BD9
	2	10	9FE6	AA6B	AA6B	6DA9	6DA9	A655	A655	7DB4
	3	11	8E22	B0DB	B0DB	650B	650B	9945	9945	80A2
	4	12	7B6D	AE2A	AE2A	6216	6216	89E8	89E8	8461
3	1	13	9C5E	7AA0	7AA0	AF18	AF18	7BD9	7BD9	85E0
	2	14	AA6B	6DA9	6DA9	A655	A655	7DB4	7DB4	81E8
	3	15	B0DB	650B	650B	9945	9945	80A2	80A2	7EA6
	4	16	AE2A	6216	6216	89E8	89E8	8461	8461	7C62
4	1	17	7AA0	AF18	AF18	7BD9	7BD9	85E0	85E0	9D62
	2	18	6DA9	A655	A655	7DB4	7DB4	81E8	81E8	97C8
	3	19	650B	9945	9945	80A2	80A2	7EA6	7EA6	8C8B
	4	20	6216	89E8	89E8	8461	8461	7C62	3E98	EE06
5	1	21	AF18	7BD9	7BD9	85E0	85E0	9D62	9D62	8CD2
	2	22	A655	7DB4	7DB4	81E8	81E8	97C8	97C8	97FB
	3	23	9945	80A2	80A2	7EA6	7EA6	8C8B	8C8B	9D6B
	4	24	89E8	8461	8461	7C62	3E98	EE06	8051	9AE3
6	1	25	7BD9	85E0	85E0	9D62	9D62	8CD2	8CD2	AC89
	2	26	7DB4	81E8	81E8	97C8	97C8	97FB	97FB	9FE6
	3	27	80A2	7EA6	7EA6	8C8B	8C8B	9D6B	9D6B	8E22
	4	28	8461	7C62	3E98	EE06	8051	9AE3	9AE3	7B6D
7	1	29	85E0	9D62	9D62	8CD2	8CD2	AC89	AC89	9C5E
	2	30	81E8	97C8	97C8	97FB	97FB	9FE6	9FE6	AA6B
	3	31	7EA6	8C8B	8C8B	9D6B	9D6B	8E22	8E22	B0DB
	4	32	3E98	EE06	8051	9AE3	9AE3	7B6D	7B6D	AE2A

[0117]

demodulation ROM2-4(for synchronization)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	8051	9AE3	7B6D	AE2A	6216	89E8	8461	7C62
1	9AE3	7B6D	AE2A	6216	89E8	8461	7C62	8051
2	7B6D	AE2A	6216	89E8	8461	7C62	8051	9AE3
3	AE2A	6216	89E8	8461	7C62	8051	9AE3	7B6D
4	6216	89E8	8461	7C62	8051	9AE3	7B6D	AE2A
5	89E8	8461	7C62	8051	9AE3	7B6D	AE2A	6216
6	8461	7C62	8051	9AE3	7B6D	AE2A	6216	89E8
7	7C62	8051	9AE3	7B6D	AE2A	6216	89E8	8461

[0118] these four demodulation ROM are conbined to one by the method descrived in this example

demodulation ROM2-1(for synchronization, p = 0 block of
ROM1 is arranged address incrementally)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	9D62	8CD2	AC89	9C5E	7AA0	AF18	7BD9	85E0
1	8CD2	AC89	9C5E	7AA0	AF18	7BD9	85E0	9D62
2	AC89	9C5E	7AA0	AF18	7BD9	85E0	9D62	8CD2
3	9C5E	7AA0	AF18	7BD9	85E0	9D62	8CD2	AC89
4	7AA0	AF18	7BD9	85E0	9D62	8CD2	AC89	9C5E
5	AF18	7BD9	85E0	9D62	8CD2	AC89	9C5E	7AA0
6	7BD9	85E0	9D62	8CD2	AC89	9C5E	7AA0	AF18
7	85E0	9D62	8CD2	AC89	9C5E	7AA0	AF18	7BD9

[0119]

demodulation ROM2-2(for synchronization)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	97C8	97FB	9FE6	AA6B	6DA9	A655	7DB4	81E8
1	97FB	9FE6	AA6B	6DA9	A655	7DB4	81E8	97C8
2	9FE6	AA6B	6DA9	A655	7DB4	81E8	97C8	97FB
3	AA6B	6DA9	A655	7DB4	81E8	97C8	97FB	9FE6
4	6DA9	A655	7DB4	81E8	97C8	97FB	9FE6	AA6B
5	A655	7DB4	81E8	97C8	97FB	9FE6	AA6B	6DA9
6	7DB4	81E8	97C8	97FB	9FE6	AA6B	6DA9	A655
7	81E8	97C8	97FB	9FE6	AA6B	6DA9	A655	7DB4

[0120]

demodulation ROM2-3(for synchronization)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	8C8B	9D6B	8E22	B0DB	650B	9945	80A2	7EA6
1	9D6B	8E22	B0DB	650B	9945	80A2	7EA6	8C8B
2	8E22	B0DB	650B	9945	80A2	7EA6	8C8B	9D6B
3	B0DB	650B	9945	80A2	7EA6	8C8B	9D6B	8E22
4	650B	9945	80A2	7EA6	8C8B	9D6B	8E22	B0DB
5	9945	80A2	7EA6	8C8B	9D6B	8E22	B0DB	650B
6	80A2	7EA6	8C8B	9D6B	8E22	B0DB	650B	9945
7	7EA6	8C8B	9D6B	8E22	B0DB	650B	9945	80A2

[0121] to combine these four demodulation ROM of which data placed at timing proper over-sampling poditic

demodulation ROM1(convined data of 4 ROMs)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	r	i	1	2	3	4	5	6	7	8
0	1	1	9D62	997B	B890	AF21	B887	AF2C	9D5F	997E
	2	2	97C8	8F11	AB0D	95FE	AB0A	9606	97C7	8F13
	3	3	8C8B	829F	8FED	77F6	8FF2	77F7	8C8D	829F
	4	4	8051	794B	726B	6175	7274	616F	8055	7949
1	1	5	8CD2	960D	9094	A6DE	908D	A6DF	8CD0	960D
	2	6	97FB	9CEC	AB83	B772	AB79	B77A	97F7	9CEF
	3	7	9D6B	9C08	B8A5	B549	B89B	B554	9D68	9C0B
	4	8	9AE3	93BE	B28B	A147	B286	A151	9AE2	93C1
2	1	9	AC89	A7C5	C013	C67C	BC7F	A548	A8F2	8674
	2	10	9FE6	89B7	99AC	903D	84E5	7B3E	8B0C	74A5
	3	11	8E22	6BC3	6F9D	588F	4E89	54B8	6CF0	67E9
	4	12	7B6D	54FB	4BD1	2C95	263E	3ACF	55BA	6341
3	1	13	9C5E	C288	CE26	EE2C	F38D	DC95	C1E6	B0E2
	2	14	AA6B	C9D6	DF89	FECC	FED7	DFA4	C9D5	AA92
	3	15	B0DB	C21D	DCC6	F3E7	EE98	CE87	C2BD	9C9C
	4	16	AE2A	AD31	C685	D00F	C6A7	AD48	AE4C	8A4B
4	1	17	7AA0	4A52	24CB	0B29	0A60	1643	3AAC	6533
	2	18	6DA9	3CA4	14B6	0089	008B	14E7	3CD9	6DF2
	3	19	650B	3AC7	1689	0AE5	0BB3	256C	4AD0	7AFF
	4	20	6216	4505	29FE	28A9	2A23	454E	626F	8A5C
5	1	21	AFI8	BA97	C855	BF2F	BD43	A4C7	944D	7AAC
	2	22	A655	9E73	9CC5	8A81	886D	765D	7516	6DB3
	3	23	9945	7F37	6E5F	55C5	53DB	4AF7	5916	6510
	4	24	89E8	61A6	4436	2907	2791	2935	4491	6216
6	1	25	7BD9	6FD3	63CC	6B74	7B6F	8F46	9374	939A
	2	26	7DB4	776C	7737	8187	923E	A0B3	9CB0	968D
	3	27	80A2	80A0	849C	9857	A85B	B02F	A455	9870
	4	28	8461	8AA7	967B	ADF0	BBE0	BC66	A9B9	9918
7	1	29	85E0	73E0	5AAE	429D	3DB5	4D55	68F1	7E95
	2	30	81E8	6D32	5198	3CC8	3CB9	516F	6D11	81D2
	3	31	7EA6	6902	4D5F	3D9B	4266	5A69	73B1	85C6
	4	32	7C62	67AB	4E60	4503	4E3E	677E	7C40	8A1B

[0122] the circuit block diagram which use demodulation ROM1 conbined data in number of over-sampling represented in FIG. 5, and output the demodulation data which is accumulated and divided by α.

demodulation ROM1-4(data of demodulation matrix4
exchanged to positive Hex. data)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	8051	794B	726B	6175	7274	616F	8055	7949
1	9AE3	93BE	B28B	A147	B286	A151	9AE2	93C1
2	7B6D	54FB	4BD1	2C95	263E	3ACF	55BA	6341
3	AE2A	AD31	C685	D00F	C6A7	AD48	AE4C	8A4B
4	6216	4505	29FE	28A9	2A23	454E	626F	8A5C
5	89E8	61A6	4436	2907	2791	2935	4491	6216
6	8461	8AA7	967B	ADF0	BBE0	BC66	A9B9	9918
7	7C62	67AB	4E60	4503	4E3E	677E	7C40	8A1B

[0123] before the multiplication, data stored in ROM is exchanged to the number indicating positive or negat

[0124] also the modulation data is exchanged to the number having positive signe.

[0125] where Di is 8 bit modulation data, equation of exchange is

2×Di−255

[0126] when the result of calculation prosess is output, the data is done by inverse exchange.

demodulation ROM1-1(data of demodulation matrix1
exchanged to positive Hex. data)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	9D62	997B	B890	AF21	B887	AF2C	9D5F	997E
1	8CD2	960D	9094	A6DE	908D	A6DF	8CD0	960D
2	AC89	A7C5	C013	C67C	BC7F	A548	A8F2	8674
3	9C5E	C288	CE26	EE2C	F38D	DC95	C1E6	B0E2
4	7AA0	4A52	24CB	0B29	0A60	1643	3AAC	6533
5	AF18	BA97	C855	BF2F	BD43	A4C7	944D	7AAC
6	7BD9	6FD3	63CC	6B74	7B6F	8F46	9374	939A
7	85E0	73E0	5AAE	429D	3DB5	4D55	68F1	7E95

[0127]

demodulation ROM1-2(data of demodulation matrix2
exchanged to positive Hex. data)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	97C8	8F11	AB0D	95FE	AB0A	9606	97C7	8F13
1	97FB	9CEC	AB83	B772	AB79	B77A	97F7	9CEF
2	9FE6	89B7	99AC	903D	84E5	7B3E	8B0C	74A5
3	AA6B	C9D6	DF89	FECC	FED7	DFA4	C9D5	AA92
4	6DA9	3CA4	14B6	0089	008B	14E7	3CD9	6DF2
5	A655	9E73	9CC5	8A81	886D	765D	7516	6DB3
6	7DB4	776C	7737	8187	923E	A0B3	9CB0	968D
7	81E8	6D32	5198	3CC8	3CB9	516F	6D11	81D2

[0128]

demodulation ROM1-3(data of demodulation matrix3
exchanged to positive Hex. data)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	8C8B	829F	8FED	77F6	8FF2	77F7	8C8D	829F
1	9D6B	9C08	B8A5	B549	B89B	B554	9D68	9C0B
2	8E22	6BC3	6F9D	588F	4E89	54B8	6CF0	67E9
3	B0DB	C21D	DCC6	F3E7	EE98	CE87	C2BD	9C9C
4	650B	3AC7	1689	0AE5	0BB3	256C	4AD0	7AFF
5	9945	7F37	6E5F	55C5	53DB	4AF7	5916	6510
6	80A2	80A0	849C	9857	A85B	B02F	A455	9870
7	7EA6	6902	4D5F	3D9B	4266	5A69	73B1	85C6

[0129]

stored data in modulation ROM
(data of modulation matrix exchanged to positive Hex. data)
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	r	i	1	2	3	4	5	6	7	8
0	1	1	E584	CDF5	F0E5	BC50	F63D	B105	FA7E	A521
	2	2	A107	FBA9	C728	EA65	DA73	DA90	EA75	C710
	3	3	4EE0	F632	8CA1	FF5F	B0DF	F64D	D144	E2E3
	4	4	110C	BFD2	4F1F	F64C	7FD6	FFFF	B116	F636
1	1	5	0121	6F0A	1D25	D14F	4ED4	F62D	8CAF	FF5E
	2	6	25B5	2546	027E	9923	2552	DA56	6731	FD92
	3	7	6FA5	010D	0574	5B08	09A3	B0B8	43D6	F0FA
	4	8	C05A	115A	2555	25A6	0000	7FAD	25A6	DAAA
2	1	9	F66D	4F70	5A9A	0596	09E2	4EAE	0F3C	BC8F
	2	10	FB80	A19E	98B1	0268	25C6	2535	0284	993F
	3	11	CD79	E5E3	D0F6	1CDC	4F6D	0993	0096	73C3
	4	12	7F63	FFFF	F620	4EB4	807B	0000	099D	4F54
3	1	13	318E	E524	FF6A	8C2E	B177	09F2	1CD3	2F15
	2	14	042E	A070	EAA5	C6C8	DAE7	25E4	388F	15CA
	3	15	0A0A	4E4F	BCB5	F0AF	F67B	4F93	5A70	05A3
	4	16	40B5	10BE	8073	FFFF	FFFF	80A4	7F8C	0000
4	1	17	9190	0136	4415	F11B	F5FD	B19D	A4B2	0560
	2	18	DB27	2624	15DB	C788	D9FE	DB04	C6B0	154A
	3	19	FF06	7040	00AB	8D14	B046	F68B	E29A	2E62
	4	20	EE56	C0E1	0987	4F89	7F32	FFFE	F609	4E7F
5	1	21	AFFE	F6A8	2E57	1D6E	4E3C	F5ED	FF52	72DD
	2	22	5DCA	FB57	666B	0295	24DE	D9E1	FDA8	985D
	3	23	19BE	CCFC	A489	0553	0964	B020	F130	BBC4
	4	24	0001	7EC7	DA07	2503	0001	7F08	DAFC	DA07
6	1	25	1B3B	3112	FA47	5A2B	0A22	4E17	BCF5	F08C
	2	26	6027	0406	FDAD	9840	263B	24C1	99B0	FD64
	3	27	B240	0A47	E36C	D09C	5005	0955	7435	FF74
	4	28	EF8E	413D	B1B5	F5F3	8120	0001	4FBF	F68D
7	1	29	FEB3	922B	7444	FF75	B20E	0A32	2F6E	E375
	2	30	D96B	DB95	3997	EAE4	DB5B	2659	160B	C7CF
	3	31	8F23	FF19	0F87	BD1B	F6B9	502B	05C5	A5FD
	4	32	3E98	EE06	0001	80E6	FFFD	8149	0001	80E6

[0130] and above data are delayed one over-sampling and demodulated using the demodulation matrix 1˜4 the mean value of demodulation data are

	q	r	j	xj
	0	1	1	3.9847
		2	2	7.2244
	1	1	3	−2.1027
		2	4	−10.1946
	2	1	5	1.5695
		2	6	11.9217
	3	1	7	−1.3175
		2	8	−13.1774

[0131] the out put adjusted data by which is mentioned adjustment circuit in this paper using above adjustment parameter

	q	r	j	xj
	0	1	1	1.0945
		2	2	14.9236
	1	1	3	−0.679
		2	4	−14.8599
	2	1	5	1.0464
		2	6	15.1295
	3	1	7	−1.0984
		2	8	−15.1392

[0132] above data is rounded as below

	q	r	j	xj
	0	1	1	1
		2	2	15
	1	1	3	−1
		2	4	−15
	2	1	5	1
		2	6	15
	3	1	7	−1
		2	8	−15

[0133] this demodulation data is same as the modulation data of transmission side.

[0134] above data are changed a little by the noise of line to demodulation circuit

i  di
1  3.4752
2  3.8076
3  0.2641
4  −6.2598
5  −13.2246
6  −18.1845
7  −17.6699
8  −12.0553
9  −3.1223
10 6.2118
11 11.5807
12 11.6888
13 5.5937
14 −2.9461
15 −10.6135
16 −12.4051
17 −6.4104
18 5.6919
19 21.8561
20 34.7286
21 40.1087
22 35.2151
23 19.0815
24 −3.6546
25 −26.993
26 −44.5621
27 −52.648
28 −49.4096
29 −36.3798
30 −18.107
31 0.7936
32 15.1676

[0135] modulation data are as x1=x5=x6=15, x3=x7=−1, x4=x8=−15 in practical communication, modulaed data are

i  di
1  3.8853
2  0.4624
3  −6.1088
4  −13.2972
5  −17.9469
6  −17.698
7  −12.1194
8  −3.0384
9  6.1155
10 11.7103
11 11.4849
12 5.6252
13 −3.1445
14 −10.5474
15 −12.4635
16 −6.6923
17 5.9496
18 21.6735
19 34.9428
20 40.4428
21 35.062
22 19.1293
23 −3.5679
24 −26.9999
25 −44.8891
26 −52.7427
27 −49.1863
28 −36.1509
29 −17.9151
30 0.5586
31 15.3163
32 3.3394

[0136] and above data are delayed one over-sampling and demodulated using the demodulation matrix 1˜4 the mean value of demodulation data are

	q	r	j	xj
	0	1	1	10.9686
		2	2	4.0607
	1	1	3	12.015
		2	4	8.7172
	2	1	5	12.6055
		2	6	11.1354
	3	1	7	13.4383
		2	8	12.7259

[0137] the parameters of adjustment data are determined as

p {overscore (D)}2p+12(test) + {overscore (D)}2p+22(test)
0 136.8002
1 220.3448
2 282.8956
3 342.5367
p {overscore (D)}2p+1(test) + {overscore (D)}2p+2(test)
0 15.0293
1 20.7322
2 23.7409
3 26.1642
p {overscore (D)}2p+1(test) − {overscore (D)}2p+2(test)
0 6.908
1 3.2977
2 1.4702
3 0.7124

[0138] above data are changed a little by the noise of line to demodulation circuit

i  di
1  79.7745
2  81.1090
3  65.0050
4  37.0460
5  5.6597
6  −21.4443
7  −37.4286
8  −41.5717
9  −36.3611
10 −26.2757
11 −17.1823
12 −11.3325
13 −10.1673
14 −10.4529
15 −9.9276
16 −5.3161
17 3.3021
18 12.8503
19 21.3957
20 23.7096
21 19.4529
22 10.3367
23 −1.1009
24 −9.2484
25 −10.4869
26 −3.8698
27 7.3148
28 18.5145
29 24.5774
30 21.4752
31 9.2918
32 −9.5909

[0139] modulated data for DA converter input

i  di
1  81.1867
2  65.2033
3  37.1970
4  5.5872
5  −21.2066
6  −37.4566
7  −41.6358
8  −36.2772
9  −26.3720
10 −17.0527
11 −11.5364
12 −10.1358
13 −10.6513
14 −9.8615
15 −5.3745
16 3.0202
17 13.1080
18 21.2131
19 23.9238
20 19.7870
21 10.1836
22 −1.0532
23 −9.1617
24 −10.4938
25 −4.1968
26 7.2201
27 18.7377
28 24.8063
29 21.6671
30 9.0569
31 −9.4422
32 79.6386

[0140] the frequency of sub-carriers is determined as below

[0141] r=1 α=4 ρf0=2.5×10 and according to below equation 20$\sum _{q=0}^{n-1}{\cos }^2\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}=\sum _{q=0}^{n-1}{\sin }^2\frac{2\pi f_{\rho }}{\rho \times \alpha \times f_0}$

[0142] ƒ0=1.0423 MHz

[0143] ƒ1=0.7809 MHz

[0144] ƒ2=0.6255 MHz

[0145] ƒ3=0.4684 MHz

[0146] therefore ρ=2.399 is got.

[0147] if the bit wide of the modulation data is only one bit, the trancemission speed is 21$2.399\times 4\times 1.0423\times \frac{1}{4}=2.5\mathrm{Mbps}$

[0148] elements data of modulation matris and demodulation matrix 1˜4 should be changed to positive hex number to store in ROM, and the example method about cos θ is descrived as following 22$\frac{\cos \theta +1}{2}\times 65535$$\frac{\begin{array}{c}\begin{array}{c}\text{data of demodulati on matrix}+\\ \text{(absolute maximum negative}\end{array}\\ \text{data of demodulati on matrix)}\end{array}}{\begin{array}{c}\text{(absolute maximum negative}\\ \text{data of demodulati on matrix)}\end{array}\times 2}\times 65535$

[0149] by above equation, cos θ values of modulation matrix and of demodulation matris 1˜4 are changed to positive dezimal number and are changed to hex number and are stored in ROM.

[0150] each address of ROMS are i 1 and q and the number of port is j and 16 bits wide in this example.

[0151] at first in test communication, modulation is done as all modulation data are 15(F)

x1=x2=x3= . . . x8=15

[0152]

demodulation matrix 2
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	0.3351	0.1206	0.8091	0.2909	0.8088	0.2916	0.3351	0.1209
1	0.3403	0.4618	0.8213	1.1147	0.8203	1.1154	0.3400	0.4621
2	0.5350	−0.0107	0.3819	0.1500	−0.1295	−0.3669	0.0219	−0.5293
3	0.7938	1.5670	2.1010	2.8705	2.8715	2.1036	1.5669	0.7976
4	−0.7012	−1.9079	−2.8909	−3.3878	−3.3876	−2.8863	−1.9030	−0.6944
5	0.6936	0.5000	0.4588	0.0094	−0.0421	−0.4867	−0.5184	−0.7003
6	−0.3065	−0.4610	−0.5643	−0.2119	0.1997	0.5554	0.4565	0.3052
7	−0.2032	−0.7132	−1.3929	−1.9051	−1.9064	−1.3964	−0.7161	−0.2052

[0153]

demodulation matrix 3
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	0.0585	−0.1856	0.1414	−0.4483	0.1418	−0.4482	0.0586	−0.1856
1	0.4740	0.4398	1.1442	1.0612	1.1432	1.0622	0.4737	0.4401
2	0.0979	−0.7478	−0.6531	−1.2202	−1.4673	−1.3148	−0.7190	−0.8427
3	0.9522	1.3771	2.0331	2.6026	2.4718	1.6826	1.3924	0.4541
4	−0.9133	−1.9539	−2.8462	−3.1332	−3.1132	−2.4799	−1.5594	−0.3733
5	0.3722	−0.2687	−0.6832	−1.2887	−1.3362	−1.5549	−1.2076	−0.9129
6	−0.2344	−0.2343	−0.1359	0.3499	0.7442	0.9366	0.6446	0.3516
7	−0.2834	−0.8163	−1.4967	−1.8847	−1.7665	−1.1753	−0.5529	−0.1078

[0154]

demodulation matrix4
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	−0.2423	−0.4151	−0.5848	−1.0019	−0.5839	−1.0024	−0.2420	−0.4153
1	0.4116	0.2357	0.9936	0.5686	0.9931	0.5695	0.4114	0.2360
2	−0.3624	−1.3085	−1.5340	−2.3026	−2.4589	−1.9525	−1.2902	−0.9572
3	0.8860	0.8623	1.4855	1.7206	1.4888	0.8646	0.8893	0.0034
4	−0.9862	−1.7021	−2.3676	−2.4008	−2.3642	−4.6954	−0.9780	0.0047
5	−0.0059	−0.9965	−1.7211	−2.3903	−2.4266	−2.3861	−1.7128	−0.9862
6	−0.1421	0.0126	0.3041	0.8816	1.2246	1.2372	0.7773	0.3678
7	−0.3392	−0.8491	−1.4717	−1.7021	−1.4747	−0.8531	−0.3421	−0.0012

[0155] method of demodulation matrix creation

[0156] for example, matrix of which size is 8 columns is created by picking the line number r=1

	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	0.7931	0.6091	0.8820	0.4712	0.9238	0.3830	0.9570	0.2901
1	−0.9912	−0.1326	−0.7723	0.6353	−0.3841	0.9233	0.0990	0.9951
2	0.9253	−0.3791	−0.2922	−0.9564	−0.9228	−0.3852	−0.8811	0.4730
3	−0.6132	0.7900	0.9955	0.0951	0.3863	−0.9224	−0.7747	−0.6324
4	0.1377	−0.9905	−0.4680	0.8837	0.9219	0.3874	0.2870	−0.9579
5	0.3744	0.9273	−0.6380	−0.7700	−0.3885	0.9214	0.9948	−0.1022
6	−0.7868	−0.6172	0.9553	−0.2956	−0.9210	−0.3896	0.4758	0.8796
7	0.9898	0.1428	−0.0916	0.9958	0.3907	−0.9205	−0.6299	0.7767

[0157] the demodulation matrix is inverse matrix of the above matrix

demodulation matrix 1
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	1	2	3	4	5	6	7	8
0	0.4731	0.3770	1.1419	0.9096	1.1411	0.9106	0.4728	0.3773
1	0.0658	0.2928	0.1586	0.7069	0.1580	0.7070	0.0656	0.2929
2	0.8459	0.7289	1.3268	1.4849	1.2389	0.6677	0.7577	−0.0911
3	0.4480	1.3872	1.6732	2.4612	2.5938	2.0283	1.3717	0.9529
4	−0.3821	−1.5709	−2.4948	−3.1259	−3.1454	−2.8527	−1.9564	−0.9097
5	0.9092	1.1926	1.5310	1.3061	1.2585	0.6558	0.2499	−0.3810
6	−0.3523	−0.6481	−0.9441	−0.7554	−0.3619	0.1264	0.2291	0.2326
7	−0.1056	−0.5488	−1.1693	−1.7617	−1.8824	−1.4975	−0.8178	−0.2849

[0158]

modulation matrix
	p
	0	1	2	3
	r
	1	2	1	2	1	2	1	2
	j
q	r	i	1	2	3	4	5	6	7	8
0	1	1	0.7931	0.6091	0.8820	0.4712	0.9238	0.3830	0.9570	0.2901
	2	2	0.2580	0.9661	0.5559	0.8312	0.7067	0.7075	0.8317	0.5552
	3	3	−0.3839	0.9234	0.0987	0.9951	0.3818	0.9242	0.6349	0.7726
	4	4	−0.8669	0.4985	−0.3819	0.9242	−0.0012	1.0000	0.3834	0.9236
1	1	5	−0.9912	−0.1326	−0.7723	0.6353	−0.3841	0.9233	0.0990	0.9951
	2	6	−0.7053	−0.7089	−0.9805	0.1964	−0.7084	0.7058	−0.1939	0.9810
	3	7	−0.1276	−0.9918	−0.9574	−0.2888	−0.9247	0.3807	−0.4702	0.8826
	4	8	0.5030	−0.8643	−0.7084	−0.7058	−1.0000	−0.0024	−0.7060	0.7082
2	1	9	0.9253	−0.3791	−0.2992	−0.9564	−0.9228	−0.3852	−0.8811	0.4730
	2	10	0.9648	0.2629	0.1929	−0.9812	−0.7050	−0.7092	−0.9804	0.1970
	3	11	0.6050	0.7962	0.6325	−0.7746	−0.3796	−0.9251	−0.9954	−0.0958
	4	12	−0.0051	1.0000	0.9228	−0.3852	0.0036	−1.0000	−0.9248	−0.3805
3	1	13	−0.6132	0.7900	0.9955	0.0951	0.3863	−0.9224	−0.7747	−0.6324
	2	14	−0.9675	0.2530	0.8332	0.5530	0.7101	−0.7041	−0.5579	−0.8299
	3	15	−0.9214	−0.3886	0.4744	0.8803	0.9256	−0.3785	−0.2931	−0.9561
	4	16	−0.4941	−0.8694	0.0036	1.0000	1.0000	0.0048	−0.0032	−1.0000
4	1	17	0.1377	−0.9905	−0.4680	0.8837	0.9219	0.3874	0.2870	−0.9579
	2	18	0.7125	−0.7017	−0.8292	0.5589	0.7033	0.7109	0.5526	−0.8335
	3	19	0.9925	−0.1225	−0.9948	0.1022	0.3774	0.9261	0.7706	−0.6373
	4	20	0.8617	0.5074	−0.9256	−0.3785	−0.0060	1.0000	0.9223	−0.3864
5	1	21	0.3744	0.9273	−0.6380	−0.7700	−0.3885	0.9214	0.9948	−0.1022
	2	22	−0.2679	0.9635	−0.1999	−0.9798	−0.7118	0.7024	0.9816	0.1908
	3	23	−0.7993	0.6009	0.2854	−0.9584	−0.9265	0.3763	0.8841	0.4673
	4	24	−0.9999	−0.0102	0.7033	−0.7109	−1.0000	−0.0072	0.7105	0.7037
6	1	25	−0.7868	−0.6172	0.9553	−0.2956	−0.9210	−0.3896	0.4758	0.8796
	2	26	−0.2481	−0.9687	0.9819	0.1894	−0.7016	−0.7126	0.2002	0.9798
	3	27	0.3933	−0.9194	0.7768	0.6297	−0.3752	−0.9270	−0.0927	0.9957
	4	28	0.8719	−0.4896	0.3885	0.9215	0.0084	−1.0000	−0.3775	0.9260
7	1	29	0.9898	0.1428	−0.0916	0.9958	0.3907	−0.9205	−0.6299	0.7767
	2	30	0.6980	0.7161	−0.5500	0.8352	0.7135	−0.7007	−0.8281	0.5605
	3	31	0.1174	0.9931	−0.8786	0.4775	0.9274	−0.3740	−0.9551	0.2962
	4	32	−0.5118	0.8591	−1.0000	0.0072	1.0000	0.0096	−1.0000	0.0064

EXAMPLE

[0159] [Effect of Invention]

[0160] The effect of this invention applied to DSL of metal twist pair is described below. The parameter of the modulation and demodulation system is differ from example and determined below.

Number of carrier frequency      n = 16
Number of over-sampling          α = 8
Bit wide of modulation data      A = 8
Numbers of basic sampling in one wave form ρ
Most high frequency of sub-carrier ƒ0

[0161] defined as ρƒ0=12.5 MHz. Sampling frequency CLK of DA and AD converter is

CLK=ρ×α׃0=12.5×8=100 MHz

[0162] Transmission speed is 23$\mathrm{CLK}\times \frac{A}{\alpha }=100\times \frac{8}{8}=100\mathrm{Mbps}$

[0163] About frequency of sub-carrier concern in the frequency range of 6.0 MHz˜0.09 MHz 24$\sum _{q=0}^{31}{\cos }^2\frac{2\pi f_p}{8\times 12.5}\left(8q+1\right)\cong \sum _{q=0}^{31}{\sin }^2\frac{2\pi f_p}{8\times 12.5}\left(8q+1\right)$

[0164] The frequency is determined as 25$\begin{array}{cccc}{f}_0=0.0950\mathrm{MHz}& f_1=0.473\mathrm{MHz}& f_2=0.852\mathrm{MHz}& f_3=1.231\mathrm{MHz}\\ f_4=1.610\mathrm{MHz}& f_5=1.989\mathrm{MHz}& f_6=2.368\mathrm{MHz}& f_7=2.747\mathrm{MHz}\\ f_8=3.314\mathrm{MHz}& f_9=3.693\mathrm{MHz}& f_{10}=4.072\mathrm{MHz}& f_{11}=4.451\mathrm{MHz}\\ f_{12}=4.830\mathrm{MHz}& f_{13}=5.208\mathrm{MHz}& f_{14}=5.588\mathrm{MHz}& f_{15}=5.966\mathrm{MHz}\end{array}$

SIMPLE PROVE OF FIG.

[0165] [FIG. 1] Modulation and demodulation total system block diagram.

[0166] [FIG. 2] Block diagram of modulation.

[0167] [FIG. 3] Block diagram of demodulation.

[0168] [FIG. 4] Block diagram of phase and magnitude adjustment.

[0169] [FIG. 5] Block diagram of distributed time phase and magnitude adjustment.

[0170] [FIG. 6] Block diagram of demodulation for synchronization.

[0171] [FIG. 7] Block diagram of adjustment signal.

[0172] [FIG. 8] Block diagram of adjustment signal.

[0173] [FIG. 9] Block diagram of adjustment signal.

SIMPLE PROVE OF SYMBOL

[0174] DFF data flip-flop.

[0175] CLK clock.

[0176] ROM read only memory.

[0177] TFF toggle flip-flop.

Claims

1. The numbers of sub-carrier frequency are n, and by using proper positive integer α, modulation circuit is constructed, by 2n numbers of modulation ROM of which address are 2αn, by 2n numbers of multiplier of 2n number of modulation data and data of modulation ROM as product, by accumulator summing together all data from multipliers, and by DA converter converting the data to analog from accumulator. Demodulation circuit is constructed, by ad converter of which sampling frequency is same as da converter, by 2n numbers of ROM1 and 4n numbers of ROM2 of which address is 2αn, by 2n numbers of multipliers by which the data from AD converter is multiplied with the data of each ROM1, by 2n numbers of accumulator by which the products of multiplier are accumulated and reset at every 2αn data, by 4n numbers of multiplier by which the data from AD converter is multiplied with the data of each ROM2, by 4αn numbers of accumulator by which the products of the multiplier are accumulated partially by α number and reset at every 2αn data, and by the phase adjustment circuit using the accumulated data of cosine and sine wave of same sub-carrier frequency. 2n numbers of modulation Rom store the columns element data independently of modulation matrix of which elements are the value of trigonometric sine and cosine of sub-carrier frequencies in the address as sampling order, 2n number of demodulation ROM1, of which lines and columns are 2αn and 2n, store the element data of combined matrix in α number position of inverse matrices which are made from the α numbers matrices of 2n lines and 2n columns picking up the line of modulation ROM according a number. 4n numbers of demodulation ROM2 store one pair of ROM1 belonging to sine and cosine of same sub-carrier frequency and store columns data which are shifted α number respectively to the end of this pair data of ROM1. 4αn numbers of accumulated partially data by α number are adjusted about phase and are sent in accordance with shifting number to comparator and the address counter for demodulation is reset as the top of same data series near to a meets the data of the top of minimum shift number. Such system is claimed.

2. The modulation and demodulation system included in claim 1, of which sub-carrier frequency is determined so as to become minimum difference of the accumulated square value of the cosine data and the sine data picked up from modulation ROM by a interval of same sub-carrier frequency.

3. The modulation and demodulation system included in claim 1, of which synchronization circuit is different as following, of which every two series of modulation data are same and in specified trigonometric function in a sub-carrier for synchronization this is different from next series, of which demodulation ROM for synchronization is picked up from demodulation ROM1 responding synchronization sub-carrier for modulation and specified the address by continuous number being different from demodulation ROM address, of which data of demodulation ROM for synchronization is multiplied with AD converted data and accumulated for one round address number from every address as starting and send amount value at every time, and which have comparator comparing the amount value and next one find out difference for the synchronization signal.

4. The modulation and demodulation system included in claim 1, which have the same demodulation circuits described in claim 1 and a first detection circuit constructed by partial oscillator, mixer and mid-frequency filter, and which have such modulation block that output the same signal as DA converter output described in claim 1 at the output of mid-frequency filter by proper modulation method.

5. The modulation and demodulation system include in claim 1, of which element of the modulation ROM are the products of the element of trigonometric modulation ROM and proper element of same size matrix at same position of each matrix, and of which element of demodulation ROM is inverted matrix of this above modulation ROM.

6. The modulation and demodulation system included in claim 1, of which sub-carrier frequency is determined so as to become minimum difference between the accumulated value of the cosine data to the power m and the accumulated value of the sine data to the power m of which cosine and sine are picked up from modulation ROM by a interval of same sub-carrier frequency, by positive integer number of m.