Claims
- 1. A method for verifying instructions in a module of a computer program, one-module-at-a-time, the method comprising:
determining whether checking an instruction in a first module requires information in a referenced module different than the first module; and if the information is required, writing a constraint for the referenced module without requiring access to the referenced module.
- 2. The method of claim 1, further comprising:
performing any intra-module check required for the instruction; and returning to determining whether checking an instruction in the first module requires information in the referenced module until needed instructions in the first module have been subjected to said determination.
- 3. The method of claim 2, said performing any intra-module check further comprising sending an error message if the instruction fails to satisfy any intra-module check.
- 4. A method for verifying instructions of a module of a computer program during linking, the method comprising:
determining whether a first module which is loaded has passed per-verification one-module-at-a-time; if the first module has passed pre-verification, reading a pre-verification constraint on a constrained module, if any; if any pre-verification constraint is read, determining if the constrained module is loaded; and if the constrained module is loaded, enforcing the pre-verification constraint.
- 5 The method of claim 4, said enforcing the pre-verification constraint further comprising sending an error message if the constrained module fails to satisfy the pre-verification constraint.
- 6 The method of claim 4, further comprising, if the constrained module is not loaded, loading the constrained module and enforcing the per-verification constraint.
- 7 The method of claim 4, further comprising, if the constrained module passes the pre-verification constraint during said enforcing, returning to reading a pre-verification constraint on a constrained module until all per-verification constraints are read.
- 8 The method of claim 6, further comprising, if the constrained module passes the pre-verification constraint during said enforcing, returning to reading a pre-verification constraint on a constrained module until all per-verification constraints are read, whereby the first module is verified.
- 9. A computer program product for verifying instructions in a module of a computer program, one-module-at-a-time, the product comprising:
a computer readable storage medium; computer controlling commands, stored on the computer readable storage medium, for determining whether checking an instruction in a first module requires information in a referenced module different than the first module; and, writing a constraint for the referenced module without requiring access to the referenced module, if the information is required.
- 10. The computer program product of claim 9, 1further comprising computer controlling commands, stored on the computer readable storage medium, performing any intra-module check required for the instruction and for returning to determining whether checking an instruction in the first module requires information in the referenced module until needed instructions in the first module have been subjected to said determination.
- 11. The computer program product of claim 10, further comprising computer controlling commands, stored on the computer readable storage medium, for sending an error message during if the instruction fails to satisfy any intra-module check.
- 12. A computer program product for verifying instructions of a module of a computer program during linking, the computer program product comprising:
a computer readable storage medium; computer controlling commands, stored on the computer readable storage medium, for determining whether a first module which is loaded has passed per-verification one-module-at-a-time, for reading a pre-verification constraint on a constrained module, if any, if the first module has passed verification, for determining if the constrained module is loaded if any pre-verification constraint is read, and for enforcing the pre-verification constraint if the constrained module is loaded.
- 13 The computer program product of claim 12, further comprising computer controlling commands, stored on the computer readable storage medium, for sending an error message if the constrained module fails to satisfy the pre-verification constraint while enforcing the pre-verification constraint.
- 14 The computer program product of claim 12, further comprising computer controlling commands, stored on the computer readable storage medium, for loading the constrained module and enforcing the pre-verification constraint, if the constrained module is not loaded.
- 15 The computer program product of claim 12, further comprising computer controlling commands, stored on the computer readable storage medium, for returning to reading a pre-verification constraint on a constrained module, if the constrained module passes the pre-verification constraint during said enforcing, until all pre-verification constraints are read.
- 16 The computer program product of claim 14, further comprising computer controlling commands, stored on the computer readable storage medium, for returning to reading a pre-verification constraint on a constrained module, if the constrained module passes the pre-verification constraint during said enforcing, until all pre-verification constraints are read, whereby the first module is verified.
- 17. A pre-verification apparatus for verifying a module one-module-at-a-time, the apparatus comprising:
a computer readable storage medium for storing a module of a computer program and a constraint; a processor configured to determine whether checking an instruction in a first module requires information in a referenced module different than the first module, and to write a constraint for the referenced module without requiring access to the referenced module if the information is required.
- 18. The pre-verification apparatus of claim 17, wherein the processor is further configured to performing any intra-module check required for the instruction, and to return to determining whether checking an instruction in the first module requires information in the referenced module until needed instructions in the first module have been subjected to said determination.
- 19. The pre-verification apparatus of claim 18, wherein the processor is further configured to send an error message if the instruction fails to satisfy any intra-module check.
- 20. A verification apparatus for verifying a module during linking, the apparatus comprising:
a computer readable storage medium for storing a module of a computer program; a memory into which a module is loaded; a processor configured to determine whether a first module which is loaded has passed pre-verification one-module-at-a-time, to read a per-verification constraint on a constrained module, if any, if the first module has passed verification, to determine if the constrained module is loaded if any per-verification constraint is read, and to enforce the pre-verification constraint if the constrained module is loaded.
- 21 The verification apparatus of claim 20, wherein the processor is further configured to send an error message if the constrained module fails to satisfy the pre-verification constraint during said enforcing.
- 22 The verification apparatus of claim 20, wherein the processor is further configured to load the constrained module and to enforce the per-verification constraint, if the constrained module is not already loaded.
- 23 The verification apparatus of claim 20, wherein the processor is further configured to return to reading a pre-verification constraint on a constrained module if the constrained module passes the pre-verification constraint during said enforcing, until all pre-verification constraints are read.
- 24 The verification apparatus of claim 22, wherein the processor is further configured to return to reading a pre-verification constraint on a constrained module if the constrained module passes the pre-verification constraint during said enforcing, until all pre-verification constraints are read, whereby the first module is verified.
- 25. A signal transmission comprising:
a carrier wave on a communications line; and signals indicative of computer controlling commands, transmitted using the carrier wave, for determining whether checking an instruction in a first module of a computer program requires information in a referenced module different than the first module; and, writing a constraint for the referenced module without requiring access to the referenced module if the information is required.
- 26. The signal transmission of claim 25, further comprising computer controlling commands, transmitted using the carrier wave, for performing any intra-module check required for the instruction and for returning to determining whether checking an instruction in the first module requires information in the referenced module until needed instructions in the first module have been subjected to said determination.
- 27. The signal transmission of claim 26, further comprising computer controlling commands, transmitted using the carrier wave, for sending an error message during if the instruction fails to satisfy any intra-module check.
- 28. A signal transmission comprising:
a carrier wave on a communications line; and signals indicative of computer controlling commands, transmitted using the carrier wave, for determining whether a first module which is loaded has passed pre-verification one-module-at-a-time, for reading a pre-verification constraint on a constrained module, if any, if the first module has passed per-verification, for determining if the constrained module is loaded if any per-verification constraint is read, and for enforcing the pre-verification constraint if the constrained module is loaded.
- 29 The signal transmission of claim 28, further comprising computer controlling commands, transmitted using the carrier wave, for sending an error message if the constrained module fails to satisfy the pre-verification constraint while enforcing the pre-verification constraint.
- 30 The signal transmission of claim 28, further comprising computer controlling commands, transmitted using the carrier wave, for loading the constrained module and enforcing the pre-verification constraint, if the constrained module is not loaded.
- 31 The signal transmission of claim 28, further comprising computer controlling commands, transmitted using the carrier wave, for returning to reading a pre-verification constraint on a constrained module, if the constrained module passes the pre-verification constraint during said enforcing, until all per-verification constraints are read.
- 32 The signal transmission of claim 30, further comprising computer controlling commands, transmitted using the carrier wave, for returning to reading a pre-verification constraint on a constrained module, if the constrained module passes the pre-verification constraint during said enforcing, until all per-verification constraints are read, whereby the first module is verified.
- 33. A pre-verification system comprising:
a network; a computer readable storage medium connected to the network for storing a module of a computer program; a memory connected to the network into which a module is loaded; a processor connected to the network, configured to determine whether checking an instruction in a first module requires information in a referenced module different than the first module, and to write a constraint for the referenced module without requiring access to the referenced module if the information is required, whereby pre-verification is performed one-module-at-a-time; and a processor connected to the network configured to determine during linking whether a first module which is loaded has passed pre-verification one-module-at-a-time before linking, to read a pre-verification constraint on a constrained module, if any, if the first module has passed pre-verification, to determine if the constrained module is loaded if any pre-verification constraint is read, and to enforce the pre-verification constraint if the constrained module is already loaded, whereby verification is performed one-module-at-a-time before linking with reduced verification during linking.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. patent application Ser. No. 575,291 (P1000) filed Dec. 20, 1995, Yellin and Gosling, entitled BYTECODE PROGRAM INTERPRETER APPARATUS AND METHOD WITH PRE-VERIFICATION OF DATA TYPE RESTRICTIONS AND OBJECT INITIALIZATION, now U.S. Pat. No. 5,740,441; U.S. patent application Ser. No. 09/134,477 (P3135) filed Aug. 14, 1998, Bracha and Liang, entitled METHODS AND APPARATUS FOR TYPE SAFE, LAZY, USER-DEFINED CLASS LOADING; the disclosures of which are incorporated herein in their entireties by reference.
[0002] This application is also related to U.S. patent application Ser. No. [50253-228](P3564) filed ______, 1999, entitled FULLY LAZY LINKING; U.S. patent application Ser. No. [50253-230] (P3566) filed ______, 1999, entitled FULLY LAZY LINKING WITH MODULE-BY-MODULE VERIFICATION; U.S. patent application Ser. No. [50253-235] (P3810) filed ______, 1999, entitled CACING UNTRUSTED MODULES FOR MODULE-BY-MODULE VERIFICATION; U.S. patent application Ser. No. [50253-236] (P3809) filed ______, 1999, entitled DATAFLOW ALGORITHM FOR SYMBOLIC COMPUTATION OF LOWEST UPPER BOUND TYPE.
Continuations (1)
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Number |
Date |
Country |
Parent |
09320574 |
May 1999 |
US |
Child |
10650968 |
Aug 2003 |
US |