MODULO-BASED ANALOG-TO-DIGITAL CONVERSION APPARATUS AND METHOD

Abstract

A modulo-based ADC implementation is provided and involves converting an input analog signal into phases of other M periodic analog reference signals based on one or more transfer functions, wherein M≥2. The phase of each of the M reference signals comprises a folded signal corresponding to the input analog signal that is amplitude-folded to fall within a required amplitude range. This signal-to-phase conversion allows a modulo operation to be implemented over the input analog signal. Further, the M reference signals are used to obtain M discrete-time digital signals which, in turn, are used to obtain a digital representation of the input analog signal.

Description

BACKGROUND

Applying digital signal processing algorithms to an input analog signal requires an interface between the input analog signal and a digital signal processor. As an example of such an interface, an ADC apparatus, also known as an AD converter, may be used, whose tasks are to sample and quantize a continuous-time continuous-amplitude (i.e. analog) signal in order to create discrete-time discrete-valued (i.e. digital) inputs required by any digital signal processing algorithm. If input analog signals are bandlimited and sampled at the Nyquist rate or above and quantized with very high precision, then the effects of the AD converters are negligible, since digital signals reconstructed at the digital signal processor from the discrete-time digital inputs approximate the input analog signals with negligible distortion.

In some applications, very high-precision AD converters are however not cost and/or power-efficient or not even feasible using the existing technology. For example, this is the case when the ADC is applied to wideband multi-GHz analog signals. Indeed, the existing ADC technology working at very high sampling rates and high resolution is limited by a timing (or aperture) jitter, i.e. the failure to sample at precisely defined times. More specifically, electronic-based AD converters cannot achieve timing jitters smaller than one femtosecond and, hence, photonic-based AD converters are preferred to meet the strict timing jitter required by sampling frequencies in the order of tens of GHz. Furthermore, wideband AD converters with very high resolution are challenging even theoretically. Indeed, their accuracy is strictly below 8 bits, and this is not enough in some applications. For example, it cannot guarantee high-order modulations required in envisioned THz wireless communications to support very high throughputs. Therefore, new ADC strategies are being investigated.

One such ADC strategy has been recently proposed in the literature under the name of modulo-based ADC or modulo-ADC. The modulo-based ADC allows avoiding clipping errors caused by the conventional ADC but requires additional digital signal processing to reconstruct a digital estimate of the original analog signal from modulo-reduced discrete-time digital inputs resulting from the modulo-based ADC. This is not always possible to do and requires some conditions placed on the input analog signals to hold. In case an ADC is applied to a single input analog signal, the input analog signal needs to present some time correlation, or it needs to be generated by means of oversampling.

In general, the prior art solutions relating to the modulo-based ADC involve using corresponding digital reconstruction algorithms for specific ADC problems. However, the prior art solutions have not specified the actual modulo-based ADC implementation. There is therefore a need to provide an ADC apparatus configured to implement a modulo-based ADC and a corresponding method.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure.

It is an objective of the present disclosure to provide a technical solution that allows modulo-based ADC to be performed on analog signals.

One or more of the objectives above is achieved by the features of the independent claims in the appended claims. Further embodiments and examples are apparent from the dependent claims, the detailed description and the accompanying drawings.

According to a first aspect, an ADC apparatus is provided, which comprises a signal-to-phase conversion unit, an ADC unit, and a digital signal processing (DSP) unit. The signal-to-phase conversion unit is configured to convert an input analog signal into phases of M periodic reference signals based on at least one transfer function, wherein M≥2. The phase of each of the M periodic reference signals comprises a folded signal. The folded signal corresponds to the input analog signal that is amplitude-folded to fall within an amplitude range. Given this, the signal-to-phase conversion corresponds to the outcome of a modulo operation. The ADC unit is configured to obtain M discrete-time digital signals by performing an ADC operation on the M periodic reference signals within the amplitude range. The DSP unit is configured to obtain, based on the M discrete-time digital signals, a digital representation of the input analog signal. By so doing, it is possible to perform the modulo-based ADC on the input analog signal. Furthermore, such a configuration of the ADC apparatus may provide the high-resolution quantization of the input analog signal at a very high sampling rate and very high signal bandwidths. Given this, the accuracy of obtaining the digital representation of the input analog signal may be increased.

In one embodiment of the first aspect, the phases of at least two of the M periodic reference signals have a difference other than 0 or π. By using at least one pair of periodic reference signals with such a phase difference, it is possible to cope with the problem of phase sign ambiguity which occurs, for example, when the pair of periodic reference signals are represented by two sine functions such that sin(x(t))=sin(π−x(t)), where x(t) is the input analog signal.

In one embodiment of the first aspect, the input analog signal changes in a predefined dynamic range, and each of the at least one transfer functions is a bijective function in the predefined dynamic range of the input analog signal. By using the bijective function, it is possible to provide a proper relationship between the phases of the reference signals and the input analog signal, thereby increasing the accuracy of obtaining the digital representation of the input analog signal.

In one embodiment of the first aspect, the at least one transfer function comprises a first transfer function and a second transfer function, and, in the predefined dynamic range of the input analog signal, the first transfer function and the second transfer function are a same bijective function. In this embodiment, the first transfer function has a first constant phase shift and the second transfer function has a second constant shift. The first constant phase shift of the first transfer function and the second constant phase shift of the second transfer function have a difference other than 0 or π. By using such phase shifts for the same bijective function, it is possible to cope with the above-mentioned problem of phase sign ambiguity arising, for example, from sin(x(t))=sin(π−x(t)).

In one embodiment of the first aspect, each of the at least one transfer function is an affine function. By using the affine functions, it is possible to provide a proper relationship between the phases of the reference signals and the input analog signal, thereby increasing the accuracy of obtaining the digital representation of the input analog signal. Furthermore, the possibility of choosing among the affine functions and the bijective functions makes the ADC apparatus according to the first aspect more flexible in use.

In one embodiment of the first aspect, the ADC unit comprises M synchronized ADC subunits each configured to perform the ADC operation on one of the M periodic reference signals. By so doing, it is possible to perform the ADC operation on the M periodic reference signals in parallel, thereby increasing the accuracy of obtaining the digital representation of the input analog signal.

In one embodiment of the first aspect, at least one of the M ADC subunits has a different bit resolution or different quantization level (i.e., different quantization function) compared to the other synchronized ADC subunits of the M synchronized ADC subunits. This may allow one to differently quantize the M periodic reference signals, if required and depending on particular applications, thereby making the ADC apparatus according to the first aspect more flexible in use.

In one embodiment of the first aspect, the DSP unit is configured to obtain the digital representation of the input analog signal by:

• • determining a phase of at least one of the M discrete-time digital signals; inverting one of the at least one transfer function based on the determined phase, while using at least one other of the M discrete-time digital signals to solve phase sign ambiguity; and
  • obtaining the digital representation of the input analog signal based on the inverted transfer function.

By so doing, it is possible to obtain the digital representation of the input analog signal by using only two discrete-time digital signals or, in other words, only two periodic reference signals.

In one embodiment of the first aspect, the signal-to-phase conversion unit comprises an optical source and M phase-biased electro-optic modulators. The optical source is configured to generate a pulse train that serves as the M periodic reference signals. Each of the M phase-biased electro-optic modulators has an electro-optical response as one of the at least one transfer function and is configured to receive the input analog signal and modulate the pulse train with the input analog signal, thereby converting the input analog signal into the phases of the M periodic reference signals. By so doing, it is possible to implement the modulo-based ADC with photonic sampling.

In one embodiment of the first aspect, the optical source comprises a mode-locked laser. The mode-locked laser may generate an ultra-stable pulse train that may be used to optically sample the input analog signal, while addressing the problem of a timing jitter.

In one embodiment of the first aspect, each of the M phase-biased electro-optic modulators comprises a Mach-Zehnder modulator (MZM). This type of electro-optic modulator is preferred due to its low optical relative loss, high optical power processing capability, and wide optical bandwidth.

In one embodiment of the first aspect, at least two of the M MZMs have a modulation index that is more than 1. If the transfer function is represented by a sine/cosine function, the MZMs with such a modulation index may fully use the sine/cosine transfer function and not only its linear part (as would be the case for the MZMs with the modulation index less than 1).

In one embodiment of the first aspect, the at least two MZMs have a same bijective transfer function supplemented by different constant phase shifts which are obtained by applying different DC bias voltages to the at least two MZMs. By using different DC bias voltages in this embodiment, it is possible to ensure that the phase difference between the corresponding periodic reference signals is other than 0 or π.

In one embodiment of the first aspect, the DSP unit is configured to obtain the digital representation of the input analog signal by applying a machine-learning algorithm. The machine-learning algorithm may speed-up the operation of obtaining the digital representation of the input analog signal.

According to a second aspect, an ADC method is provided. The ADC method starts with the step of converting an input analog signal into phases of M periodic reference signals based on at least one transfer function, wherein M≥2. The phase of each of the M periodic reference signals comprises a folded signal. The folded signal corresponds to the input analog signal that is amplitude-folded to fall within an amplitude range. Given this, the signal-to-phase conversion corresponds to the outcome of the modulo operation. The method further proceeds to the step of obtaining M discrete-time digital signals by performing an ADC operation on the M periodic reference signals within the amplitude range. After that, the method goes on to the step of using the M discrete-time digital signals to obtain a digital representation of the input analog signal. By so doing, it is possible to perform the modulo-based ADC on the input analog signal. Furthermore, the method according to the second aspect may provide the high-resolution quantization of the input analog signal at a very high sampling rate and very high signal bandwidths. Given this, the accuracy of obtaining the digital representation of the input analog signal may be increased.

In one embodiment of the second aspect, the phase of at least two of the M periodic reference signals have a difference other than 0 or π. By using at least one pair of periodic reference signals with such a phase difference, it is possible to cope with the problem of phase sign ambiguity which occurs, for example, when the pair of periodic reference signals are represented by two sine functions such that sin(x(t))=sin(π−x(t)), where x(t) is the input analog signal.

In one embodiment of the second aspect, the input analog signal changes in a predefined dynamic range, and each of the at least one transfer functions is a bijective function in the predefined dynamic range of the input analog signal. By using the bijective function, it is possible to provide a proper relationship between the phases of the reference signals and the input analog signal, thereby increasing the accuracy of obtaining the digital representation of the input analog signal.

In one embodiment of the second aspect, the at least one transfer function comprises a first transfer function and a second transfer function, and, in the predefined dynamic range of the input analog signal, the first transfer function and the second transfer function are a same bijective function. In this embodiment, the first transfer function has a first constant phase shift and the second transfer function has a second constant phase shift. The first constant phase shift of the first transfer function and the second constant phase shift of the second transfer function have a difference other than 0 or π. By using such phase shifts for the same bijective function, it is possible to cope with the above-mentioned problem of phase sign ambiguity arising, for example, from sin(x(t))=sin(π−x(t)).

In one embodiment of the second aspect, each of the at least one transfer functions is an affine function. By using the affine functions, it is possible to provide a proper relationship between the phases of the reference signals and the input analog signal, thereby increasing the accuracy of obtaining the digital representation of the input analog signal. Furthermore, the possibility of choosing among the affine functions and the bijective functions makes the method according to the second aspect more flexible in use.

In one embodiment of the second aspect, the digital representation of the input analog signal is obtained by:

• • determining a phase of at least one of the M discrete-time digital signals; inverting one of the at least one transfer function from the determined phase, while using at least one other of the M discrete-time digital signals to solve phase sign ambiguity; and obtaining the digital representation of the input analog signal based on the inverted transfer function.

By so doing, it is possible to obtain the digital representation of the input analog signal by using only two discrete-time digital signals or, in other words, only two periodic reference signals.

In one embodiment of the second aspect, the digital representation of the input analog signal is obtained by applying a machine-learning algorithm. The machine-learning algorithm may allow one to reduce the time required to obtain the digital representation of the input analog signal.

According to a third aspect, a computer program product is provided. The computer program product comprises a computer-readable storage medium storing a computer code which, when executed by at least one processor, causes the at least one processor to perform the method according to the second aspect. By using such a computer program product, it is possible to simplify the implementation of the method according to the second aspect in any ADC apparatus, like the ADC apparatus according to the first aspect.

According to a fourth aspect, a signal processing apparatus is provided. The signal processing apparatus comprises a receiving unit and the ADC apparatus according to the first aspect. The receiving unit is configured to receive the input analog signal and provide the input analog signal to the ADC apparatus according to the first aspect for its processing in the above-described manner. By using such an ADC apparatus in the signal processing apparatus according to the fourth aspect, it is possible to perform the modulo-based ADC on the input analog signal at a very high sampling rate and very high signal bandwidths. This, in turn, makes it possible to use the signal processing apparatus according to the fourth aspect, for example, in THz wireless communications.

Other features and advantages of the present disclosure will be apparent upon reading the following detailed description and reviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is explained below with reference to the accompanying drawings, in which:

FIG. 1 shows one example of a transfer function of a modulo-A operation;

FIG. 2 shows the transfer function for the case of an ideal modulo-based ADC at a quantization resolution of b=4 bits;

FIG. 3 shows a block diagram of an ADC apparatus in accordance with a first exemplary embodiment;

FIG. 4 shows a flowchart of an ADC method in accordance with one exemplary embodiment;

FIG. 5 shows a block diagram of an ADC apparatus in accordance with a second exemplary embodiment;

FIGS. 6A and 6B show digital representations of an input analog signal which are obtained using two different bit resolutions (i.e. 4 bits and 8 bits) of a high-resolution ADC subunit included in the ADC apparatus shown in FIG. 5;

FIGS. 7A and 7B show digital representations y[] of the input analog signal which are obtained using two different bit resolutions (i.e. 4 bits and 8 bits) of two identical ADC subunits included in the ADC apparatus shown in FIG. 5;

FIG. 8 shows a block diagram of an ADC apparatus in accordance with a third exemplary embodiment;

FIG. 9 shows an electro-optic response and a desired operational regime for a conventional MZM; and

FIG. 10 shows a block diagram of a signal processing apparatus in accordance with one exemplary embodiment.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are further described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description. In contrast, these embodiments are provided to make the description of the present disclosure detailed and complete.

According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the present disclosure encompasses any embodiment thereof, which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the present disclosure. For example, the apparatuses and method disclosed herein may be implemented in practice by using any number of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the present disclosure may be implemented using one or more of the features presented in the appended claims.

The word “exemplary” is used herein in the meaning of “used as an illustration”. Unless otherwise stated, any embodiment described herein as “exemplary” should not be construed as preferable or having an advantage over other embodiments.

Although the numeric terminology, such as “first”, “second”, etc., may be used herein to describe various embodiments, it should be understood that these embodiments should not be limited by this numeric terminology. This numeric terminology is used herein only to distinguish one embodiment from another embodiment. Thus, a first embodiment discussed below could be called a second embodiment, without departing from the teachings of the invention.

As used in the embodiments disclosed herein, an ADC apparatus or, in other words, AD converter may refer to a device configured to convert an analog signal into its digital representation by means of a modulo-based ADC. The basic idea behind the modulo-based ADC is to apply a modulo operation to the analog signal before its quantization such that a resulting folded signal perfectly matches a quantizer input range. It should be noted that the analog signal may be represented by any one of an RF signal received by a receiver, an acoustic signal picked up by a microphone, a light signal entering a digital camera, etc. Generally speaking, the analog signal to be digitally processed in the embodiments disclosed herein may be any wireless or wired signal. Furthermore, the ADC apparatus may be integrated into any signal processing apparatus which may be implemented, for example, as a part of a communication apparatus (e.g., a user equipment (UE) or network node), a radar, a sensing apparatus (e.g., a measurement bridge or voltmeter), etc.

The UE may refer to a mobile device, a mobile station, a terminal, a subscriber unit, a mobile phone, a cellular phone, a smart phone, a cordless phone, a personal digital assistant (PDA), a wireless communication device, a desktop computer, a laptop computer, a tablet computer, a gaming device, a netbook, a smartbook, an ultrabook, a medical device or medical equipment, a biometric sensor, a wearable device (for example, a smart watch, smart glasses, a smart wrist band, etc.), an entertainment device (for example, an audio player, a video player, etc.), a vehicular component or sensor, a smart meter/sensor, an unmanned vehicle (e.g., an industrial robot, a quadcopter, etc.), industrial manufacturing equipment, a global positioning system (GPS) device, an Internet-of-Things (IoT) device, an Industrial IoT (IIoT) device, a machine-type communication (MTC) device, a group of Massive IoT (MIoT) or Massive MTC (mMTC) devices/sensors, or any other suitable device configured to support wireless communications. In some embodiments, the UE may refer to at least two collocated and inter-connected UEs thus defined.

The network node may relate to a fixed point of communication for the UE in a particular wireless communication network. The network node may be implemented as a Radio Access Network (RAN) node referred to as a base transceiver station (BTS) in terms of the 2G communication technology, a NodeB in terms of the 3G communication technology, an evolved NodeB (eNodeB) in terms of the 4G communication technology, and a gNB in terms of the 5G New Radio (NR) communication technology. The RAN node may serve different cells, such as a macrocell, a microcell, a picocell, a femtocell, and/or other types of cells. The macrocell may cover a relatively large geographic area (for example, at least several kilometers in radius). The microcell may cover a geographic area less than two kilometers in radius, for example. The picocell may cover a relatively small geographic area, such, for example, offices, shopping malls, train stations, stock exchanges, etc. The femtocell may cover an even smaller geographic area (for example, a home). Correspondingly, the RAN node serving the macrocell may be referred to as a macro node, the RAN node serving the microcell may be referred to as a micro node, and so on.

Turning back to the modulo-based ADC, how the modulo-based ADC may be implemented from an ideal point of view will now be described. The present disclosure provides a modulo-based ADC implementation which behaves as close as possible to the ideal modulo-based ADC, as will be explained further.

An ideal response of a modulo-based ADC apparatus with a sample frequency f_s=1/T_s, an input range [−λ/2, λ/2], and a resolution of b bits may be described as follows. Let x(t) be an input analog signal (bandlimited with a bandwidth BW≤f_s/2), then the ideal modulo-based ADC may be mathematically expressed as:

y[]=Q_b(mod_λ(x(T_s))),

where

• • The sampling process, i.e., the conversion from continuous-time to discrete-time, is assumed ideal (i.e. there are no sampling jitter errors) and is abstracted as changing the continuous-time t to the sample index =1, 2, 3, . . . Accordingly, x[]=x(T_s) denotes the discrete-time version of the input analog signal x(t), where T_s is the sampling period.

mod_λ(·) is the modulo-λ operation that folds the input analog signal whenever its amplitude is higher than λ/2 or lower than −λ/2. Mathematically, it is defined as the following transfer function:

mod_λ(x)=x−λ(1+[x/λ−1/2]),

where [·] denotes the floor function. FIG. 1 shows the above-written transfer function of the modulo-λ operation (the notation “input” in FIG. 1 denotes the input analog signal x(t)). That is, FIG. 1 shows the transfer function of the modulo operation with a predefined constant equal to A.

• • Q_b(·) is the quantization function that is an abstraction modelling the composition of quantization mapping (which outputs b bits) and digital reconstruction (which maps quantization bits to appropriate signal levels). Given quantization thresholds

${\gamma }_0=-\frac{\lambda }{2},{\gamma }_1,{\gamma }_2,\dots ,{\gamma }_{2^b-1},{\gamma }_{2^b}=\frac{\lambda }{2},$

and reconstruction levels μ₀, μ₁, μ₂, . . . , μ_2b-1, the quantization function Q_b(·) may be expressed as follows:

$Q_b\left(x\right)=\sum _{i=0}^{2^b-1}{\mu }_i𝒥\left({\gamma }_i\le x\le {\gamma }_{i+1}\right),$

where (·) denotes the indicator function.

The above-given mathematical expression of the ideal modulo-based ADC, i.e. y[], does not impose any particular order between performing the sampling and modulo operations. In fact, these operations may be even simultaneously performed. The quantization function Q_b(·) remains general and, hence, includes, for example, non-uniform quantizers.

As an example, for a uniform quantizer with the resolution of b bits, the input range [−λ/2, λ/2], and a quantization step-size μ=2^−bλ, the quantization function Q_b(·) is given by

$Q_b\left(x\right)=\{\begin{array}{cc}-\mu \left(2^b-1\right)/2& x\le -\lambda /2\\ \mu \left(\left[x/\mu \right]+1/2\right)& -\lambda /2<x<\lambda /2\\ \mu \left(2^b-1\right)/2& x\ge \lambda /2\end{array}.$

FIG. 2 shows the transfer function for the case of the ideal modulo-based ADC at the resolution of b=4 bits.

Any practical implementation of the modulo-based ADC cannot support an infinite number of folds, as implied by the above-given definition of the modulo operation, i.e. mod_λ(x). Otherwise, this would require supporting an infinite dynamic range of the input analog signal x(t), which is physically impossible. In fact, there is even no need to support the infinite number of folds, and, in practice, it is enough to guarantee the maximum number of folds [max ∥x(t)∥/λ] for the optimum λ, i.e. the minimum possible λ guaranteeing the recovery of the input analog signal from discrete-time folded samples outputted by the modulo-based ADC apparatus. Consequently, the number of folds to be supported depends on the application: typically less than 10 in general-purpose AD converters or several order of magnitudes higher in the context of a full duplex transceiver.

It should be also noted that there are no commercially available devices implementing the modulo-based ADC concept as such, and only “ad-hoc” solutions or proof-of-concept designs have been proposed in the past.

For example, one approach consists in using commercially available folding AD converters or self-reset AD converters. These AD converters follow the so-called bit-per-stage architecture. There are as many stages as a bit resolution b, each of which has a “bit” output and a “residue” output. The residue output of one stage is an input to the next stage and the last bit is detected with a single comparator. It turns out that the b bits outputted by a folding AD converter may be interpreted as follows: the m most significant bits are used to count the number of folds and the remaining b−m least significant bits give a quantization index of a residual signal after folding. Hence, by using the folding AD converter with the resolution of b bits, one may implement the modulo-based ADC with the resolution of b−m bits, which allows the analog signal being folded 2^m−1 times by discarding the m most significant bits outputted by the folding AD converter. An alternative design for the self-reset AD converters includes special circuits configured to compute the modulo operation and count the number of folds followed by a quantization module of a successive approximation AD converter. The main problem with the folding AD converters or self-reset AD converters is that they are not cost or power-efficient, since, for example, the hardware used to count the number of folds is not necessary under the paradigm of the modulo-based ADC. Even more importantly, the number of times that the analog signal may be folded is small and intrinsically limited by the design of such AD converters. This prevents them from being used, for example, in full-duplex applications.

A different approach for implementing the modulo-based ADC implies that the modulo operation relies on a circular chain of inverter circuits, where the output of each inverter in the chain is connected to the input of the next inverter in the chain. The inversion for all inverters is then controlled by the same input signal. Such a circuit is called a ring oscillator. When wired this way, the frequency of oscillation in the ring oscillator will be a function of the input signal and it will generate a frequency modulated signal. Such a circuit has been long used for generating such frequency modulated signals, for example, for frequency modulated radio diffusion, but it may be repurposed as a modulo operator. The response of ring oscillators used as the modulo operation tends to have an uneven resolution, and the AD converters based on it also appear to perform relatively worse for high bitrates.

Besides the architectural limitations of the previous approaches, they also inherit the intrinsic limitation of electronic ADC technologies when converting high-speed RF signals, namely the so-called timing jitter (also referred to as aperture ambiguity or aperture jitter) and comparator ambiguity. The timing jitter is a random variation in the position of a temporal sampling interval. The result is that the sampling interval is not constant, but varies randomly, leading to accuracy degradation. The comparator ambiguity, a major limiting factor at high signal frequencies, comes from a finite speed with which an ADC comparator responds to small variations in an input analog signal to produce a correct quantization decision relative to a comparator reference.

The exemplary embodiments disclosed herein provide a technical solution that allows mitigating or even eliminating the above-mentioned drawbacks of the prior art. In particular, the technical solution disclosed herein relies on the fact that a phase of an input analog signal is naturally measured modulo 27λ. Given this, it is possible to convert the input analog signal into phases of other M periodic analog signals (hereinafter referred to as reference signals), where M≥2. The phase of each of the M periodic reference signals comprises a folded signal corresponding to the input analog signal that is amplitude-folded to fall within a required amplitude range. Thus, this signal-to-phase conversion allows the modulo operation to be implemented over the input analog signal. Further, the M periodic reference signals are used to obtain M discrete-time digital signals which, in turn, are used to obtain a digital representation of the input analog signal. By so doing, it is possible to perform the modulo-based ADC on the input analog signal.

FIG. 3 shows a block diagram of an ADC apparatus 300 in accordance with a first exemplary embodiment. The ADC apparatus 300 comprises the following constructive elements: a signal-to-phase conversion unit 302, ADC subunits 304-1, 304-2, . . . , 304-M, and a digital signal processing (DSP) unit 306. The ADC apparatus 300 may optionally comprise a reference clock 308 configured to synchronize the operation of the ADC subunits 304-1, 304-2, . . . , 304-M. However, the ADC subunits 304-1, 304-2, . . . , 304-M may also operate asynchronously, for example, successively, if required and depending on particular applications. Furthermore, at least one of the ADC subunits 304-1, 304-2, . . . , 304-M may be configured to provide a different bit resolution b or different quantization level compared to the rest of the ADC subunits 304-1, 304-2, . . . , 304-M, if required and depending on particular applications. It should be noted that the number, arrangement and interconnection of the constructive elements constituting the ADC apparatus 300, which are shown in FIG. 3, are not intended to be any limitation of the present disclosure, but merely used to provide a general idea of how the constructive elements may be implemented within the ADC apparatus 300. For example, the subunits 304-1, 304-2, . . . , 304-M may be combined into a single ADC unit. If the subunits 304-1, 304-2, . . . , 304-M are implemented as individual devices included in the ADC apparatus 300, their number should be equal to the number of periodic reference signals to be used in the modulo-based ADC, as will be discussed further in detail.

Each of the ADC subunits 304-1, 304-2, . . . , 304-M may be implemented as integrated circuits (ICs). These ICs may be implemented based on any suitable semiconductor technology, such, for example, as Complementary Metal-Oxide-Semiconductor (CMOS), Bipolar CMOS technology, etc. As a certain example, these ICs may take the form of mixed-signal IC chips that integrate both analog and digital circuits.

The DSP unit 306 may be implemented as a CPU, general-purpose processor, single-purpose processor, microcontroller, microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), digital signal processor, complex programmable logic device, etc. In some embodiments, the DSP unit 306 may be implemented as any combination of the aforesaid, e.g., as two or more microprocessors.

As for the signal-to-phase unit 302, it may be implemented by using electro-optic modulators or ring oscillators. In a preferred embodiment, the signal-to-phase unit 302 comprises the combination of an optical source (e.g., a mode-locked laser) and Mach-Zehnder modulators (MZMs).

FIG. 4 shows a flowchart of an ADC method 400 in accordance with one exemplary embodiment. More specifically, the method 400 describes the operation of the ADC apparatus 300 in terms of the modulo-based ADC implementation. As shown in FIG. 4, the method 400 starts with a step 5402, in which the signal-to-phase conversion unit 302 converts an input analog signal x(t) into phases of M periodic reference signals y₁(t), y₂(t), . . . y_M(t) based on transfer functions ϕ₁(x(t)), . . . ϕ_M(x(t)), wherein M≥2. The phase of each of the M periodic reference signals y₁(t), y₂(t), y . . . y_M(t) comprises a folded signal (not shown) corresponding to the input analog signal x(t) that is amplitude-folded to fall within an amplitude range. The term “amplitude-folded” or, in other words, “folded by amplitude” implies the same folding as used earlier when describing the modulo-λ operation mod_λ(x). Given this, the amplitude range may be equal to [−λ/2, λ/2], and the folded signal should be defined within this amplitude range. In general, the amplitude range should be selected such that the folded signal matches a quantization range of each of the ADC subunits 304-1, 304-2, . . . , 304-M. The transfer functions ϕ₁(x(t)), . . . ϕ_M(x(t)), may be bijective or affine. In the former case, the transfer function ϕ_i(x(t)) may be bijective in a predefined dynamic range of the input analog signal x(t), where the term “dynamic range” refers to the ratio of the highest signal level to the lowest signal level. By so doing, the outcome of the step 5402 is equivalent, to some extent, to the outcome of the modulo operation mod_λ(x). Then, the method 400 proceeds to a step 5404, in which each of the M periodic reference signals y₁(t), y₂(t), y_M(t) is fed to a corresponding one of the ADC subunits 304-1, 304-2, . . . , 304-M in order to be converted into a discrete-time digital signal within the same amplitude range. As a result of the step S404, there are M discrete-time digital signals. After that, the method 400 goes on to a step S406, in which the DSP unit 306 uses the M discrete-time digital signals to obtain a digital representation y [] of the input analog signal x(t). By using the method 400, it is possible to implement the modulo-based ADC as similar as possible to the above-described ideal modulo-based ADC.

As can be seen from FIG. 3, the phase of each of the M periodic reference signals y₁(t), y₂(t), . . . y_M(t) results from the transfer functions ϕ₁(x(t)), . . . (x(t)), which comprise the same bijective function ϕ(x(t)) supplemented by different constant phase shifts ψ₁, ψ₂, . . . ψ_M. To avoid the problem of phase sign ambiguity occurring, for example, when the M periodic reference signals y₁(t), y₂(t), . . . y_M(t) are represented by sine functions with some of them being such that sin(x)=sin(π−x), at least two of the constant phase shifts ψ₁, ψ₂, . . . , ψ_M may have a difference other than 0 or π.

However, the phase structures shown in FIG. 3 should not be construed as any limitation of the present disclosure. In some other embodiments, the phase of each of the M periodic reference signals y₁(t), y₂(t), . . . y_M(t) may comprise a different function. In this case, there may be no need to use constant phase shifts. At the same time, the problem of phase sign ambiguity may be again addressed if the phases (but not the phase shifts) of at least two of the M periodic reference signals y₁(t), y₂(t), . . . y_M(t) have a difference other than 0 or

In one embodiment, the DSP unit 306 may perform the step S406 of the method 400 as follows. At first, the DSP unit 306 determines a phase of at least one of the M discrete-time digital signals obtained by the ADC subunits 304-1, 304-2, . . . , 304-M in the step S404 of the method 400. Then, the DSP unit 306 inverts one of the transfer functions ϕ₁(x(t)), . . . ϕ_M(x(t)) based on the determined phase, while using at least one other of the M discrete-time digital signals to solve the problem of phase sign ambiguity. After that, the DSP unit 306 obtains the digital representation y[] of the input analog signal x(t) based on the inverted transfer function. By so doing, it is possible to use only two periodic reference signals when performing the modulo-based ADC on the input analog signal x(t).

In another embodiment, the DSP unit 306 may use, in the step 406 of the method 400, a suitable machine learning algorithm to properly process the M discrete-time digital signals outputted by the ADC subunits 304-1, 304-2, . . . , 304-M. This may improve the accuracy of the step S406 of the method 400.

The following is one non-restrictive example of how to implement the modulo operation by using the step S402 of the method 400. First, assume that the input analog signal x(t) is converted in the step S402 of the method 400 into the phase of a periodic reference signal y(t), for example, as follows:

y(t)=A sin(ϕ)(x(t))+ψ),

where A is the amplitude, ψ is the initial constant phase shift, and ϕ(·) denotes the phase transfer function, which is assumed to be any bijective function such that its inverse function ϕ⁻¹(·) exists and satisfies

ϕ(x(t)+k·λ)=ϕ(x(t))+k·2π, k=±1, ±2, . . . .

This operation effectively folds the analog input signal x(t), since it holds

y(t)=A sin(ϕ(x(t))+ψ)=A sin(ϕ(mod_λ(x(t)))+ψ).

However, the function relating y(t) with ϕ(x(t)) is not linear and not even invertible in one 2π period, i.e. when ϕ(x(t)) ∈ [−π, π), due to the phase ambiguity arising from sin(x)=sin(π−x). In order to have enough information to recover mod_λ(x(t)) from y(t), the analog input signal x(t) is converted into the phases of at least two periodic reference signals. Consider the general case of the signal-to-phase converter 302 with the following M outputs:

y _i(t)=A_i sin(ϕ(x(t))+ψ_i), i=1,2, . . . , M.

Then, the only requirement for uniquely obtaining mod_λ(x(t)) from y(t) is that there exists at least one pair of periodic reference signals y_i(t) and y_j(t) whose corresponding phase shifts ψ_i and ψ_j are neither equal nor separated by π modulo 2π:

∥ψ_i−mod_2π(ψ)∥≠0 and ∥ψ_i−mod_2π(ψ)∥≠π.

In this case, the following is computed:

ϕ_A,i=mod_2π(arcsin(y_i(t)/A_i)−ψ_i), i=1,2, . . . , M

ϕ_B,j=mod_2π(π−arcsin(y_j(t)/A_j)−ψ_j), j=1,2, . . . , M

A further step comprises uniquely recovering ϕ(x(t)) ∈ ]−π, π) as

ϕ(x(t))=ϕ_A,i if ϕ_A,1=ϕ_A,2= . . . =ϕ_A,M,   (i)

ϕ(x(t))=ϕ_B,i if ϕ_B,1=ϕ_A,2= . . . =ϕ_B,M, or ϕ(x(t))=ϕ_A,i, if for any j such that   (ii)

ϕ_A,i≠ϕ_A,j, it holds that ϕ_A,i=ϕ_B,j.

Finally, it is possible to invert the phase transfer function and obtain the modulo operation as follows:

mod_λ(x(t))=ϕ⁻¹(ϕ(x(t)))

Given the above-given example, the whole modulo-based ADC implemented by using the method 400 may be described as follows:

• • (1) The analog input signal x(t) is converted, in the step S402 of the method 400, into the phase of M periodic reference signals {y_i(t)} such that there exists at least one pair of periodic reference signals y_i(t) and y_j(t) whose corresponding phase shifts ψ_i and ψ_j have a difference other than 0 or π.
  • (2) The M periodic reference signals outputted by the signal-to-phase conversion unit 302 are converted, in the step S404 of the method 400, into the M discrete-time digital signals by using the ADC units 304-1, 304-2, . . . , 304-M with possibly different bit resolutions and synchronized under the same reference clock 308:

ŷ_i[]=Q_bi(y_i(·T_s)), i=1,2, . . . ,M.

• • (3) The DSP unit 306 jointly processes, in the step S406 of the method 400, the M discrete-time digital signals {ŷ_i[]} to uniquely determine ϕ(x(t)) ∈ [−π, π) and linearize the transfer functions of the signal-to-phase conversion unit 302 to obtain the digital representation y[] which approximates the output of the above-described ideal modulo-ADC.

According to the present disclosure, ϕ(x(t)) ∈ [−π, π) it) is recovered in the digital domain, after the M periodic reference signals outputted by the signal-to-phase conversion unit 302 have been converted to the M discrete-time digital signals using the ADC units 304-1, 304-2, . . . , 304-M.

FIG. 5 shows a block diagram of an ADC apparatus 500 in accordance with a second exemplary embodiment. The ADC apparatus 500 comprises the following constructive elements: a signal-to-phase conversion unit 502, two ADC subunits 504-1, 504-2, and a DSP unit 506. Similar to the ADC apparatus 300, the ADC apparatus 500 may optionally comprise a reference clock 508 configured to synchronize the operation of the ADC subunits 504-1, 504-2. The constructive elements of the ADC apparatus 500 are intended to perform functions similar to those performed by the constructive elements of the ADC apparatus 300 in accordance with the method 400. The ADC apparatus 500 differs from the ADC apparatus 300 in that the modulo-based ADC is implemented therein by using the signal-to-phase conversion unit 502 with the following affine transfer functions:

${\varphi }_1\left(x\left(t\right)\right)=\varphi \left(x\left(t\right)\right)=\frac{2\pi }{\lambda }x\left(t\right)$ ${\varphi }_2\left(x\left(t\right)\right)=\varphi \left(x\left(t\right)\right)=\frac{\pi }{2}=\frac{2\pi }{\lambda }x\left(t\right)+\frac{\pi }{2}.$

and with only two outputs providing a phase difference of 7r/2, namely:

$y_1\left(t\right)=A\sin \left(\varphi \left(x\left(t\right)\right)\right)=A\sin \left(\frac{2\pi }{\lambda }x\left(t\right)\right),$ $y_2\left(t\right)=A\sin \left(\varphi \left(x\left(t\right)\right)+\frac{\pi }{2}\right)=A\cos \left(\frac{2\pi }{\lambda }x\left(t\right)\right).$

Then, upon performing, by the ADC subunits 504-1, 504-2, the ADC with quantization functions Q_b1(·) and Q_b2(·) having bit resolutions b₁ and b₂, respectively, the following discrete-time digital signals may be obtained:

${\hat{y}}_1\left[\ell \right]=Q_{b_1}\left(A\sin \left(\frac{2\pi }{\lambda }x\left(\ell T_s\right)\right)\right),$ ${\hat{y}}_2\left[\ell \right]=Q_{b_2}\left(A\cos \left(\frac{2\pi }{\lambda }x\left(\ell T_s\right)\right)\right).$

At this point, there are different options to solve the problem of phase sign ambiguity and invert the transfer function of the phase-to-signal conversion unit 502, which basically depend on the quantization function applied by both the ADC subunits 504-1, 504-2.

For example, let us assume that the ADC subunit 504-1 is a high-resolution ADC subunit, while the ADC subunit 504-2 is a 1-bit ADC subunit. In case of converting y₁(t) using the high-resolution ADC subunit 504-1, one may assume that

${\hat{y}}_1\left[\ell \right]=A\sin \left(\frac{2\pi }{\lambda }x\left(\ell T_s\right)\right).$

Then, converting y₂(t) using the 1-bit ADC subunit 504-2 is as follows:

${\hat{y}}_2\left[\ell \right]=\mathrm{sign}\left(A\cos \left(\frac{2\pi }{\lambda }x\left(\ell T_s\right)\right)\right).$

Given this, the modulo-based ADC output, i.e. the output of the DSP unit 506, may be simply written as follows:

$y\left[\ell \right]=\{\begin{array}{ccc}\frac{\lambda }{\pi }\arcsin \left(\frac{{\hat{y}}_1\left[\ell \right]}{A}\right),& {\hat{y}}_2\left[\ell \right]>0& \\ & & \approx Q_{b_1}\left({\mathrm{mod}}_{\lambda }\left(x\left(\ell T_s\right)\right)\right),\\ -\frac{\lambda }{\pi }\arcsin \left(\frac{{\hat{y}}_1\left[\ell \right]}{A}\right),& {\hat{y}}_2\left[\ell \right]\le 0& \end{array}$

One problem associated with the above-given exemplary implementation is that equivalent quantization errors become higher as the phase shift ϕ(x(t)) approaches π/2, since sin(ϕ(x(T_s))) is far from linear. This problem may be alleviated by carefully designing the quantization thresholds and reconstruction levels associated with the high-resolution ADC subunit 504-1.

More specifically, FIGS. 6A and 6B show digital representations y[] of the input analog signal x(t) which are obtained using two different bit resolutions (i.e. 4 bits and 8 bits) of the high-resolution ADC subunit 504-1. As can be seen, the quantization errors present in the digital representation y[(] corresponding to the 8-bit ADC subunit 504-1 are significantly lower than those present in the digital representation y [] corresponding to the 4-bit ADC subunit 504-1. Still, when the phase shift ϕ(x(t)) approaches π/2, i.e. when the input signal x((T_s) approaches λ/2+k, for k=±1, ±2, . . . , the quantization errors are relatively high.

A different option, which also alleviates the above-mentioned problem of the quantization errors (becoming higher as the phase shift ϕ(x(t)) approaches π/2) comes from using two identical ADC subunits 504-1, 504-2 with the same quantization function Q_b(·) for converting both the outputs of the signal-to-phase conversion unit 502, i.e. the periodic reference signals y₁(t) and y₂(t). In this case, the digital representation may be obtained as follows:

$y\left[\ell \right]=\frac{\lambda }{\pi }\mathrm{atan}\left(\frac{{\hat{y}}_1\left[\ell \right]}{{\hat{y}}_2\left[\ell \right]}\right)\approx Q_b\left({\mathrm{mod}}_{\lambda }\left(x\left(\ell T_s\right)\right)\right).$

FIGS. 7A and 7B show digital representations y[] of the input analog signal x(t) which are obtained using two different bit resolutions (i.e. 4 bits and 8 bits) of the two identical ADC subunits 504-1, 504-2. It can be seen that the quantization errors present in the digital representation y[] corresponding to the 4-bit ADC subunits 504-1, 504-2 are significantly higher than those present in the digital representation y[] corresponding to the 8-bit ADC subunits 504-1, 504-2. Specifically, the quantization errors present in the digital representation y[-e] corresponding to the 8-bit ADC subunits 504-1, 504-2 can be hardly seen, so that the problem of the quantization errors becoming higher when ϕ(x(t)) approaches π/2, which is shown in FIGS. 6A and 6B, has been alleviated.

Thus, the DSP unit 506 (as well as the DSP unit 306) may select different DSP algorithms depending on the transfer function used in the signal-to-phase conversion unit and the quantization functions used in the ADC subunits to convert the periodic reference signals to the digital signals.

FIG. 8 shows a block diagram of an ADC apparatus 800 in accordance with a third exemplary embodiment. The ADC apparatus 800 comprises the following constructive elements: a signal-to-phase conversion unit 802, a single ADC unit 804, and a DSP unit 806. The ADC unit 804 is shown to encompass two groups of ADC subunits. Similar to the ADC apparatuses 300 and 500, the ADC apparatus 800 may optionally comprise a reference clock 808 configured to synchronize the operation of the two groups of ADC subunits. The constructive elements of the ADC apparatus 800 are intended to perform functions similar to those performed by the constructive elements of the ADC apparatuses 300 and 500 in accordance with the method 400.

More specifically, the signal-to-phase conversion unit 802 is configured as the combination of an optical source 810, two identical MZMs (A and B) 812, 814, and a bias control unit 816. The optical source 810 may be implemented as a mode-locked laser configured to generate an ultra-stable pulse train serving as the M periodic reference signals. The ultra-stable pulse train avoids the problem of the timing jitter. The MZMs 812, 814 driven by the optical source 810 are configured to receive the input analog signal x(t) and modulate the pulse train with the input analog signal x(t) such that the input analog signal x(t) is related to the phases of the M periodic reference signals via the transfer function, as discussed earlier. The MZMs 812, 814 may be further configured to receive corresponding DC bias voltages V_DC,A and V_DC,B from the bias control unit 816. The DC bias voltages V_DC,A and V_DC,B are controlled such that the difference between the associated phases ϕ_DC(V_DC,A) and ϕ_DC(V_DC,B) is equal to a desired value, such as π/2. It should be noted that the present disclosure is not limited to the application of the MZMs, and any other suitable electro-optic modulators may be used in the signal-to-phase conversion unit 802 for the same purpose. At the same time, it is preferable to use the MZMs due to their low optical relative loss, high optical power processing capability, and wide optical bandwidth. It is also worth noting that the number, arrangement and interconnection of the constructive elements constituting the ADC apparatus 800, which are shown in FIG. 8, are not intended to be any limitation of the present disclosure, but merely used to provide a general idea of how the constructive elements may be implemented within the ADC apparatus 800. For example, the number of the MZMs may be more than two, if required and depending on particular applications.

As mentioned above, the ADC unit 804 comprises the two groups of ADC subunits schematically denoted in FIG. 8 as “Electronic ADC A” and “Electronic ADC B”, respectively, for the sake of convenience and in order not to overload the figure with reference numerals. The two groups of ADC subunits are also provided, respectively, with time or wavelength demultiplexers 818, 820 and two groups of photo-detectors. The pulses of the modulated pulse train are detected with the photo-detectors to generate current pulses which are then amplified and converted into digital samples (or, in other words, discrete-time digital signals) using the two groups of ADC subunits. As for the demultiplexers 818 and 820, they are used to alleviate bandwidth requirements of the photo-detectors and electronic ADC subunits. In particular, when multiple wavelengths are used, each pulse of the pulse train generated by the optical source 810 is separated into N sub-pulses, each at a different center wavelength, using a filter bank (not shown). These sub-pulses are then delayed by different amounts and re-combined into a single pulse train to form the optical source output, which now has its repetition rate increased by a factor of N. After the MZMs 812 and 814, different wavelengths are taken apart by the filter bank, and each wavelength is processed independently with its dedicated photodetector and electronic ADC subunit. The resulting digital samples are finally combined at the DSP unit 806.

In one preferred embodiment, each of the MZMs 812, 814 has a modulation index m_RF»1. This is in contradiction with the conventional application of MZMs for ADC, which requires the modulation index m_RF«1. To explain such a selection of the modulation index for the MZMs 812, 814, the electro-optical response of a conventional MZM with a single output working in push-pull mode is described mathematically. Let P₀ be the light power at the MZM input, x(t) be the input RF analog signal, and V_DC be the DC bias voltage, then the photocurrent at the MZM output may be accurately modeled as follows:

$I\left(x\left(t\right)\right)=\frac{P_0}{2}\alpha \left(1-\beta \cos \left({\varphi }_{\mathrm{RF}}\left(x\left(t\right)\right)+{\varphi }_{\mathrm{DC}}\left(V_{\mathrm{DC}}\right)+\varphi \right)\right),$

where α is the optical loss in the MZM, β is the contrast ratio, ϕ is the intrinsic phase caused by the length difference in the MZM arms, and ϕ_RF(x(t)), ϕ_RF(V_DC) are the phase shifts caused by the RF analog signal x(t) and the V_DC bias voltage, respectively, which are given by

${\varphi }_{\mathrm{RF}}\left(x\left(t\right)\right)=\frac{\pi }{V_{\mathrm{RF},\pi }}x\left(t\right),$ ${\varphi }_{\mathrm{DC}}\left(V_{\mathrm{DC}}\right)=\frac{\pi }{V_{\mathrm{DC},\pi }}{V}_{\mathrm{DC}},$

where V_RF,π is the half-wave voltage at RF and V_DC,π is the half-wave voltage at DC.

Since it is desirable to obtain a highly linear response to the RF analog signal x(t) in case of ADC using conventional MZMs, the MZM parameters may be configured such that the electro-optical response of each of the conventional MZMs behaves as

$I\left(x\left(t\right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \sin \left({\varphi }_{\mathrm{RF}}\left(x\left(t\right)\right)\right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \sin \left(\frac{\pi }{V_{\mathrm{RF},\pi }}x\left(t\right)\right)\right).$

Thus, if the modulation index

$m_{\mathrm{RF}}=\frac{\pi }{V_{\mathrm{RF},\pi }}\max ❘x\left(t\right)❘\ll 1,$

the linear region of a sine function is used, as shown in FIG. 9.

As opposed to the conventional MZM, the MZMs 812, 814 are configured such that they may operate in a regime where

∥X(t)∥»>V_RF,π,

because, in the case of the modulo-based ADC, the RF analog signal x(t) should expand as many 2π periods of the MZM transfer function as desired, so that the signal x(t) is effectively folded in the step S402 of the method 400. In fact, in this case, the MZM modulation index,

$m_{\mathrm{RF}}=\frac{\pi }{V_{\mathrm{RF},\pi }}\max ❘x\left(t\right)❘,$

directly determines the maximum number of folds supported by the modulo-based ADC implementation in accordance with the method 400. In consequence, as opposed to the conventional MZM, m_RF»1, which allows one to fully use the sine/cosine transfer function of the MZM and not only its linear part.

To solve the problem of phase sign ambiguity arising, for example, from sin(x)=sin(π−x), the MZMs 812, 814 should operate in parallel, for example, with the phase difference of π/2, namely:

$I_A\left(x\left(t\right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \sin \left({\varphi }_{\mathrm{RF}}\left(x\left(t\right)\right)+\varphi \right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \sin \left(\frac{\pi }{V_{\mathrm{RF},\pi }}x\left(t\right)+\varphi \right)\right),$ $I_B\left(x\left(t\right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \cos \left({\varphi }_{\mathrm{RF}}\left(x\left(t\right)\right)+\varphi \right)\right)=\frac{P_0}{2}\alpha \left(1+\beta \cos \left(\frac{\pi }{V_{\mathrm{RF},\pi }}x\left(t\right)+\varphi \right)\right).$

Therefore, the ADC apparatus 800 comprises the two identical MZMs (A and B) 812, 814 with V_RF,π=λ driven by the same optical source 810 and with the RF analog signal x(t) and the corresponding bias voltages V_DC,A and V_DC,B controlled such that the difference between the associated phases ϕ_DC(V_DC,A) and ϕ_DC(V_DC,B) is π/2.

The later steps S404 and S406 of the method 400 may be performed in the ADC apparatus 800 as follows. The digital representation y [] may be obtained from the outputs of the two groups of ADC subunits:

${\hat{y}}_A\left[\ell \right]=Q_{b_A}\left(I_A\left(x\left(\ell T_s\right)\right)\right),$ ${\hat{y}}_B\left[\ell \right]=Q_{b_B}\left(I_B\left(x\left(\ell T_s\right)\right)\right),$ $\mathrm{as}$ $y\left[\ell \right]=\{\begin{array}{ccc}\frac{\lambda }{\pi }\arcsin \left(\left(\frac{2}{P_0\alpha }\right)\left(\frac{{\hat{y}}_A\left[\ell \right]-1}{\beta }\right)\right),& {\hat{y}}_B\left[\ell \right]>\frac{P_0}{2}\alpha & \\ & & \approx Q_b\left({\mathrm{mod}}_2\left(x\left(\ell T_s\right)\right)\right),\\ -\frac{\lambda }{\pi }\arcsin \left(\left(\frac{2}{P_0\alpha }\right)\left(\frac{{\hat{y}}_A\left[\ell \right]-1}{\beta }\right)\right),& {\hat{y}}_B\left[\ell \right]-\le \frac{P_0}{2}\alpha & \end{array}$

when the ADC subunits of the group called “Electronic ADC A” have a quantization function Q_b(·) with a resolution of b_A=b bits and the ADC subunits of the group called “Electronic ADC B” are 1-bit ADC subunits, or as

$y\left[\ell \right]=\frac{\lambda }{\pi }\mathrm{atan}\left(\frac{{\hat{y}}_A\left[\ell \right]-1}{{\hat{y}}_B\left[\ell \right]-1}\right)\approx Q_b\left({\mathrm{mod}}_{\lambda }\left(x\left(\ell T_s\right)\right)\right),$

when both the groups “Electronic ADC A” and “Electronic ADC B” have a quantization function Q_b(·) with a resolution of b=b_A=b_B bits.

FIG. 10 shows a block diagram of a signal processing apparatus 1000 in accordance with one exemplary embodiment. The signal processing apparatus 1000 comprises a receiving unit 1002 and an ADC apparatus 1004. The receiving unit 1002 is configured to receive an input analog signal, for example, any of the above-discussed signals x(t), and provide the input analog signal to the ADC apparatus 1004 in order to obtain its digital representation, for example, any of the above-discussed digital representations y[]. Given this, the ADC apparatus 1004 may be implemented as any one of the ADC apparatuses 300, 500, and 800, depending on particular applications. It should also be noted that the signal processing apparatus 1000 may be of a different type, depending on the analog input signal to be processed. For example, if the input analog signal is a wireless communication signal, the signal processing apparatus 1000 may be part of a communication apparatus, such as a UE or network node, in which the receiving unit 1002 may be implemented as a wireless receiver. In one other example, if the input analog signal is an AC voltage or current signal, the signal processing apparatus 1000 may be implemented as any measurement or sensing apparatus, such as a measurement bridge or network analyzer, in which the receiving unit 1002 may be implemented as a voltage or current sensor. In one other example, if the input analog signal is a sound signal, the signal processing apparatus 1000 may be implemented as a sound-pickup equipment, such as a microphone, in which the receiving unit 1002 may be implemented as a microphone capsule. In one other example, if the input analog signal is a radio wave, the signal processing apparatus 1000 may be implemented as a detector, such as a radar, in which the receiving unit 1002 may be implemented as a receiving antenna. Thus, the signal processing apparatus 1000 may be implemented as any apparatus which requires the modulo-based ADC for its operation.

It should be noted that each step or operation of the method 400, or any combinations of the steps or operations, can be implemented by various means, such as hardware, firmware, and/or software. As an example, one or more of the steps or operations described above can be embodied by processor executable instructions, data structures, program modules, and other suitable data representations. Furthermore, the executable instructions which embody the steps or operations described above can be stored on a corresponding data carrier and executed by at least one processor. This data carrier can be implemented as any computer-readable storage medium configured to be readable by said at least one processor to execute the processor executable instructions. Such computer-readable storage media can include both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, the computer-readable media comprise media implemented in any method or technology suitable for storing information. In more detail, the practical examples of the computer-readable media include, but are not limited to information-delivery media, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile discs (DVD), holographic media or other optical disc storage, magnetic tape, magnetic cassettes, magnetic disk storage, and other magnetic storage devices.

Although the exemplary embodiments of the present disclosure are described herein, it should be noted that any various changes and modifications could be made in the embodiments of the present disclosure, without departing from the scope of legal protection which is defined by the appended claims. In the appended claims, the word “comprising” does not exclude other elements or operations, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be advantageously used.

Claims

1. An analog-to-digital conversion (ADC) apparatus comprising: a signal-to-phase conversion unit configured to convert an input analog signal into phases of M periodic reference signals based on at least one transfer functions, wherein M≥2, and wherein the phase of each of the M periodic reference signals comprises the input analog signal amplitude-folded into a folded signal that falls within an amplitude range;an ADC unit configured to obtain M discrete-time digital signals by performing an ADC operation on the M periodic reference signals within the amplitude range; anda digital signal processing (DSP) unit configured to obtain, based on the M discrete-time digital signals, a digital representation of the input analog signal.

2. The ADC apparatus of claim 1, wherein the phases of at least two of the M periodic reference signals have a difference other than 0 or π.

3. The ADC apparatus of claim 1, wherein the input analog signal changes in a predefined dynamic range, and wherein each of the at least one transfer functions is a bijective function in the predefined dynamic range of the input analog signal.

4. The ADC apparatus of claim 3, wherein the at least one transfer functions comprises a first transfer function and a second transfer function, wherein, in the predefined dynamic range of the input analog signal, the first transfer function and the second transfer function are a same bijective function, wherein the first transfer function has a first constant phase shift and the second transfer function has a second constant phase shift, and wherein the first constant phase shift of the first transfer function and the second constant phase shift of the second transfer function have a difference other than 0 or π.

5. The ADC apparatus of claim 1, wherein each of the at least one transfer functions is an affine function.

6. The ADC apparatus of claim 1, wherein the ADC unit comprises M synchronized ADC subunits each configured to perform the ADC operation on one of the M periodic reference signals.

7. The ADC apparatus of claim 6, wherein at least one of the M synchronized ADC subunits has a different bit resolution or a different quantization level compared to the other synchronized ADC subunits of the M synchronized ADC subunits.

8. The ADC apparatus of claim 1, wherein the DSP unit is configured to obtain the digital representation of the input analog signal by: determining a phase of at least one of the M discrete-time digital signals;inverting one of the at least one transfer functions based on the determined phase, while using at least one other of the M discrete-time digital signals to solve phase sign ambiguity; andobtaining the digital representation of the input analog signal based on the inverted transfer function.

9. The ADC apparatus of claim 1, wherein the signal-to-phase conversion unit comprises: an optical source configured to generate a pulse train configured to serve as the M periodic reference signals; andM phase-biased electro-optic modulators each having an electro-optical response as one of the at least one transfer functions and configured to receive the input analog signal and modulate the pulse train with the input analog signal, thereby converting the input analog signal into the phases of the M periodic reference signals.

10. The ADC apparatus of claim 9, wherein the optical source comprises a mode-locked laser.

11. The ADC apparatus of claim 9, wherein each of the M phase-biased electro-optic modulators comprises a Mach-Zehnder modulator.

12. The ADC apparatus of claim 11, wherein at least two of the M Mach-Zehnder modulators have a modulation index that is more than 1.

13. The ADC apparatus of claim 12, wherein the at least two Mach-Zehnder modulators have a same bijective transfer function supplemented by different constant phase shifts which are obtained by applying different DC bias voltages to the at least two Mach-Zehnder modulators.

14. The ADC apparatus of claim 1, wherein the DSP unit is configured to obtain the digital representation of the input analog signal by applying a machine-learning algorithm.

15. An analog-to-digital conversion (ADC) method comprising: converting an input analog signal into phases of M periodic reference signals based on at least one transfer function, wherein M>2, and wherein the phase of each of the M periodic reference signals comprises the input analog signal amplitude-folded into a folded signal that falls within an amplitude range;obtaining M discrete-time digital signals by performing an ADC operation on the M periodic reference signals within the amplitude range; andbased on the M discrete-time digital signals, obtaining a digital representation of the input analog signal.

16. The method of claim 15, wherein the phases of at least two of the M periodic reference signals have a difference other than 0 or π.

17. The method of claim 15, wherein the input analog signal changes in a predefined dynamic range, and wherein each of the at least one transfer functions is a bijective function in the predefined dynamic range of the input analog signal.

18. The method of claim 17, wherein the at least one transfer functions comprise a first transfer function and a second transfer function, and wherein, in the predefined dynamic range of the input analog signal, the first transfer function and the second transfer function are a same bijective function, wherein the first transfer function has a first constant phase shift and the second transfer function has a second constant phase shift, and wherein the first constant phase shift of the first transfer function and the second constant phase shift of the second transfer function have a difference other than 0 or π.

19. The method of claim 15, wherein each of the at least one transfer functions is an affine function.

20. A computer program product comprising: a computer-readable storage medium storing a computer code which, when executed by at least one processor, causes the at least one processor to perform: converting an input analog signal into phases of M periodic reference signals based on at least one transfer function, wherein M24 2, and wherein the phase of each of the M periodic reference signals comprises the input analog signal amplitude-folded into a folded signal that falls within an amplitude range;obtaining M discrete-time digital signals by performing an ADC operation on the M periodic reference signals within the amplitude range; andbased on the M discrete-time digital signals, obtaining a digital representation of the input analog signal.