This non-provisional application claims priority under 35 U.S.C. ยง119(a) on Patent Application No(s). 201010589582.3 filed in China, P.R.C. on Nov. 30, 2010, the entire contents of which are hereby incorporated by reference.
1. Field of Invention
The present invention relates to a monitoring system, and more particularly to a monitoring system of the power sequence signals of peripheral devices of a motherboard in operation process.
2. Related Art
In the prior art, the operation of a motherboard is detected by a baseboard management controller.
A Complex Programmable Logic Device (CPLD) is disposed in the motherboard 100 in the prior art. However, the motherboard 100 in the prior art is solely used to control the electrification of the power supply unit for the peripheral devices (for example, a fan 120, a central processing unit (CPU) 130, or a platform controller hub (PCH) 140). In other words, the CPLD 110 is only responsible for the power switch of the peripheral devices, and does not monitor the powers of the peripheral devices. Therefore, in case of abnormal operation of the peripheral devices caused by the unstable power supplied by the power supply unit, the CPLD 110 cannot know which peripheral device has the power supply problem. Accordingly, as far as a development manufacturer is concerned, a correct solution cannot be provided if the error source cannot be effectively detected.
In view of the problem above, the present invention is a monitoring system of the power sequence signals, so as to monitor power sequence signals transmitted through peripheral devices of a motherboard in operation.
The monitoring system of the power sequence signals disclosed in the present invention comprises a power supply unit and a CPLD. The power supply unit is used to provide operation powers to the motherboard and the peripheral devices; and the CPLD is electrically connected to the power supply unit and the peripheral devices and further comprises at least one data register; in which the CPLD controls operation powers of the peripheral devices through a General Purpose Input/Output (GPIO) pin, and records the power sequence signals of the peripheral devices by the data register.
The present invention is further a monitoring method of a power sequence signals, so as to monitor power sequence signals transmitted through peripheral devices of a motherboard in operation.
The monitoring method of the power sequence signals disclosed in the present invention comprises: activating the motherboard, and driving the CPLD to select any one of the peripheral devices in sequence for being electrified; controlling, by the CPLD, operation powers of the peripheral devices through the GPIO pin, and recording the power sequence signals of the peripheral devices under different operation powers in a data register; and outputting, by the CPLD, the power sequence signals of the peripheral devices.
The present invention provides a monitoring system and method of the power sequence signals. According to the present invention, the CPLD controls the operation powers of the peripheral devices provided by the power supply unit and records the power sequence signals of the peripheral devices respectively through the GPIO pin and the data register. The CPLD outputs the power sequence signals through the communication interface, so as to enable a user to conveniently observe operation statuses of the peripheral devices.
The present invention will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the present invention, and wherein:
The CPLD 220 is electrically connected to the power supply unit 210 and the peripheral devices 240. The CPLD 220 is connected to the power supply unit 210 through a Power management Bus (PMBus). The CPLD 220 further comprises at least one data register 221. The CPLD 220 controls operation powers of the peripheral devices 240 through a GPIO pin, and records the power sequence signals of the peripheral devices 240 by the data register 221. The power sequence signals may be a logic level value, a duration, a Power-Good signal and the combination thereof.
The baseboard management controller 230 is electrically connected to the power supply unit 210 trough the PMBus. The baseboard management controller 230 further comprises a communication interface. The CPLD 220 outputs the power sequence signals of the peripheral devices 240 through the communication interface. The communication interface may be, but not limited to, a network interface (for example RJ-45). The CPLD 220 may output the power sequence signals through the PCI-E or the IPMB.
Operation relations of the devices in the present invention are clearly illustrated with reference to
In Step S310, a motherboard is activated, and a CPLD is driven to electrify multiple peripheral devices in sequence.
In Step S320, the CPLD controls operation powers of the peripheral devices through GPIO pins, and records power sequence signals of the peripheral devices under different operation powers in a data register.
In Step S330, the CPLD outputs the power sequence signals of the peripheral devices.
At first, in activation of the motherboard 200, a program for monitoring the peripheral devices 240 of the motherboard 200 is executed in the CPLD 220. The CPLD 220 sequentially performs the electrification and adjustment of supply power on the peripheral devices 240 according to a monitoring sequence of the peripheral devices 240 recorded by the monitoring program.
As each of the peripheral devices 240 may work at different voltages, each voltage respectively has a corresponding Power-Good signal. The CPLD 220 may control related circuits of the peripheral devices 240 through the GPIO pin according to a timer, so as to electrify the peripheral devices 240 in sequence. The CPLD 220 acquires status information of the peripheral devices 240 from the Power-Good signal at the same time.
Therefore, when the CPLD 220 adjusts the supply powers of the peripheral devices 240, the data register 221 records the power sequence signals of the peripheral devices 240, such as, logic level value, duration, and Power-Good signal.
The present invention provides a monitoring system and method of the power sequence signals. According to the present invention, the CPLD 220 controls the operation powers of the peripheral devices 240 provided by the power supply unit and records the power sequence signals of the peripheral devices respectively through the GPIO pin and the data register 221. Then, the CPLD 220 outputs the power sequence signals through the communication interface, so as to enable a user to conveniently observe operation statuses of the peripheral devices 240.
Number | Date | Country | Kind |
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201010589582.3 | Nov 2010 | CN | national |