Patent Application
20250220982
The present disclosure relates to semiconductor devices and, more particularly, to bidirectional junction field effect transistor (JFET) switching devices.
Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art including, for example, power Metal Oxide Semiconductor Field Effect Transistors (“MOSFET”), Junction Field Effect Transistors (“JFET”), bipolar junction transistors (“BJTs”), Insulated Gate Bipolar Transistors (“IGBT”), Schottky diodes, Junction Barrier Schottky (“JBS”) diodes, merged p-n Schottky (“MPS”) diodes, Gate Turn-Off Thyristors (“GTO”), MOS-controlled thyristors and various other devices. These power semiconductor devices are generally fabricated from monocrystalline silicon semiconductor material, or, more recently, from silicon carbide or gallium nitride based semiconductor materials.
Power semiconductor devices can have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain, gate and source terminals for a power MOSFET device) are on the same major surface (i.e., top or bottom) of a semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. Herein, the term “semiconductor layer structure” refers to a structure that includes one or more semiconductor layers such as semiconductor substrates and/or semiconductor epitaxial layers. That is, a “semiconductor layer structure” may include a substrate, a substrate including one or more epitaxial layers and/or one or more epitaxial layers that have been removed from a growth substrate.
A conventional silicon carbide power device typically has a silicon carbide substrate, such as a silicon carbide wafer having a first conductivity type (e.g., an n-type substrate), on which an epitaxial layer structure having the first conductivity type (e.g., n-type) is formed. This epitaxial layer structure (which may include one or more separate layers) functions as a drift region of the power semiconductor device. The active region may be formed on and/or in the drift region. The active region acts as a main junction or region for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. The device may also have an edge termination region adjacent the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will typically have its own edge termination. The power semiconductor devices may have a unit cell structure in which the active region of each power semiconductor device includes a large number of individual unit cells that are disposed in parallel to each other and that together function as a single power semiconductor device.
One application for SiC power semiconductor devices is in solid state circuit breakers (SSCBs). SSCBs, which operate at rail voltages of 400V to 800V, are normally on to allow conduction of current. Upon detection of a fault condition, an SSCB is able to quickly turn off to isolate the fault. Consequently, SSCBs are on most of the time and switch to the OFF (non-conductive) state very infrequently. SSCBs therefore need very low conduction loss, while high speed switching controllability is less important. As such SiC JFETs, are well suited for SSCB applications as a lower cost alternative to SiC MOSFETs while still being capable of normally off operation in a cascode arrangement.
Power rails 208A, 208B are connected to respective current terminals of each bidirectional cascode switch, and clamping circuits 212A, 212B are provided between the power rails 208A, 208B to provide voltage limitation. Gate drivers 214A, 214B control the bidirectional switching circuit 200 via gate signals based on temperature and voltage (VON) sensing signals from the bidirectional switching circuit 200. The gate drivers 214A, 214B may also provide control signals for open circuit (OC) protection.
A semiconductor device according to some embodiments includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET mesas, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET mesas. The first and second JFET devices may be vertical JFET devices.
The first plurality vertical JFET subcells may include a plurality of alternating first mesa stripes and first trenches on the drift layer, each of the first mesa stripes comprising sidewall gate regions in opposing sides of the mesa stripe, the sidewall gate regions having a second conductivity type opposite the first conductivity type and defining a channel region in the mesa stripe between the sidewall gate regions, first gate contacts on bottoms of the first trenches adjacent the first mesa stripes, first source contacts on tops of the first mesa stripes, a first gate terminal in electrical contact with the first gate contacts, and a first current terminal in electrical contact with the first source contacts. The second plurality of JFET subcells may include a plurality of alternating second mesa stripes and second trenches on the drift layer, each of the second mesa stripes comprising sidewall gate regions in opposing sides of the mesa stripe, the sidewall gate regions having the second conductivity type and defining a channel region in the mesa stripe between the sidewall gate regions, second gate contacts on bottoms of the second trenches adjacent the second mesa stripes, second source contacts on tops of the second mesa stripes, a second gate terminal in electrical contact with the second gate contacts, and a second current terminal in electrical contact with the second source contacts.
The semiconductor device may further include a reduced surface charge (RESURF) region in the drift layer between the first JFET device and the second JFET device.
The RESURF region may include a plurality of second conductivity regions at a surface of the drift layer between the first JFET device and the second JFET device.
The first gate contacts may not be formed on an outermost trench of the first plurality of trenches adjacent the RESURF region, and the second gate contacts may not be formed on an outermost trench of the second plurality of trenches adjacent the RESURF region.
An outermost mesa stripe of the first plurality of mesa stripes that is adjacent the RESURF region may be narrower than other ones of the first plurality of mesa stripes, and an outermost mesa stripe of the second plurality of mesa stripes that is adjacent the RESURF region may be narrower than other ones of the second plurality of mesa stripes.
The semiconductor device may further include a third plurality of vertical JFET subcells on the drift layer, wherein the third plurality of vertical JFET subcells are connected in parallel with the first plurality of vertical JFET subcells to form the first JFET device, and a fourth plurality of vertical JFET subcells on the drift layer, wherein the fourth plurality of vertical JFET subcells are connected in parallel with the second plurality of vertical JFET subcells to form the second JFET device. The first gate electrode and the first current terminal are in contact with the third plurality of vertical JFET subcells, and the second gate electrode and the second current terminal are in contact with the fourth plurality of vertical JFET subcells.
The semiconductor device may further include reduced surface charge (RESURF) region in the drift layer between the first and second plurality of vertical JFET subcells, between the second and third plurality of vertical JFET subcells, between the third and fourth plurality of vertical JFET subcells.
The semiconductor device may further include a floating terminal on the substrate opposite the drift layer.
The substrate may have the first conductivity type and current between the two JFET devices is also conducted through the substrate In some embodiments, the substrate may have a second conductivity type that is opposite the first conductivity type.
The substrate and the drift layer may include silicon carbide.
The semiconductor device may further include shield regions beneath the trenches, wherein the shield regions have the second conductivity type.
The sidewall gate regions may extend beneath adjacent ones of the trenches, and the shield regions may be beneath the portions of the sidewall gate regions that extend beneath the adjacent ones of the trenches.
A bidirectional switch according to some embodiments may include a semiconductor device as described above, a first field effect transistor having a first drain terminal coupled to the first current terminal in cascode configuration with the first JFET device and a first source terminal coupled to the first gate terminal of the first JFET device, and a second field effect transistor having a second drain terminal coupled to the second current terminal in cascode configuration with the second JFET device and a second source terminal coupled to the second gate terminal of the second JFET device.
A method of forming a semiconductor device according to some embodiments includes forming a drift layer on a substrate, the drift layer having a first conductivity type, forming a first plurality of vertical junction field effect (JFET) subcells on the drift layer, wherein the first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, forming a second plurality of vertical JFET subcells on the drift layer, wherein the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device, wherein the second JFET device is connected in anti-series with the first JFET device through the drift layer, forming a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET mesas, and forming a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET mesas.
A semiconductor device according to some embodiments includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. First and second junction field effect transistor (JFET) devices are on the drift layer, wherein the second JFET device is connected in anti-series with the first JFET device through the drift layer. A reduced surface charge (RESURF) region is provided in the drift layer between the first JFET device and the second JFET device.
The RESURF region includes a plurality of second conductivity regions at a surface of the drift layer between the first JFET device and the second JFET device.
The semiconductor device further includes a first plurality of vertical JFET subcells on the drift layer, wherein the first plurality of vertical JFET subcells are connected in parallel to form the first JFET device, and a second plurality of vertical JFET subcells on the drift layer, wherein the second plurality of vertical JFET subcells are connected in parallel to form the second JFET device. A first gate electrode and a first current terminal are in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal are in contact with the second plurality of vertical JFET subcells.
The first plurality vertical JFET subcells may include a plurality of alternating first mesa stripes and first trenches on the drift layer, each of the first mesa stripes comprising sidewall gate regions in opposing sides of the mesa stripe, the sidewall gate regions having a second conductivity type opposite the first conductivity type and defining a channel region in the mesa stripe between the sidewall gate regions.
The first plurality vertical JFET subcells further include first gate contacts on bottoms of the first trenches adjacent the first mesa stripes, first source contacts on tops of the first mesa stripes, a first gate terminal in electrical contact with the first gate contacts, and a first current terminal in electrical contact with the first source contacts.
The second plurality of JFET subcells include a plurality of alternating second mesa stripes and second trenches on the drift layer, each of the second mesa stripes comprising sidewall gate regions in opposing sides of the mesa stripe, the sidewall gate regions having the second conductivity type and defining a channel region in the mesa stripe between the sidewall gate regions.
The second plurality of JFET subcells further include second gate contacts on bottoms of the second trenches adjacent the second mesa stripes, second source contacts on tops of the second mesa stripes, a second gate terminal in electrical contact with the second gate contacts, and a second current terminal in electrical contact with the second source contacts.
The first gate contacts may not be formed on an outermost trench of the plurality of first trenches adjacent the RESURF region, and the second gate contacts may not be formed on an outermost trench of the plurality of second trenches adjacent the RESURF region.
An outermost mesa stripe of the first plurality of mesa stripes that is adjacent the RESURF region may be narrower than other ones of the first plurality of mesa stripes, and an outermost mesa stripe of the second plurality of mesa stripes that is adjacent the RESURF region may be narrower than other ones of the second plurality of mesa stripes.
Embodiments of the inventive concepts will be described more fully hereinafter with reference to the accompanying drawings. The inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout.
Some embodiments described herein provide monolithic bidirectional JFET devices that include integrated anti-series SIC JFETs in one 4-terminal normally-on device. The SiC JFETs can be connected in a cascode arrangement with silicon MOSFETs to form normally off bidirectional switches for SSCB applications. A bidirectional JFET switch as described herein can reduce SiC chip area (and hence cost) for high voltage switching applications compared to other state of the art approaches. Some embodiments may be particularly suitable for applications up to 750V. The achievable reduction in chip area will be lower at higher voltages, but the architectures described herein can also be used for higher voltage ratings, such as 900V, 1200V, etc.
In conventional bidirectional switches such as the arrangement shown in
To address this, some embodiments provide an architecture for a bidirectional SiC JFET that includes two half-cells each including number of JFET sub-cells. The half-cells and sub-cells are arranged in such a way that the specific on-resistance for a 750V rated switch would be reduced when compared to anti-series connected devices. When the specific on-resistance of the device is reduced, the cost for a particular current rating is also reduced. Additionally, reduction in chip area will also reduce capacitance of the switch and enable faster switching.
Each of the two JFET devices 330A, 330B includes a plurality of JFET subcells 20A, 20B formed as alternating mesa stripes 24A, 24B and trenches 29A, 29B. For example, in the structure shown in
Each JFET subcell 20A, 20B includes respective opposing sidewall gate regions 23A, 23B that define respective channel regions 22A, 22B in the mesa stripes 24A, 24B. Gate contacts 18A, 18B are formed on gate contact regions 26A, 26B at bottom surfaces of the trenches 29A, 29B.
Source regions 28A, 28B and heavily doped source contact regions 32A, 32B are provided at the tops of the mesa stripes 24A, 24B. Source contacts 38A, 38B are formed on the source contact regions 32A, 32B. A first insulating dielectric layer 34 is provided in the trenches 29A, 29B adjacent the mesa stripes 24A, 24B. A first source metallization 33A conductively connects the source contacts 38A of the first JFET device 330A, while a second source metallization 33B conductively connects the source contacts 38B of the second JFET device 330B. A second insulating dielectric layer 36 is formed over the first and second source metallizations 33A, 33B.
A first current terminal 44A is connected to the source contacts 38A of the first JFET device 330A through the source metallization 33A, and a second current terminal 44B is connected to the source contacts 38B of the second JFET device 330B through the source metallization 33B. A first gate terminal 42A is connected to the gate contacts 18A via a gate metallization 43A, and a second gate terminal 42B is connected to the gate contacts 18B via a gate metallization 43B.
A reduced surface charge (RESURF) region 55 is provided at the surface of the drift layer 12 between the two JFET devices 330A, 33B. The RESURF region 55 is provided between the blocking junctions between the gate regions 23A, 23B and the drift layer 12, and includes a plurality of implanted regions that form RESURF rings 54 having a conductivity opposite that of the drift layer 12. The RESURF rings 54 are spaced with n-epi regions in the drift layer 12 between the JFET devices 330A, 330B to block voltage.
The substrate 10 is floating and is isolated from the device terminals 42A, 42B, 44A, 44B. A floating drain contact 25 is provided on the back side of the substrate 10 opposite the drift layer 12.
In some embodiments, the substrate 10, the drift layer 12, the channel regions 22A, 22B, the source regions 28A, 28B and the source contact regions 32A, 32B may have a first conductivity type, and the gate contact regions 26A, 26B and sidewall gate regions 23A, 23B may have a second conductivity that is opposite the first conductivity. For example, the substrate 10, the drift layer 12, the channel regions 22A, 22B, the source regions 28A, 28B and the source contact regions 32A, 32B may be n-type silicon carbide regions, and the gate contact regions 26A, 26B, the sidewall gate regions 23A, 23B and the RESURF rings 54 may be p-type silicon carbide regions.
The substrate 10 may be n+ silicon carbide, and the drift layer 12 may be n-silicon carbide having a doping concentration of about 1.5E16/cm3. The channel regions 22A, 22B may be n-type silicon carbide having a doping concentration of about 5E16/cm3.
The overall width of each of the JFET devices 330A, 330B may be equal to about 2.5 microns multiplied by the number of JFET sub-cells 20A, 20B in the device.
In some embodiments discussed in greater detail below, the substrate 10 may have the second conductivity type (e.g., p-type).
The first and second insulating dielectric layers 34, 36 may include silicon oxide, silicon nitride, silicon oxynitride, etc.
During on-state operation, current flows between the current terminals 44A, 44B through the channel regions 22A, 22B and the drift layer 12. During off-state operation, the channel regions 22A, 22B are pinched off by a depletion region formed at the junction between the sidewall gate regions 23A, 23B and the respective channel regions 22A, 22B.
Also shown in
When a p+ substrate is provided, the n-drift layer 12 can be depleted in blocking state by both the p-type RESURF region 55 and by the p+ substrate. This may allow better voltage control in the reversed blocking state, and hence allow reduction of the width of the RESURF region, which can reduce the specific on-resistance, reduce chip area and/or reduce manufacturing costs.
However, the use of a p+ substrate 10A may also eliminate the current path through substrate 10A in the on-state, which may increase the specific on-resistance and/or increase chip area when multiple JFET subcells 20A, 20B are used.
Accordingly, when a p+ substrate 10A is used, there may be a lower optimum number of subcells per device compared to the device 300 shown in
In the embodiment shown in
Reducing the mesa width may also help to reduce cell pitch, which may allow more cells to be placed in a given chip size. The absence of a gate contact on the outside of the outermost mesa stripes 124A, 124B allows creation the mesa stripe without needing a metal finger. This may improve current density in the chip.
The exact mesa width may be as low as physically possible in the manufacturing setup. Reducing the mesa width comes with tradeoff however. For example, the absence of a gate finger means that the gate voltage reaches that locality with a slight delay (e.g., nanoseconds), which increases the resistance of that locality and reduces the transconductance of that locality (i.e., the speed with which the JFET can turn on if the gate voltage signal is increased from an off-state value to an on-state value).
An advantage of narrowing the outermost mesa stripes 124A, 124B is that it increases the local threshold voltage of the mesa stripes (JFETs have a negative threshold voltage). This increase means that the locality will have a less negative voltage, e.g., 3 volts instead of −9 volts, meaning that the locality with a narrow mesas need to go from 0 to −3 V to turn off as opposed to 0 to −9 V for the rest of the chip. The nanoseconds lost due to gate voltage delay is made up by shorter voltage traversals during turn-off.
It will be appreciated that the narrow mesa modification as shown in
Rather than floating, the drain terminal 25 in the bidirectional JFET switch 300 can be drawn out as an external pin for this purpose.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present inventive concepts. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” “lateral,” “vertical,” “beneath,” “over,” “on,” etc., may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
Embodiments of the inventive concepts are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the inventive concepts. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted regions. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the inventive concepts.
Some embodiments of the inventive concepts are described with reference to semiconductor layers and/or regions which are characterized as having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some material may be designated with a “+” or “−” (as in n+, n−, p+, p−, n++, n−−, p++, p−−, or the like), to indicate a relatively larger (“+”) or smaller (“−”) concentration of majority carriers compared to another layer or region. However, such notation does not imply the existence of a particular concentration of majority or minority carriers in a layer or region.
It also will be understood that, as used herein, the terms “row” and “column” indicate two non-parallel directions that may be orthogonal to one another. However, the terms row and column do not indicate a particular horizontal or vertical orientation.
Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
