Monolithic MOSFET and schottky diode for mobile phone boost converter

Abstract

A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device.

Description

FIELD OF THE INVENTION

The present invention relates in general to electronic circuits and semiconductor devices and, more particularly, to an integrated or monolithic MOSFET and Schottky diode for mobile phone boost converters.

BACKGROUND OF THE INVENTION

Most modern electronic equipment require a power supply to provide a direct current (DC) operating potential to the electronic components contained therein. Common types of electronic equipment which use DC power supplies include cell phones, personal computers, energy systems, telecommunication systems, audio-video equipment, consumer electronics, automotive components, and other devices which utilize integrated circuits, semiconductor chips, or otherwise require DC operating potential. Most, if not all, semiconductor components require a low voltage DC operating potential.

Not all semiconductor devices or electronic components operate with the same DC potential. Some integrated circuits (ICs) or discrete semiconductor devices require a higher DC supply voltage than others. A common approach in electronic systems requiring multiple DC operating voltage levels is to convert a base DC operating potential to other voltage levels. For example, the battery or main power supply to the electronic system may provide 3 volts DC. One or more DC/DC boost converters within the electronic system increase the voltage level to say 5 volts DC or 12 volts DC to supply power to certain components within the system.

The DC/DC boost converter uses an inductor or coil having a first terminal coupled to the converter input and power metal oxide semiconductor field effect transistor (MOSFET) coupled between a second terminal of the coil and ground. The conduction through MOSFET is controlled by a pulse width modulated (PWM) controller. The PWM controller turns on the power MOSFET to enable a current conduction path through the coil and thereby store energy in the coil. When the PWM controller turns off the power MOSFET, the energy stored in the coil is transferred through a Schottky diode to an output of the DC/DC boost converter. The output voltage of the converter is used to generate a feedback signal to the PWM controller to control the on-time of the power MOSFET and regulate the DC output voltage of the boost converter.

The power MOSFET and Schottky diode are typically discrete components in the DC/DC boost converter. In some electronic systems, such as cellular phones, space on the printed circuit board (PCB) is a premium. As cell phones reduce in feature size, the space required for discrete components becomes a design issue. In addition to surface area limitations, the need for low profile and small footprint semiconductor devices continues to grow as cell phones become thinner and smaller in design.

A need exists for semiconductor devices and packages that are compatible with electronic systems having limited surface areas and low profiles.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a monolithic semiconductor device, comprising a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed with a plurality conduction fingers on a surface of the monolithic semiconductor device. A diode is formed on the surface of the monolithic semiconductor device and integrated between the plurality of conduction fingers of the LDMOSFET. A first conduction terminal of the LDMOSFET is connected to a first terminal of the diode on the surface of the monolithic semiconductor device.

In another embodiment, the present invention is a semiconductor package, comprising a monolithic semiconductor device including a lateral double diffused metal oxide semiconductor field effect transistor formed on a surface of the monolithic semiconductor device and a diode formed on the surface of the monolithic semiconductor device and integrated between a plurality of conduction fingers of the LDMOSFET.

In another embodiment, the present invention is a monolithic semiconductor device, comprising a lateral double diffused metal oxide semiconductor field effect transistor formed with a plurality conduction fingers on a surface of the monolithic semiconductor device. A diode is formed on the surface of the monolithic semiconductor device and integrated between the plurality of conduction fingers of the LDMOSFET.

In another embodiment, the present invention is a method of making a monolithic semiconductor device comprising the steps of forming a lateral double diffused metal oxide semiconductor field effect transistor with a plurality conduction fingers on a surface of the monolithic semiconductor device, and forming a diode on the surface of the monolithic semiconductor device integrated between the plurality of conduction fingers of the LDMOSFET.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cellular telephone with a printed circuit board containing integrated circuits and semiconductor devices;

FIG. 2 is a schematic diagram of a DC/DC boost converter;

FIG. 3 is a monolithic integrated circuit package containing the power MOSFET and Schottky diode of FIG. 2;

FIG. 4 is a cross-sectional view of the monolithic power MOSFET and Schottky diode; and

FIG. 5 is a top view of the monolithic power MOSFET and Schottky diode.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

Referring to FIG. 1, a cellular phone 10 is shown having a front body 12 housing keyboard 14 and liquid crystal display (LCD) 16. Cell phone 10 further includes a rear body 20 housing PCB 22. PCB 22 is separated into radio frequency (RF) signal processing section 24 and digital signal processing section 26, separated by shielding. The RF signal processing section 24 includes electronic components such as RF amplifier, modulator, demodulator, oscillator, and power management. The RF signal processing section receives RF signals, downconverts, and demodulates the signals to baseband signals. The digital signal processing section 24 includes electronic components such as microprocessor, analog to digital converter, digital to analog converter, memory, and control logic. The digital signal processing section 26 processes the baseband information so the user can hear and speak over the cell phone.

Many of the electronic components on PCB 22 may require different DC operating potentials. Cell phone 10 has one lithium-ion battery source, e.g. 3.6 volts DC, attached to rear body 20. To convert the 3.6 VDC battery voltage to other operating potentials, one or more DC/DC boost converters are designed into PCB 22. The DC/DC boost converter generates DC operating potentials, e.g. 5 VDC or higher, for the electronic components which require a power supply different than the 3.6 VDC battery voltage.

The space limitations of PCB 22 in cell phone 10 dictate that the use of discrete components should be minimized and eliminated where possible. The semiconductor die or device within each discrete component is small compared to its overall package size. The same issue exists with other electronic systems having space limitations, such as radios, two-way pagers, digital recorders, laptop computers, compact disk players, compact video players, and the like. To support this design preference, in the following description, the power MOSFET and Schottky diode of the DC/DC boost converter are integrated into a single monolithic package.

In addition, other electronic systems that do not necessarily have space limitations, e.g. personal computers, energy systems, telecommunication systems, audio-video equipment, consumer electronics, and automotive components, can benefit from the cost savings and design efficiencies associated with the integration of discrete components.

A DC/DC boost converter 40 is shown in FIG. 2. A DC input voltage V_IN from the battery source is applied to input terminals 42 and 44. An inductor or coil 46 is coupled between terminal 42 and Schottky diode 48. An n-channel power MOSFET 50 has a drain terminal coupled to the anode of diode 48 and a source terminal coupled to terminal 44. MOSFET 50 is a 25V lateral diffused power MOSFET with a drain source resistance (R_DSon) of 0.25 ohms with gate voltage of 2.5 V. The total gate charge of MOSFET 50 is 0.5 nC (5V). Parasitic diode 52 is shown across the conduction terminals of power MOSFET 50. Diode 48 is a 25V Schottky diode with forward voltage drop less than 0.35V. The cathode of diode 48 is coupled to output terminal 54. Capacitor 58 is coupled across the output terminals of the converter for filtering and energy storage. DC/DC boost converter 40 provides DC output voltage V_OUT having a voltage level different from V_IN. The DC output voltage V_OUT is used to provide operating potential to one or more of the electronic components in RF signal processing section 24 and/or digital signal processing section 26.

The output voltage VOUT is used to generate a feedback (FB) signal, which is applied to PWM controller 56. PWM controller 56 generates a PWM control signal which is applied to the gate of power MOSFET 50. PWM controller 56 controls the conduction time of MOSFET 50 during each control cycle. If the output voltage V_OUT falls, due to an increasing load, the duty cycle of the PWM control signal increases to lengthen the on-time of MOSFET 50 within the control cycle. Diode 48 is reversed biased to isolate the converter output during the on-state of the MOSFET. The longer conduction period of MOSFET 50 stores more energy in coil 46. During the off-time of the MOSFET, diode 48 becomes forward biased and the energy stored in coil 46 is transferred to the converter output to charge capacitor 58 and increases the output voltage V_OUT. If the output voltage V_OUT rises, due to a decreasing load, the duty cycle of the PWM control signal decreases to shorten the on-time of MOSFET 50 during the control cycle. Again, diode 48 is reversed biased to isolate the converter output during the on-state of the MOSFET. The shorter conduction period of MOSFET 50 stores less energy in coil 46. During the off-time of the MOSFET, diode 48 becomes forward biased and the lesser amount of energy stored in coil 46 is transferred to the converter output to charge capacitor 58 so as to decrease the output voltage V_OUT.

In the present embodiment, power MOSFET 50 and Schottky diode 48 are integrated into a single, chip-scale, monolithic package 60 having a 1.15×1.15 square millimeter (mm²) footprint. The height of package 60 is 0.8 mm to accommodate the low profile requirement. The power MOSFET occupies about 23% of the die area (0.28 mm²), while the Schottky diode occupies about 60% of the die area (0.72 mm²).

As shown in FIG. 3, package 60 is a four-terminal flip-chip combo device containing power MOSFET 50 and Schottky diode 48. Bumps 62-68 are formed on the flip-chip package. Bump 62 is the source of power MOSFET 50 and is electrically coupled to ground terminal 44; bump 64 is the gate of power MOSFET 50 and is electrically coupled to the output of PWM controller 56; bump 66 is the common drain of power MOSFET 50 and anode of diode 48 and is electrically coupled to the second terminal of coil 46; bump 68 is the cathode of diode 48 and is electrically coupled to output terminal 54. Alternatively, in an IC package with external pins, e.g. SOP or DIP, the external connections from the semiconductor die to the package can be made by wire bonds.

Package 60 occupies significantly less space than conventional discrete components providing the same function. In fact, package 60 uses 68% less space on PCB 22 as compared to a conventional discrete MOSFET alone. The difference is more pronounced when taking into account a discrete Schottky diode and interconnecting PCB tracks. The small footprint and low profile of package 60 is applicable to systems requiring efficient and compact components, such as DC/DC boost converters used in cellular phones.

Further detail of the monolithic semiconductor device 78 including power MOSFET 50 and Schottky diode 48 is shown in FIG. 4. The semiconductor device 78 uses a lateral double diffused MOSFET structure. The lateral double diffused power MOSFET 50 and Schottky diode 48 are formed on the surface of semiconductor device 78.

In the cross-sectional view, substrate 80 is made of p-type semiconductor material and provides structural support. The following regions and layers are formed on substrate 80 using semiconductor manufacturing processes understood by those skilled in the art. The manufacturing processes includes layering, patterning, doping, and heat treatment. In the layering process, materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.

Using the above semiconductor manufacturing processes, a P-well region 82 is formed on substrate 80. A body region 84 made with P-material is formed over or above P-well region 82. P+ body 86 and N+ source region 88 are formed over or above P− body region 84. Terminal 89 is connected to N+ source region 88 to provide the source terminal of power MOSFET 50. Terminal 89 electrically connects to bump 62. An N-drift region 90 and N+ drain region 92 are formed above P-well region 82. Oxide layer 96 is formed over N+ source region 88, P− body region 84, and N-drift region 90. Gate region 98 is formed over oxide layer 96. Terminal 99 is coupled to gate region 98 to provide the gate terminal of power MOSFET 50. Terminal 99 electrically connects to bump 64.

Using the above semiconductor manufacturing processes, an N-drift region 100 and N+ region 102 are formed over or above P-well region 82. A metal layer 104 is formed over or above N-drift region 100 and further connects to N+ drain region 92 to provide terminal 105. Metal layer 104 may be made with titanium (Ti) or titanium nitride (TiN). The metal layer junction with the lightly doped N-drift region 100 forms the Schottky diode. The metal layer 104 contact to the heavier doped N+ drain region 92 forms an ohmic contact. Terminal 105 is the common terminal for the drain of power MOSFET 50 and the anode of diode 48. Terminal 106 is connected to N+ region 102 which forms the cathode of diode 48. Terminals 105 and 106 electrically connect to bumps 66 and 68, respectively.

FIG. 5 illustrates a top view of a portion of semiconductor device 78. MOSFET 50 is formed with a repeating pattern of source and drain conduction fingers, i.e. source, drain, drain, source, source, drain, drain, source, etc. The N-drift regions 100 and N+ regions 102 of diode 48 are integrated between the repeating pattern of MOSFET conduction fingers for efficiency of space and design layout. In FIG. 5, the repeating pattern is shown as P+ body 86, N+ region 88 (source), gate region 98, N-drift region 90, N+ region 92 (drain), P-well region 82 (isolation), N-drift region 100 (anode), N+ region 102 (cathode), N-drift region 100 (anode), P-well region 82 (isolation), N+ region 92 (drain), N-drift region 90, gate region 98, N+ region 88 (source), and P+ body 86. The lateral diffused MOS structure provides access to the drain on the surface of the semiconductor device 78. The drain of power MOSFET 50 on the surface can be readily connected to the anode of diode 48 by terminal jumper 105.

In another application, diode 48 may be formed in semiconductor structure 78 as a Zener diode. The Zener diode would be formed in the surface of semiconductor structure 78 and be commonly connected to MOSFET 50 as described above.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

1. A monolithic semiconductor device, comprising: a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed with a plurality conduction fingers on a surface of the monolithic semiconductor device; and a diode formed on the surface of the monolithic semiconductor device and integrated between the plurality of conduction fingers of the LDMOSFET, wherein a first conduction terminal of the LDMOSFET is connected to a first terminal of the diode on the surface of the monolithic semiconductor device.

2. The monolithic semiconductor device of claim 1, further including a semiconductor package enclosing the LDMOSFET and diode and having four external connections.

3. The monolithic semiconductor device of claim 2, wherein the semiconductor package has a first connection coupled to a first conduction terminal of the LDMOSFET.

4. The monolithic semiconductor device of claim 3, wherein the semiconductor package has a second connection commonly coupled to a second conduction terminal of the LDMOSFET and a first terminal of the diode.

5. The monolithic semiconductor device of claim 4, wherein the semiconductor package has a third connection coupled to a second terminal of the diode.

6. The monolithic semiconductor device of claim 5, wherein the semiconductor package has a fourth connection coupled to a control terminal of the LDMOSFET.

7. The monolithic semiconductor device of claim 1, wherein the plurality of conduction fingers of the LDMOSFET include a repeating pattern of source and drain conduction fingers.

8. The monolithic semiconductor device of claim 7, wherein drift regions of the diode are integrated between the repeating pattern of source and drain conduction fingers of the LDMOSFET.

9. A semiconductor package, comprising a monolithic semiconductor device including a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed on a surface of the monolithic semiconductor device and a diode formed on the surface of the monolithic semiconductor device and integrated between a plurality of conduction fingers of the LDMOSFET.

10. The semiconductor package of claim 9, wherein a first connection of the semiconductor package is coupled to a first conduction terminal of the LDMOSFET.

11. The semiconductor package of claim 10, wherein a second connection of the semiconductor package is commonly coupled to a second conduction terminal of the LDMOSFET and a first terminal of the diode.

12. The semiconductor package of claim 11, wherein a third connection of the semiconductor package is coupled to a second terminal of the diode.

13. The semiconductor package of claim 12, wherein a fourth connection of the semiconductor package is coupled to a control terminal of the LDMOSFET.

14. The semiconductor package of claim 9, wherein the plurality of conduction fingers of the LDMOSFET include a repeating pattern of source and drain conduction fingers.

15. The semiconductor package of claim 14, wherein drift regions of the diode are integrated between the repeating pattern of source and drain conduction fingers of the LDMOSFET.

16. A monolithic semiconductor device, comprising: a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed with a plurality conduction fingers on a surface of the monolithic semiconductor device; and a diode formed on the surface of the monolithic semiconductor device and integrated between the plurality of conduction fingers of the LDMOSFET.

17. The monolithic semiconductor device of claim 16, further including a semiconductor package enclosing the LDMOSFET and diode and having four external connections.

18. The monolithic semiconductor device of claim 17, wherein the semiconductor package has a first connection coupled to a first conduction terminal of the LDMOSFET.

19. The monolithic semiconductor device of claim 18, wherein the semiconductor package has a second connection commonly coupled to a second conduction terminal of the LDMOSFET and a first terminal of the diode.

20. The monolithic semiconductor device of claim 19, wherein the semiconductor package has a third connection coupled to a second terminal of the diode.

21. The monolithic semiconductor device of claim 20, wherein the semiconductor package has a fourth connection coupled to a control terminal of the LDMOSFET.

22. The monolithic semiconductor device of claim 16, wherein the plurality of conduction fingers of the LDMOSFET include a repeating pattern of source and drain conduction fingers.

23. The monolithic semiconductor device of claim 22, wherein drift regions of the diode are integrated between the repeating pattern of source and drain conduction fingers of the LDMOSFET.

24. A method of making a monolithic semiconductor device, comprising: forming a lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a plurality conduction fingers on a surface of the monolithic semiconductor device; and forming a diode on the surface of the monolithic semiconductor device integrated between the plurality of conduction fingers of the LDMOSFET.

25. The method of claim 24, further including forming the plurality of conduction fingers of the LDMOSFET as a repeating pattern of source and drain conduction fingers.

26. The method of claim 25, further including integrating drift regions of the diode between the repeating pattern of source and drain conduction fingers of the LDMOSFET.