Monolithic semiconductor integrated circuit device having current adjusting circuit

Abstract

A monolithic semiconductor integrated circuit device includes a differentially operative circuit section, an amplifying element connected to define a current flowing in the differentially operative circuit section and a circuit for adjusting a current flowing in the amplifying element to thereby compensate for variations of electric characteristics from one semiconductor device to another. The current adjusting circuit includes at least one amplifying element and a load resistance for the amplifying element in the current adjusting circuit. The load resistance has a structure suitable for a trimming operation to adjustably determine the resistance value of the load resistance. The amplifying elements are in a current mirror circuit connection with their control electrodes being concerned with each other so that the electric current flowing in the current path between the current receiving and delivering electrodes of the amplifying element connected to define the current flowing in the differentially operative circuit section is controlled by the adjustably determined resistance of the load resistance.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuit device, and more particularly to a monolithic semiconductor integrated circuit device including an audio signal processing circuit.

When circuit elements of a circuit dealing with an audio signal, for example a filter circuit, are incorporated in a semiconductor integrated circuit, a time constant of the filter circuit has manufacturing variations. For example, the resistance value of a resistor element has a variation of about .+-.25% and the capacitance value of a capacitor has a variation of about .+-.30%. As a result, the time constant of a time constant circuit including such resistor element and capacitor has a large variation of about .+-.60%. Especially, in the case where two or more filter circuits having such large variations are involved in a semiconductor integrated circuit, the possession of the above-mentioned variation by each filter circuit does not give assurance that no reliability for the electric characteristic of the overall system is lost.

A basic circuit for a filter has been disclosed in, for example, "PRACTICAL ELECTRONIC CIRCUIT HANDBOOK (2)" published by CQ Publishing Co., Ltd. on Oct. 20, 1975, pp. 281-289. In the active filter circuit, time constant circuit elements including a capacitor C and a resistor R are constructed by external parts in order to suppress the variation of a cut-off frequency of the filter circuit.

On the other hand, in order to improve the high-frequency performance of a transistor included in an integrating circuit, JP-A-63-193710 (laid open on Aug. 11, 1988) has proposed to make an emitter current of the transistor as large as possible for the purpose of increasing a transition frequency of the transistor. The proposed integrated circuit includes a differential amplifier and is provided with a terminal for supplying a signal which controls the emitter current of a transistor forming the differential amplifier.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a monolithic semiconductor integrated circuit device including an audio signal processing circuit, in which variations of electric characteristics from one chip to another can be compensated for with a simple construction.

Another object of the present invention is to provide a monolithic semiconductor integrated circuit device in which compensation for variations of filter characteristics can be made with a simple construction.

According to one aspect of the present invention, a monolithic semiconductor integrated circuit device includes a differentially operative circuit section, an amplifying element connected to define a current flowing in the differentially operative circuit section and a circuit for adjusting a current flowing in the amplifying element to thereby compensate for variations of electric characteristics from one semiconductor device to another. The current adjusting circuit includes at least one amplifying element and a load resistance for the amplifying element in the current adjusting circuit. The load resistance has a structure suitable for a trimming operation to adjustably determine the resistance value of the load resistance. The amplifying elements are in a current mirror circuit connection with their control electrodes being connected with each other so that the electric current flowing in the current path between the current receiving and delivering electrodes of the amplifying element connected to define the current flowing in the differentially operative circuit section is controlled by the adjustably determined resistance of the load resistance.

According to another aspect of the present invention, a monolithic semiconductor integrated circuit device includes a plurality of filter circuits. Each filter circuit includes a pair of differentially operative transistors and a cut-off frequency of the filter circuit is changed by controlling an emitter current of the transistor pair. Amplifying elements dealing with the emitter current are in a current mirror circuit connection which receives an adjustable control current through a resistor-trimming operation. The emitter currents of the differentially operative transistor pairs are adjusted en bloc through the resistor-trimming operation so that the cut-off frequencies of the respective filter circuits are corrected en bloc.

With the above construction, the time constants of the respective filter circuits can be readily made identical with each other by the resistor-trimming operation at one location since the characteristics of circuit elements formed in one chip have substantially the same deviation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a monolithic semiconductor integrated circuit device according to an embodiment of the present invention.

FIGS. 2A to 2D are diagrams showing examples of the structure of load resistor means for amplifying means in a current adjusting circuit shown in FIG. 1.

FIGS. 3A and 3B are a circuit diagram and a block diagram of a monolithic semiconductor integrated circuit device including a filter circuit according to an embodiment of the present invention.

FIGS. 4A and 4B are a circuit diagram and a block diagram of a monolithic semiconductor integrated circuit device including another filter circuit according to another embodiment of the present invention.

FIG. 4C shows a gain versus frequency characteristic useful for explaining the operation of the device shown in FIGS. 4A and 4B.

FIGS. 5A and 5B are a circuit diagram and a block diagram of a monolithic semiconductor integrated circuit device including a further filter circuit according to a further embodiment of the present invention.

FIGS. 6A and 6B are a circuit diagram and a block diagram of a monolithic semiconductor integrated circuit device including a still further filter circuit according to a still further embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a circuit diagram of a main part of a monolithic semiconductor integrated circuit according to an embodiment of the present invention. Circuit blocks and circuit elements shown in the figure are formed by means of known semiconductor circuit fabrication techniques on a single semiconductor substrate which may be a monocrystalline silicon substrate.

In the present embodiment, the electric characteristics of filter circuits indicated by blocks (that is, a low-pass filter F.sub.1, a high-pass filter F.sub.2 and a notch filter F.sub.3), for example, the cut-off frequencies (or time constants) thereof can be respectively adjusted by currents I.sub.1, I.sub.2 and I.sub.3 which are set by a current adjusting circuit CA. Detailed explanation of such filter circuits will be made later.

The current adjusting circuit CA includes at least one amplifying element (first amplifying element) or NPN transistors Q.sub.20 and Q.sub.21 in the shown example, a collector load resistor R.sub.90 for the transistor Q.sub.20 and emitter load resistors R.sub.5 to R.sub.8 for the transistor Q.sub.20. The collector and base of the transistor Q.sub.20 are connected with the base and emitter of the transistor Q.sub.21, respectively. The collector of the transistor Q.sub.21 is connected with a terminal of a reference voltage V.sub.ref. The collector resistor R.sub.90 is connected between the collector of the transistor Q.sub.20 and the terminal of the reference voltage V.sub.ref, and the emitter resistors R.sub.5 and R.sub.8 are connected in parallel between the emitter of the transistor Q.sub.20 and a common potential (for example, grounded) line.

The currents I.sub.1 to I.sub.3 flowing in the above-mentioned filter circuits are formed by transistors Q.sub.22 to Q.sub.24, respectively. The emitters of the transistors Q.sub.22 to Q.sub.24 are connected with emitter resistors R.sub.10 to R.sub.12, respectively. The bases of the transistors Q.sub.22 to Q.sub.24 are commonly connected and those transistors Q.sub.22 to Q.sub.24 are in a current mirror circuit connection together with the transistor Q.sub.20. Thereby, the currents I.sub.1 to I.sub.3 flowing in the respective filter circuits are set by the current adjusting circuit CA. A field-effect transistor may be used in place of the bipolar transistor Q.sub.20. In that case, the transistor Q.sub.21 is not required.

In the above construction, the emitter of the transistor Q.sub.20 is provided with the emitter resistors or trimming resistors R.sub.5 to R.sub.8 connected, for example, in parallel with each other for adjustably changing an emitter current flowing in the transistor Q.sub.20, or in other words, for adjustably changing the currents I.sub.1 to I.sub.3 flowing in the above-mentioned filter circuits. The resistors R.sub.5 to R.sub.8 are not limited to the shown parallel connection form but may be provided with another connection form.

The parallel connection line of the trimming resistors R.sub.5 to R.sub.8 is selectively cut off by, for example, irradiation thereof with a laser beam. For example, a state in which all of the resistors R.sub.5 to R.sub.8 are connected in parallel with each other exhibits the smallest combined resistance, and the combined resistance value is made large by properly cutting off the connection line of the resistors R.sub.5 to R.sub.7. When the resistance value of the emitter resistance of the transistor Q.sub.20 is thus made large, the voltage dividing ratio of the emitter resistance to the collector resistor R.sub.90 is changed to increase a base potential V.sub.c of the transistor Q.sub.20, thereby increasing the currents I.sub.1 to I.sub.3 in a constant ratio.

Resistors R.sub.91 to R.sub.93 may be connected with the collector resistor R.sub.90 of the transistor Q.sub.20 in a parallel form or another form. In this case, when the combined resistance value is made large by selectively cutting off a connection line of the resistors R.sub.90 to R.sub.93, the resistance ratio of the combined resistance on the collector side of the transistor Q.sub.20 to the combined resistance on the emitter side thereof is changed to lower the base potential V.sub.c of the transistor Q.sub.20, thereby decreasing the currents I.sub.1 to I.sub.3 in a constant ratio. Namely, it is possible not only to increase the potential V.sub.c but also to lower the same.

FIGS. 2A and 2B show one example of that structure of the collector load resistor means and/or emitter load resistor means of the transistor Q.sub.20 shown in FIG. 1 which is suitable for a trimming operation. In FIG. 2A, the load resistor means includes a plurality of resistor elements r.sub.11 to r.sub.1n (the resistance values of which may be the same or different) and two conductors l.sub.1 and l.sub.2 for making respective common connections of opposite ends of the resistor elements. For a trimming operation on the load resistor means, the conductor l.sub.2 is cut off at one of a plurality of locations indicated by one-dotted chain lines by use of, for example, a laser beam. As a result, the resistance value of the load resistor means is adjusted. FIG. 2B is an electrical connection diagram of the resistor elements shown in FIG. 2A.

FIGS. 2C and 2D show an example of another structure of the load resistor means of the transistor Q.sub.20. In FIG. 2C, the load resistor means includes a plurality of resistor elements r.sub.21 to r.sub.2n (the resistance values of which may be the same or different), a conductor l.sub.3 for commonly connecting one-side ends of the resistor elements r.sub.21 to r.sub.2n, conductors l.sub.4, l.sub.5 and l.sub.6 for connecting the other-side ends of two adjacent resistor elements. A trimming operation on the load resistor means is achieved by cutting off the conductor l.sub.3 at one or more of a plurality of locations indicated by one-dotted chain lines by use of, for example, a laser beam. FIG. 2D is an electrical connection diagram of the resistor elements shown in FIG. 2C.

The structure shown in FIG. 2A and the structure shown in FIG. 2C may be used in combination with each other.

As is apparent from the foregoing, various configurations using a plurality of resistor elements and a plurality of conductors can be considered as the structure of the load resistor means of the transistor Q.sub.20 which is suitable for the resistor-trimming operation.

FIG. 3A shows a circuit diagram of a monolithic semiconductor integrated circuit device including a low-pass filter and high-pass filter circuit, and FIG. 3B shows a block diagram of the device shown in FIG. 3A.

Constant current sources I.sub.0 are provided between the emitters of PNP type input transistors Q.sub.1 and Q.sub.2 and a power source voltage C.sub.cc, respectively. The bases of the transistors Q.sub.1 and Q.sub.2 are connected with first and second input terminals, respectively. A resistance R.sub.1 for obtaining an input signal current is provided between the emitters of the input transistors Q.sub.1 and Q.sub.2. The collectors of the transistors Q.sub.1 and Q.sub.2 are connected with diode-connected NPN transistors Q.sub.3 and Q.sub.4 which form active load circuits. The common emitter (or cathode) of the transistors Q.sub.3 and Q.sub.4 is coupled with a grounded potential point through a diode-connected NPN transistor Q.sub.5. The above-mentioned circuit elements form a differential input stage A.sub.1 or a first differentially operative circuit.

Output voltages formed by the diode-connected transistors Q.sub.3 and Q.sub.4 in which collector currents of the transistors Q.sub.1 and Q.sub.2 flow are supplied to the bases of differentially operative NPN transistors Q.sub.6 and Q.sub.7 which form a controllable voltage-current conversion circuit VVIC or a second differentially operative circuit.

The controllable voltage-current conversion circuit VVIC includes the differentially operative transistors Q.sub.6 and Q.sub.7, PNP transistors Q.sub.8 and Q.sub.9 which are provided in a current mirror circuit connection on the collector sides of the differentially operative transistors Q.sub.6 and Q.sub.7 and form active load circuits, and an adjustable current source circuit, as mentioned above, which includes a transistor Q.sub.22 forming a second amplifying element causing the above-mentioned current I.sub.1 to flow in the common emitter of the differentially operative transistors Q.sub.6 and Q.sub.7 and an emitter resistor R.sub.10 of the transistor Q.sub.22. The base of the transistor Q.sub.22 is connected with the base of the transistor Q.sub.20 of the current adjusting circuit CA so that a current mirror circuit connection is provided as a whole. A signal current formed by the differentially operative transistors Q.sub.6 and Q.sub.7 of the controllable voltage-current conversion circuit VVIC serves as a charging/ discharging current for a capacitor C.sub.1 which will be explained later, and the current signal is fed back to the base of the transistor Q.sub.2 which is a feedback terminal (or the second input terminal) of the above-mentioned differential input stage A.sub.1. The capacitor C.sub.1 forming a filter circuit is provided between the feedback terminal and an earth potential. The capacitor C.sub.1 is incorporated in the semiconductor integrated circuit. For example, the capacitor C.sub.1 is constructed by an inter-layer insulating film which has no voltage dependency and two electrodes which have the interlayer insulating film sandwiched therebetween. The other various methods of forming a capacitor in a semiconductor integrated circuit are known and any one thereof suitable for the filter circuit in the present embodiment can be used.

The differential input stage A.sub.1 operates such that an input signal V.sub.in supplied to the base of the transistor Q.sub.1 which is a non-inverted input (+) or first input terminal of the differential input stage and a DC potential of the base of the transistor Q.sub.2 which is an inverted input (-) or second input terminal of the differential input stage become equal to each other. Since the capacitor C.sub.1 is provided at the noninverted input (-) of the input stage A.sub.1, the input signal V.sub.in is AC-wise attenuated in its high frequency region. Accordingly, a low-pass filter circuit can be constructed by providing a proper buffer circuit (or a high impedance element) at a junction point of the capacitor C.sub.1 and the collectors of the transistors Q.sub.8 and Q.sub.6 so that the inverted input (-) signal is outputted through the buffer circuit.

In the present embodiment, the output of the low-pass filter circuit is inputted to a buffer circuit A.sub.3. An output of the buffer circuit A.sub.3 and the input signal V.sub.in are subtracted from each other by a subtracter circuit constructed by an operational amplifier circuit A.sub.2 and resistors R.sub.21a, R.sub.21b, R.sub.22a and R.sub.22b, thereby forming a high-pass filter output signal V.sub.out.

Provided that the ON-resistance value of each of the transistors Q.sub.3 and Q.sub.4 is r.sub.d1 and the resistance value of each of the emitter resistances of the transistors Q.sub.6 and Q.sub.7 is r.sub.e1, there are satisfied a relation of r.sub.d1 =(kT/q).div.I.sub.0 and a relation of r.sub.e1 =(kT/q).div.I.sub.1 /2. Here, kT/q is about 26 mV. Since the current I.sub.1 can be changed by a resistor-trimming operation as mentioned above, it is possible to correspondingly change the resistance r.sub.e1.

In the circuit shown in FIG. 3A, when the input signal V.sub.in is inputted, a current of (V.sub.in -V.sub.x)/R.sub.1 is outputted from the collector of the transistor Q.sub.1 and a phase-inverted current thereof is outputted from the collector of the transistor Q.sub.2. V.sub.x is a voltage on a junction point of the capacitor C.sub.1 and the base of the transistor Q.sub.2. The diode-connected transistors Q.sub.3 and Q.sub.4 serve as loads so that signal voltages outputted from the collectors of the transistors Q.sub.3 and Q.sub.4 result in r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1. These signal input voltages supplied to the bases of the differentially operative transistors Q.sub.6 and Q.sub.7 which form the controllable voltage-current conversion circuit VVIC.

Since the emitter resistance of each of the differentially operative transistors Q.sub.6 and Q.sub.7 is r.sub.e1, as mentioned above, the following current is obtained from the collectors of the transistors Q.sub.6 and Q.sub.7. Namely, in the controllable voltage-current conversion circuit VVIC, a signal current is formed in such a manner that the above-mentioned signal voltages r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1 are applied to the emitter resistances r.sub.e1 of the differentially operative transistors Q.sub.6 and Q.sub.7. Accordingly, the signal current formed is [r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1 ].div.r.sub.e1. This current is supplied to the capacitor C.sub.1. The capacitor C.sub.1 serves to attenuate a high frequency component of the supplied current signal. Therefore, there is obtained the following signal voltage V.sub.x :

V.sub.x =[(V.sub.in -V.sub.x)/R.sub.1 ].times.(r.sub.d1 j.omega.C.sub.1)(1)

On the other hand, in the subtracter circuit A.sub.2, a relation of

V.sub.in -V.sub.x /2+V.sub.out -V.sub.x /2=0 (2) is satisfied (on the assumption that R.sub.21a =R.sub.21b and R.sub.22a =R.sub.22b)

The equations (1) and (2) provide the following input/output transfer function: ##EQU1##

The equation (3) shows a high-pass filter and a cut-off frequency f.sub.H of the filter is represented by ##EQU2##

By setting r.sub.e1 and r.sub.d1 so as to satisfy a relation of (r.sub.e1 /r.sub.d1)>1 for the time constant defined by C.sub.1 .multidot.R.sub.1 (r.sub.e1 /r.sub.d1), the capacitance value of the capacitor C.sub.1 is equivalently made large. Thereby, it is possible to obtain a filter circuit having a relatively large time constant or a relatively low cut-off frequency even if a capacitor incorporated in a semiconductor integrated circuit has a relatively small capacitance. Also, the resistance value of the resistor r.sub.e1 can be corrected by adjusting the current I.sub.1 through the resistor-trimming operation in the current adjusting circuit CA. Thereby, it is possible to compensate for variations of cut-off frequencies f.sub.H from one semiconductor integrated circuit chip to another which may be caused by the deviations of electric characteristics of circuit elements in a semiconductor integrated circuit.

FIG. 4A shows a circuit diagram of a monolithic semiconductor integrated circuit device including another filter circuit, and FIG. 4B shows a block diagram of the device shown in FIG. 4A.

An input signal V.sub.in and a feedback signal V.sub.x are supplied to a differential input stage A.sub.1 (or a first differentially operative circuit) similar to that in the device shown in FIG. 3A.

Output voltages of the differential input stage A.sub.1 formed by diode-connected transistors Q.sub.3 and Q.sub.4 in which collector currents of the differentially operative transistors Q.sub.1 and Q.sub.2 flow are applied to the bases of differentially operative NPN transistors Q.sub.6 and Q.sub.7 which form a controllable voltage-current conversion circuit VVIC (or a second differentially operative circuit) and the bases of differentially operative NPN transistors Q.sub.10 and Q.sub.11 which form a voltage-current conversion circuit VIC (or a third differentially operative circuit).

Like the embodiment shown in FIGS. 3A and 3B, the controllable voltage-current conversion circuit VVIC (or the second differentially operative circuit) includes the differentially operative transistors Q.sub.6 and Q.sub.7, PNP transistors Q.sub.8 and Q.sub.9 which are provided in a current mirror circuit connection on the collector sides of the differentially operative transistors Q.sub.6 and Q.sub.7 and form active load circuits, and a transistor Q.sub.22 and an emitter resistor R.sub.10 thereof which are provided on the common emitter side of the differentially operative transistors Q.sub.6 and Q.sub.7 and form an adjustable current source circuit I.sub.12. The transistor Q.sub.22 and a current adjusting circuit CA are in a current mirror circuit connection, like the embodiment shown in FIG. 3A. A signal current (or a first current signal) formed by the differentially operative transistors Q.sub.6 and Q.sub.7 of the controllable voltage-current conversion circuit VVIC serves as a charging/discharging current for a capacitor C.sub.1 and the current signal is fed back to the base of the transistor Q.sub.2 which is a feedback terminal of the differential input stage A.sub.1.

The voltage-current conversion circuit VIC (or the third differentially operative circuit) receiving the output signal of the differential input stage A.sub.1 to convert it into a second current signal includes the differentially operative transistors Q.sub.10 and Q.sub.11, PNP transistors Q.sub.12 and Q.sub.13 which are provided in a current mirror circuit connection on the collector sides of the differentially operative transistors Q.sub.10 and Q.sub.11 and form active load circuits, and a constant current source I.sub.0 which is provided to the common emitter of the differentially operative transistors Q.sub.10 and Q.sub.11.

An output signal of the controllable voltage-current conversion circuit VVIC and an output signal of the voltage-current conversion circuit VIC are supplied to a non-inverted input (+) and an inverted input (-) of an operational amplifier circuit A.sub.2 which forms an adder circuit. The operational amplifier circuit A.sub.2 includes a differentially operative circuit and an output circuit. The differentially operative circuit is composed of differentially operative NPN transistors Q.sub.14 and Q.sub.15 which receive the output signals of the voltage-current conversion circuits VVIC and VIC, PNP transistors Q.sub.16 and Q.sub.17 which are provided in a current mirror circuit connection on the collector sides of the differentially operative transistors Q.sub.14 and Q.sub.15 and serve as active loads, a capacitor C.sub.2 for phase compensation which is provided between the base and collector of the transistor Q.sub.17 on the output side, and a constant current source I.sub.0 which is provided to the common emitter of the differentially operative transistors Q.sub.14 and Q.sub.15. The output circuit of the operational amplifier circuit A.sub.2 is composed of an emitter-follower output transistor Q.sub.18 and a constant current source I.sub.0 provided to the emitter of the transistor Q.sub.18.

The base of the transistor Q.sub.14 which is the non-inverted input (+) of the operational amplifier circuit A.sub.2 is connected with the commonly connected collectors of the transistors Q.sub.6 and Q.sub.8 which are an output terminal of the controllable voltage-current conversion circuit VVIC. The base of the transistor Q.sub.15 which is the inverted input (-) of the operational amplifier circuit A.sub.2 is connected with the commonly connected collectors of the transistors Q.sub.10 and Q.sub.13 which are an output terminal of the voltage-current conversion circuit VIC.

In order to allow the operational amplifier circuit A.sub.2 to operate as an adder circuit, a feedback resistor R.sub.2 is provided between an output terminal and the inverted input (-) of the operational amplifier circuit A.sub.2. Namely, the resistor R.sub.2 is inserted between the emitter of the output transistor Q.sub.18 and the base of the differential transistor Q.sub.15.

Explanation will now be made of the operation of the filter circuit of the present embodiment.

The differential input stage A.sub.1 operates such that an input signal V.sub.in supplied to the base of the transistor Q.sub.1 which is a non-inverted input (+) or first input terminal of the differential input stage A.sub.1 and a DC potential of the base of the transistor Q.sub.2 which is an inverted input (-) or second input terminal of the differential input stage A.sub.1 become equal to each other. Since the capacitor C.sub.1 is provided at the inverted input (-) of the input stage A.sub.1, the input signal V.sub.in is AC-wise attenuated in its high frequency region. Accordingly, like the embodiment shown in FIG. 3A, a low-pass filter output is obtained from the inverted input (-) or the base of the transistor Q.sub.2 with which the capacitor C.sub.1 is connected.

When the input signal V.sub.in is inputted, a current of (V.sub.in -V.sub.x)/R.sub.1 is outputted from the collector of the transistor Q.sub.1 and a phase-inverted current thereof is outputted from the collector of the transistor Q.sub.2 . The diode-connected transistors Q.sub.3 and Q.sub.4 serve as loads so that signal voltages outputted from the collectors of the transistors Q.sub.3 and Q.sub.4 result in r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1, provided that the ON-resistance of each of the transistors Q.sub.3 and Q.sub.4 both in a diode connection is r.sub.d1. These signal voltages (or first and second output voltages) serve for input voltages of the differentially operative transistors which form the controllable voltage-current conversion circuit VVIC and the voltage-current conversion circuit VIC.

Provided that the resistance value of the emitter resistance of each of the differentially operative transistors Q.sub.6 and Q.sub.7 is r.sub.e1, the following current is obtained from the collectors of the transistors Q.sub.6 and Q.sub.7.

In the controllable voltage-current conversion circuit VVIC, since a signal current is formed in such a manner that the above-mentioned signal voltages r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1 are applied to the emitter resistances r.sub.e1 of the differentially operative transistors Q.sub.6 and Q.sub.7, the signal current formed is [r.sub.d1 .multidot.(V.sub.in -V.sub.x)R.sub.1 ].div.r.sub.e1. This current is supplied to the capacitor C.sub.1. Since the capacitor C.sub.1 serves to attenuate a high frequency component of the supplied current signal, the signal V.sub.x has a low-pass filter output characteristic. Thus, the signal fed back to the differential input stage A.sub.1 has a low-pass filter characteristic. Accordingly, an output signal of the differential input stage A.sub.1 has a high-pass filter characteristic in accordance with the decrease of feedback amount of the high frequency component.

In the present embodiment, the output signal of the differential input stage A.sub.1 is converted into a current signal of [r.sub.d1 .multidot.(V.sub.in -V.sub.x)/R.sub.1 ].div.r.sub.e2 by the differentially operative transistors Q.sub.10 and Q.sub.11 of the voltage-current conversion circuit VIC and the current signal flows through the feedback resistor R.sub.2 of the adder circuit A.sub.2. Here, r.sub.e2 is the resistance value of the emitter resistance of each of the transistors Q.sub.10 and Q.sub.11. From the above explanation of the operation, there are satisfied the following equations (4) and (5):

V.sub.x =(V.sub.in - V.sub.x)/R.sub.1 ].times.r.sub.d1 /(r.sub.e1 .times.j.omega.C.sub.1) (4) V.sub.out =(V.sub.in - V.sub.x)/R.sub.1 ].times.(r.sub.d1 /r.sub.e2).times.R.sub.2 +V.sub.x. (5) The equations (4) and (5) provide the following input/output transfer function: ##EQU3##

From the equation (6), it is apparent that there serves for not only a low-pass filter but also a high-pass filter, depending on the resistance values of the resistors R.sub.1 and R.sub.2.

In the case of R.sub.1 r.sub.e1 <R.sub.2 r.sub.e2, there is provided a high-pass filter the lower cut-off frequency f.sub.L of which is C.sub.1 .multidot.R.sub.2 (r.sub.e1 /r.sub.e2) and the higher cut-off frequency f.sub.H of which is C.sub.1 .multidot.R.sub.1 (r.sub.e1 /r.sub.e2), as shown by solid line in FIG. 4C. On the contrary, in the case of R.sub.1 r.sub.e1 >R.sub.2 r.sub.e2, there is provided a low-pass filter the lower cut-off frequency f.sub.L of which is C.sub.1 .multidot.R.sub.1 (r.sub.e1 /r.sub.e2) and the higher cut-off frequency f.sub.H of which is C.sub.1 .multidot.R.sub.2 (r.sub.e1 /r.sub.e2), as shown by dotted line in FIG. 4C. As a matter of design, r.sub.e1 and r.sub.e2 are made approximately equal to each other and hence the filter characteristic is determined in accordance with a relation in magnitude between R.sub.1 and R.sub.2.

Compensation for a variation of a time constant defined by CR(r.sub.e1 /r.sub.e2) can be made through such a resistor-trimming operation as explained in conjunction with FIG. 2A or 2B since the resistance r.sub.e1 is changed by a constant current source I.sub.12. Also, by setting r.sub.e1 and r.sub.e2 so as to satisfy a relation of (r.sub.e1 /r.sub.e2)>1, the time constant can be regarded as being equivalent to one in which the capacitance value of the capacitor C.sub.1 is made large. Thereby, it is possible to obtain a relatively large time constant even if a capacitor incorporated in a semiconductor integrated circuit has a relatively small capacitance.

FIG. 5A shows a circuit diagram of a monolithic semiconductor integrated circuit device including a notch filter circuit, and FIG. 5B shows a block diagram of the device shown in FIG. 5A.

A differential input stage A.sub.1, a first controllable voltage-current conversion circuit VVIC.sub.1 and an operational amplifier A.sub.2 shown in FIG. 5A have constructions similar to those of the circuits shown in FIG. 4A. A second controllable voltage-current conversion circuit VVIC.sub.2 may have a construction similar to that of the first controllable voltage-current conversion circuit VVIC.sub.1.

In the embodiment shown in FIGS. 5A and 5B, output signals of the differential input stage A.sub.1 are supplied to the first and second controllable voltage-current conversion circuits VVIC.sub.1 and VVIC.sub.2 in order to obtain a notch filter characteristic. Second amplifying elements or transistors Q.sub.23 and Q.sub.24 in the first and second controllable voltage-current conversion circuits VVIC.sub.1 and VVIC.sub.2 are in a current mirror circuit connection together with a current adjusting circuit CA, like the embodiment shown in FIG. 3A. Accordingly, the transistors Q.sub.23 and Q.sub.24 form adjustable current sources I.sub.3 and I.sub.3 '. A load resistor R.sub.2 is provided between an output terminal of the second controllable voltage-current conversion circuit VVIC.sub.2 and a predetermined bias terminal V.sub.B. A capacitor C.sub.2 is provided between the outputs of the first and second controllable voltage-current conversion circuits VVIC.sub.1 and VVIC.sub.2. An output signal V.sub.y of the second controllable voltage-current conversion circuit VVIC.sub.2 and an input signal V.sub.in are summed by an adder circuit which is constructed by the operational amplifier circuit A.sub.2. Namely, the input signal V.sub.in is supplied to a non-inverted input terminal (+) of the operational amplifier circuit A.sub.2 while the signal V.sub.y is supplied to an inverted input terminal (-) thereof through a resistor R.sub.3a, and a resistor R.sub.3b is provided between the inverted input (-) and an output of the operational amplifier circuit A.sub.2.

Provided that the ON-resistance of each of the transistors Q.sub.3 and Q.sub.4 of the differential input stage A.sub.1, the emitter resistance of each of differentially operative transistors Q.sub.6 and Q.sub.7 of the first controllable voltage-current conversion circuit VVIC.sub.1 is r.sub.e1 and the emitter resistance of each of differentially operative transistors Q.sub.6 ' and Q.sub.7 ' of the second controllable voltage-current conversion circuit VVIC.sub.2 is r.sub.e3, the following equations (7) and (9) are satisfied similarly to the above explained:

[(V.sub.in -V.sub.x)/R.sub.1 ].times.2r.sub.d1 /r.sub.e1 -j.omega.C.sub.1 C.sub.x +j.omega.C.sub.2 (V.sub.y -V.sub.x)=0 (7) [(V.sub.in -V.sub.x)/R.sub.1 ].times.2r.sub.d1 /r.sub.e3 +(V.sub.y /R.sub.2)+j.omega.C.sub.2 (V.sub.y -V.sub.x)=0 (8) V.sub.out =V.sub.in +V.sub.y (under assumption of R.sub.3a =R.sub.3b).(9)

The notch frequency as represented by the corresponding angular frequency .omega..sub.0 and the gain G.sub.v.omega..sbsb.o of the notch filter circuit at the notch angular frequencies will be determined from equations (7) to (9) as follows. ##EQU4##

From the above two equations, it can be seen that the notch frequency can be controlled by the control current I.sub.3, i.e., by the resistance r.sub.e1 in the first controllable voltage-current conversion circuit VVIC.sub.1, while the gain at the notch frequency can be adjusted by the control current I.sub.3 ', i.e., by the resistance r.sub.e3 in the second controllable voltage-current conversion circuit VVIC.sub.2 with the control current I.sub.3 being first fixed, though the gain could be varied by the control current I.sub.3 (the resistance r.sub.e1).

FIG. 6A shows a circuit diagram of a monolithic semiconductor integrated circuit device including a high-pass filter circuit, and FIG. 6B shows a block diagram of the device shown in FIG. 6A.

A differential input stage A.sub.1, a controllable voltage-current conversion circuit VVIC, an operational amplifier circuit A.sub.3 and an adder circuit A.sub.2 shown in FIG. 6A may have constructions similar to those of the circuits shown in FIG. 3A. A second amplifying element or transistor Q.sub.23 in the controllable voltage-current conversion circuit VVIC is in a current mirror circuit connection together with a current adjusting circuit CA, like the embodiment shown in FIG. 3A. Accordingly, the transistor Q.sub.23 forms an adjustable current source I.sub.2.

However, in the embodiment shown in FIG. 6A, a feedback is applied to the operational amplifier circuit A.sub.3 in order to reduce the DC offset and the signal distortion of an output V.sub.out. Namely, a signal V.sub.x in the controllable voltage-current conversion circuit VVIC having a low-pass filter characteristic is divided by resistors R.sub.5a and R.sub.5b through the operational amplifier A.sub.3 in a voltage-follower configuration and is thereafter supplied to a non-inverted input (+) of the operational amplifier circuit A.sub.2. An inverted input (-) of the operational amplifier circuit A.sub.2 is applied with an input signal V.sub.in through a resistor R.sub.5a and a resistor R.sub.5b is provided between the inverted input (-) and an output of the operational amplifier circuit A.sub.2.

Briefly explaining the operation of the filter circuit of the embodiment shown in FIG. 6A, a high-pass filter characteristic is obtained subtracting the signal V.sub.x having the low-pass filter characteristic from the input signal V.sub.in. This can be quantitatively explained by equations (10) to (12) which will be shown just in below. Namely, since a relation of V.sub.x =[(V.sub.in -V.sub.x)/R.sub.1 ].times.(r.sub.d1 /r.sub.e1).times.1/j.omega.C.sub.1 is satisfied similarly to the above explained, there are satisfied the following equations (10) to (12): ##EQU5##

V.sub.y =V.sub.x /2 (11) V.sub.in -V.sub.y +V.sub.out -V.sub.y =0. (12)

From the equations (10) to (12), a transfer function as shown by the equation (3) is obtained similarly to the case of the circuit shown in FIG. 3A (on the assumption that R.sub.5a =R.sub.5b and R.sub.6a =R.sub.6b).

In the embodiment shown in FIGS. 6A and 6B, since the feedback is applied also to the amplifier circuit A.sub.3 to obtain the output signal V.sub.out, it is possible to greatly reduce the DC offset voltage and the signal distortion. Also, a gain can be adjusted by setting the ratio of the resistance value of the resistor R.sub.5a to that of the resistor R.sub.5b and the ratio of the resistance value of the resistor T.sub.6a to that of the resistor R.sub.6b to desired values.

Functional effects obtained by the above-mentioned embodiments are as follows:

(1) Since the electric characteristics of circuit elements formed in a semiconductor integrated circuit have approximately uniform deviations in only one direction, it is possible to match the time constants of filter circuits with each other through a resistor-trimming operation at one location.

(2) By transmitting an output signal of a differential input stage to a controllable voltage-current conversion circuit and providing a capacitor charged/discharged by an output signal of the controllable voltage-current conversion circuit so that the output signal is fed back to a feedback terminal of the differential input stage, a signal having a low-pass filter characteristic and a signal having a high-pass filter characteristic can be obtained from the feedback terminal and an output terminal, respectively. A variety of filter circuits can be constructed by a signal processing of those signals including summation, subtraction and/or so on. A frequency response can be corrected by flowing a control current in the controllable voltage-current conversion circuit.

(3) The capacitance value of the capacitor provided to the feedback terminal of the differential input stage can be made equivalently large in accordance with the ratio of a load resistor of the differential input stage to the emitter resistance of transistors forming the voltage-current conversion circuit. Thereby, even in a semiconductor integrated circuit in which only a capacitor having a relatively small capacitance can be formed, a filter circuit having a relatively low cut-off frequency can be obtained.

In the foregoing, the invention made by the present inventors has been specifically explained on the basis of the embodiments thereof. However, of course, the present invention is not limited to the disclosed embodiments but various changes or modifications can be made without departing from the subject matter of the present invention. For example, a structure for changing a control current by a resistor-trimming operation can employ a variety of configurations inclusive of the trimming of patterns of resistor elements themselves instead of the disclosed selective cutting-off of the connection lines by which resistor elements are connected. Also, differentially operative amplifying elements forming a filter circuit may include MOSFETs (insulated-gate field-effect transistors), junction type FETs instead of bipolar transistors disclosed. Further, a specific construction for an adder or subtracter circuit for receiving the signal having the low-pass filter characteristic and the signal having the high-pass filter characteristic can employ a variety of configurations.

The present invention is widely applicable to a semiconductor integrated circuit device having a filter circuit incorporated therein.

Claims

1. A monolithic semiconductor integrated circuit device, comprising:

a current adjusting circuit including at least one first amplifying element and first and second load resistor means for said amplifying element, said first amplifying element having a control electrode, a current receiving electrode connected with said first load resistor means and a current delivering electrode connection with said second load resistor means, at least one of said first and second load resistor means being means for trimming resistance to adjustably determine the resistance of said at least one of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode; and

an audio signal processing circuit including a differentially operative circuit section and a second amplifying element, said second amplifying element having a control electrode, a current receiving electrode and a current delivering electrode, one of said current receiving and delivering electrodes being connected with said differentially operative circuit section, said differentially operative circuit section having a frequency response depending on an electric current flowing in a current path between said current receiving and delivering electrodes of said second amplifying element, said first and second amplifying elements being in a current mirror circuit connection with their control electrodes being connected with each other so that said electric current flowing in the current path between said current receiving and delivering electrodes of said second amplifying element is controlled by said adjustably determined resistance of said at least one load resistor means to adjust the frequency response of said audio signal processing circuit, thereby compensating for variations of electric characteristics of the audio signal processing circuit.

2. A device according to claim 1, wherein the other of said first and second load resistor means is means for trimming resistance to adjustably determine the resistance of said other of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode.

3. A device according to claim 2, in which each of said first and second load resistor means includes a plurality of resistor elements arranged with connectors therebetween that may be cut during the trimming.

4. A device according to claim 1, in which said first and second amplifying elements are first and second bipolar transistors, and a third bipolar transistor is connected with said first bipolar transistor such that the base and emitter of said third bipolar transistor are connected with the collector and base of said first bipolar transistor, respectively.

5. A device according to claim 1, in which each of said first and second amplifying elements is a field-effect transistor.

6. A filter according to claim 2, wherein the other of said first and second load resistor means is means for trimming resistance to adjustably determine the resistance of said other of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode.

7. A filter according to claim 6, in which each of said first and second load resistor means includes a plurality of resistor elements arranged with connectors therebetween that may be cut curing the trimming.

8. A device according to claim 1, wherein the audio signal processing circuit has a time constant defined by a capacitance times a resistance times a value proportional to the adjustably determined resistance of said at least one load resistor means that directly determines the frequency response.

9. A device according to claim 8, wherein said means for trimming increases the time constant.

10. A filter in an integrated circuit form, comprising:

a current adjusting circuit including at least one first amplifying element and first and second load resistor means for said amplifying element, said first amplifying element having a control electrode, a current receiving electrode connected with said first load resistor means and a current delivering electrode connected with said second load resistor means, at least one of said first and second load resistor means being means for resistance to adjustably determine the resistance of said at least one of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode;

a first differentially operative circuit serving as an input stage and having a first input terminal for receiving an input signal to the filter and a second input terminal;

a capacitor connected with said second input terminal;

a second differentially operative circuit serving to convert an output voltage of said first differentially operative circuit to a corresponding current signal, said capacitor being also connected with said second differentially operative circuit to receive said current signal for a charge/discharge operation therewith, said second differentially operative circuit including a pair of differential amplifier elements and a second amplifying element, said second amplifying element having a control electrode, a current receiving electrode and a current delivering electrode, one of said current receiving and delivering electrodes being connected with said pair of differential amplifier elements, said second differentially operative circuit having a frequency response depending on an electric current receiving and delivering electrodes of said second amplifying element, said first and second amplifying elements being in a current mirror circuit connection with their control electrodes being connected with each other so that said electric current flowing in the current path between said current receiving and delivering electrodes of said second amplifying element is controlled by said adjustably determined resistance of said at least one load resistor means; and

an adder circuit for summing an output signal representative of a terminal voltage of said capacitor and said input signal.

11. A filter according to claim 10, wherein the other of said first and second load resistor means is means for trimming resistance to adjustably determine the resistance of said other of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode.

12. A filter according to claim 11, in which each of said first and second load resistor means includes a plurality of resistor elements arranged with connectors therebetween that may be cut curing the trimming.

13. A filter according to claim 10, wherein said second differentially operative circuit has a time constant defined by a capacitances times a resistance times a value proportional to the adjustably determined resistance times a value proportional to the adjustably determined resistance of said at least one load resistor means that directly determine the frequency response.

14. A device according to claim 13, wherein said means for trimming increases the time constant.

15. A filter according to claim 10, wherein said first differentially operative circuit, said capacitor and said second differentially operative circuit constitute one of a low-pass filter, high-pass filter and notch filter, and further comprising another of the low-pass filter, high-pass filter and notch filter including another first differentially operative circuit, another capacitor and another second differentially operative circuit, substantially identical to the first mentioned first differentially operative circuit, capacitor and second differentially operative circuit all connected so that the frequency response of at least two separate filters is commonly adjusted by a single means for trimming.

16. A filter according to claim 15, wherein the other of said first and second load resistor means is means for trimming resistance to adjustably determine the resistance of said other of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode.

17. A filter according to claim 16, wherein each of said first and second load resistor means includes a plurality of resistor elements arranged with connectors therebetween that may be cut curing the trimming.

18. A filter according to claim 15, wherein said second differentially operative circuit has a time constant defined by a capacitance times a resistance times a value proportional to the adjustably determined resistance of said at least one load resistor means that directly determine the frequency response.

19. A device according to claim 18, wherein said means for trimming increases the time constant.

20. A filter according to claim 15, wherein the other of said first and second load resistor means is means for trimming resistance to adjustably determine the resistance of said other of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode.

21. A filter according to claim 20, wherein each of said first and second load resistor means includes a plurality of resistor elements arranged with connectors therebetween that may be cut curing the trimming.

22. A filter in an integrated circuit form comprising:

a current adjusting circuit including at least one first amplifying element and first and second load resistor means for said amplifying element, said first amplifying element having a control electrode, a current receiving electrode connected with said first load resistor means and a current delivering electrode connected with said second load resistor means, at least one of said first and second load resistor means being means for trimming resistance to adjustably determine the resistance of said at least one of said first and second load resistor means for controlling the current flowing between said current receiving electrode and said current delivering electrode;

a first differentially operative circuit serving as an input stage and having a first input terminal for receiving an input signal to the filter and a second input terminal;

a capacitor connected with said second input terminal;

a second differentially operative circuit serving to convert an output voltage of said first differentially operative circuit to a corresponding current signal, said capacitor being also connected with said second differentially operative circuit to receive said current signal for a charge/discharge operation therewith, said second differentially operative circuit including a pair of differential amplifier elements and a second amplifying element, said second amplifying element having a control electrode, a current receiving electrode and a current delivering electrode, one of said current receiving and delivering electrodes being connected with said pair of differential amplifier elements, said second differentially operative circuit having a frequency response depending on an electric current flowing in a current path between said current receiving and delivering electrodes of said second amplifying element, said first and second amplifying elements being in a current mirror circuit connection with their control electrodes being connected with each other so that said electric current flowing in the current path between said current receiving and delivering electrodes of said second amplifying element is controlled by said adjustably determined resistance of said at least one load resistor means; and

a third differentially operative circuit serving to convert a second output voltage of said first differentially operative circuit to a corresponding second current signal; and

an adder circuit for summing an output signal of said second differentially operative circuit representative of a terminal voltage of said capacitor and an output signal of said third differentially operative circuit representative of said second current signal.

23. A device according to claim 22, wherein said second differentially operative circuit has a time constant defined by a capacitances times a resistance times a value proportional to the adjustably determined resistance of said at least one load resistor means that directly determine the frequency response.

24. A filter according to claim 23, wherein said means for trimming increases the time constant.

25. A filter according to claim 22, wherein said first differentially operative circuit, said capacitor and said second differentially operative circuit constitute one of a low-pass filter, high-pass filter and notch filter, and further comprising another of the low-pass filter, high-pass filter and notch filter including another first differentially operative circuit, another capacitor and another second differentially operative circuit, substantially identical to the first mentioned first differentially operative circuit, capacitor and second differentially operative circuit all connected so that the frequency response of at least two separate filters is commonly adjusted by a single means for trimming.

26. A filter according to claim 25, wherein said second differentially operative circuit has a time constant defined by a capacitance times a resistance times a value proportional to the adjustably determined resistance of said at least one load resistor means that directly determine the frequency response.

27. A device according to claim 26, wherein said means for trimming increases the time constant.