Patent Application
20200395652
The present disclosure relates to improvements in or relating to antenna arrangements, and is more particularly concerned with monolithically integrated antennas.
Thin film wireless identification tags are known which operate at frequencies below 1 GHz, for example, in radio frequency identity (RFID) tags, near-field communication (NFC), capacitive identification (CAPID). Such wireless ID tags typically comprise two sub-components, namely, the chip or integrated circuit and the antenna. The chip is responsible for the electronic functionality, such as: matching the antenna, rectifying the AC input wave to a DC supply, storing the tag memory, reading incoming signals from the reader, transmitting outgoing signals to the reader. The antenna is responsible for converting these signals into electromagnetic waves and sending them to the reader.
The chips and antennas are fabricated separately using different technologies, and, are assembled together in a tag assembly process. A typical delivery format for chips is a diced wafer on a temporary carrier as the size of the chip is small, usually below 1 mm2. A typical delivery format for antennas is antenna components glued to a temporary carrier (typically a paper-based roll), and, the size of the antenna is large, usually above several cm2. A pick-and-place assembly step is used to connect the chip and the antenna.
Pick-and-place assembly is a relatively complex process, and has several limitations:
Limited throughput: The throughput of the assembly process is reciprocal to the total time required to assemble one tag. The time, in turn, is defined by the sum of the sub-step times and may be up to several seconds. This is a limitation for manufacturers. Moreover, any delays or failures might cause process disruption and limit the throughput even further.
Limited yield: The yield depends on the throughput and implementation of the sub-steps. As a general rule of thumb—higher throughputs (faster process) result in lower process accuracy and consequently in lower yield. Non-working devices are discarded from manufacturing, or simply lost. Limited yield drives the tag cost up and this is a problem for manufacturers.
Testing and quality control: Any faulty tags must be removed from the final delivery. This requires intermediate testing and quality control. At least two different quality control steps need to be implemented for: (i) testing of individual chips and antennas before the assembly; and for (ii) testing of the complete tag after the assembly.
Finally, the assembly process requires advanced material and equipment, which entails additional manufacturing costs.
A semiconductor device in which an antenna is integrally formed with an integrated circuit as described in WO-A-2005/088704. The antenna is integrally formed with a transistor component layer on a substrate, electronic components in the transistor component layer being configured to be connected to the antenna element. Such a semiconductor device has improved mechanical strength but requires the provision of an insulating layer containing fine particles of a soft magnetic material over the antenna to reduce suppress the generation of eddy currents in conducting wires forming the antenna in order to increase the mutual inductance of the antenna as well as an insulating interlayer between the insulating layer and the transistor component layer.
However, the addition of the insulating layer with the fine particles of soft magnetic material and the insulating interlayer requires at least two additional steps in the manufacturing process making it more complex than is necessary with longer manufacturing times. Moreover, the fine particles of soft magnetic material are non-standard materials for thin-film transistor manufacturing.
It is therefore an object of the present disclosure to provide a monolithically integrated antenna device where no assembly of components is required.
It is another object of the present disclosure to provide a wireless tag incorporating a monolithically integrated antenna device.
It is a further object of the present disclosure to provide an antenna device comprising a chip and an antenna structure where the chip substrate size is the same or larger than that of the antenna structure.
It is a yet further object of the present disclosure to provide a monolithically integrated antenna device in which no additional non-standard material layers are required to provide shielding from electromagnetic interference.
In accordance with the present disclosure, there is provided a monolithically integrated antenna device comprising: a substrate having a first surface and a second surface; a transistor component layer comprising at least one electronic component therein; and at least one antenna structure formed on one of: the substrate and the transistor component layer, the antenna structure being configured to operate in a frequency range of between 30 kHz and 2.4 GHz; wherein the substrate is configured to have a size which is the same or larger than the at least one antenna structure; characterized the at least one electronic component in the transistor component layer is configured to be shielded from electromagnetic interference.
Such a monolithically integrated antenna device has the advantage that all components can be formed on a single substrate. In addition, by configuring the at least one electronic component in the transistor component layer to be shielded from electromagnetic interference, electromagnetic radiation does not interfere with the transistor component layer of the device without having to include additional non-standard materials.
While modern ID tag technologies drive the electronics or chip size to smaller and smaller dimensions, by increasing the chip area significantly, it is possible to create a sub-1 GHz monolithic antenna directly ‘on-chip’.
This eliminates the need of the assembly process completely. In this context, monolithic integration means that both the chip and the antenna are manufactured on the same substrate, either in one or in subsequent processes.
In an embodiment, the transistor component layer may be formed side-by-side with the at least one antenna structure on the first surface of the substrate. Such an embodiment can be used for both capacitive and inductive antenna structures.
In an embodiment, the at least one antenna structure is formed in a stack with the transistor component layer and the substrate. Such an embodiment can be used for both capacitive and inductive antenna structures.
The antenna structures may be formed by one of: physical vapor deposition, electroplating and printing.
In an embodiment, the at least one antenna structure comprises a first antenna structure, and, the transistor component layer is formed on the first surface of the substrate with the first antenna structure formed over at least one interlayer formed on the transistor component layer.
In an embodiment, the device further comprises a shielding layer and the at least one interlayer comprises a first interlayer and a second interlayer separated by the shielding layer.
This has the advantage that the antenna or electrode can be shielded from electromagnetic interference.
In an embodiment, the first antenna structure is configured to extend over the at least one electronic component in the transistor component layer to provide shielding thereof.
In an embodiment, a second antenna structure may be formed on the second surface of the substrate.
In such an embodiment, each antenna structure may operate at a different frequency in a single device. For example, the antenna structures may operate at different frequencies within the range of 30 kHz to 2.4 GHz described above. They may preferably operate in the range of 30 kHz to 300 MHz.
In an embodiment, the at least one antenna structure comprises a first antenna structure formed on the first surface of the substrate and the transistor component layer is formed over the first antenna structure.
At least one interlayer may be provided between the first antenna structure and the transistor component layer.
The provision of such an interlayer has the advantage of providing both decoupling of components within the structure and planarization ready for the next deposition step.
In an embodiment, a metal layer may be configured to extend over the at least one electronic component in the transistor component layer to provide shielding thereof.
A shielding layer may also be provided in the at least one interlayer which separates it into first and second interlayers.
Such a shielding layer electrically decouples the components in the transistor component layer from the antenna structure.
In an embodiment, the transistor component layer may be formed on the first side of the substrate and the at least one antenna structure is formed on the second side of the substrate. At least one interlayer may be located between the at least one antenna structure and the second surface of the substrate. A shielding layer may also be located within the at least one interlayer.
In an embodiment, routing elements may extend through at least one further layer for connecting to the transistor component layer. Such routing elements may be configured to extend over the at least one electronic component in the transistor component layer to provide shielding thereof.
In an embodiment, the at least one antenna structure may comprise at least two stacked metal layers formed on the substrate. The antenna structure may be formed from three stacked metal layers. Here, the antenna structure is formed side-by-side with the transistor component layer.
A metal layer may be provided which is configured to extend over the at least one electronic component in the transistor component layer to provide shielding thereof.
In accordance with a further aspect of the present disclosure, there is provided an antenna device as described above configured as a dipole antenna device and having an operational frequency range up to 2.4 GHz.
In accordance with another aspect of the present disclosure, there is provided a wireless tag comprising a monolithically integrated antenna device as described above.
For a better understanding of the present disclosure, reference will now be made, by way of example, to the accompanying drawings in which:—
The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.
Abbreviations and acronyms used herein include:
“low-k dielectrics” refers to dielectrics having k values in the range of between 2 and 5;
“VDD” refers to the supply voltage;
“IC” refers to an integrated circuit or chip;
“TFT” refers to a thin film transistor, referred to as “TFT component”, “TFT component layer” or simply “TFT” in the following disclosure;
“SAL TFT” refers to a self-aligned TFT;
“TFIC” refers to a thin film integrated circuit, referred to as “TFIC component” or simply “TFIC”;
“RFID” refers to radio frequency identification;
“CAPID” refers to capacitive identification;
“MIM” refers to metal-insulator-metal used in capacitors;
“PVD” refers to physical vapor deposition, and describes a multitude of vacuum deposition processes, such as, sputtering, e-beam, laser ablation and evaporation, where the material transitions from a condensed phase to a vapor phase and then back to a thin film condensed phase; metals and metal oxides can be used for the deposition and “DC-PVD” refers to a PVD process where DC power is applied to a target;
“PECVD” refers to plasma-enhanced chemical vapor deposition (CVD) in which thin films are deposited onto a substrate in a solid state starting from a gaseous state (vapor);
“TFIC substrate” refers to a substrate for the electronics or chip in the TFT component; also described as “flexible substrate” or simply “substrate”—the substrate having a size which is the same or larger than the antenna component formed thereon and on which all processing steps are performed to form the integrated antenna structure of the present disclosure;
“sub-1 GHz” refers to the operating frequency range for the monolithic integrated antenna device in accordance with the present disclosure, and, is between 30 kHz and 1 GHz, preferably between 30 kHz and 300 MHz;
“monolithically integrated antenna structure”, “monolithically integrated antenna device” or “monolithically integrated device” refer to the antenna structure in accordance with the present disclosure in which all processing steps are performed on the same substrate; and
“Q-factor” refers to a measure of the bandwidth of an antenna relative to the centre frequency of the bandwidth; antennas with high Q are narrowband and those with low Q are wideband—the antenna structure in accordance with the present disclosure is narrowband.
In accordance with the present disclosure, a new wireless ID tag is described in which the chip substrate is the same size or larger than that of the antenna. This is contrary to what is currently done in the field as the chips tend to have smaller and smaller dimensions. The chip area of the device according to the present disclosure may be 10 mm2 or larger which allows for the creation of a sub-1 GHz monolithic antenna directly ‘on-chip’ as will be described below.
In contrast, in
A new chip construction for a monolithically integrated device according to one aspect of the present disclosure is described with reference to
The additional conductive structures may be integrated in various embodiments relative to the chip electronics (i.e. thin-film transistor (TFT component or TFT) layer):
Side-by-side with the chip electronics in the TFIC substrate (as shown in
Above the chip electronics in the TFIC substrate (as shown in
Below the chip electronics in the TFIC substrate (as shown in
Both below and above the chip electronics in the TFIC substrate (as shown in
Below the chip substrate, that is, on an opposite side of the TFIC substrate to the TFT component layer (as shown in
Below the chip substrate and above the chip electronics in the TFIC substrate (as shown in
In each embodiment, the additional conductive structures may form capacitive or inductive antennas.
For inductive antennas, the integrated antenna structures are conductive structures configured such that a change in current through one wire of a conductive structure (e.g. a reader antenna structure) induces a voltage across the ends of a wire of another conductive structure (e.g. a tag antenna structure) through electromagnetic induction and vice versa. The amount of inductive coupling between two conductors is measured by their mutual inductance. The coupling between two wires can be increased by winding them into coils and placing them close together on a common axis, so the magnetic field of one coil passes through the other coil. The antenna structure (or coil) forms an electrical connection with the chip electronics as shown in
In
For capacitive antennas, the integrated antenna structures are conductive structures configured such that a change in the electric field between the structures induces displacement currents within the structures. The antenna structure (plates) forms an electrical connection with the chip electronics (
In
Each of the inductive antenna structure 200 and the capacitive antenna structure 250 shown in respective ones of
Each embodiment in accordance with the present disclosure is described in more detail below.
In the side-by-side configuration shown in
Capacitive antennas may be formed by physical vapor deposition (PVD) or by printing. Inductive antennas may also be formed by printing as well as plating. For both capacitive and inductive antennas, low power TFICs are proposed and for inductive antennas, high conductivity layers may be used, as described below.
As described above, there are issues with antenna metal conductivity. In effect, for an inductive antenna, the conductivity must be high resulting in a large Q-factor in the range of 5 to 30.
For typical PVD metals, such as, molybdenum, molybdenum-chromium, copper, gold and aluminum, layer thicknesses in excess of the μm range are needed. Such thick metals are uncommon in TFIC manufacturing. Much thinner layers are used in a TFT stack 50 to 250 nm. A TFT stack customization is therefore required to accommodate for conductivity requirements of monolithic inductive antennas which includes an integration process for thicker metals, that is, greater than 1 μm thick; material change to higher conductivity metals, for example, aluminum, copper or multi-metal structures, such as MoCr/Al/MoCr, Mo/Al/Mo and Ti/Al/Ti).
Returning now to
With the antenna structure on top of the TFT component as shown in
A cross-section of a metal-oxide TFT architecture 400 is shown in
Contact holes for the Source-Drain (SD) contacts are opened up by dry etching and 100 nm Mo is deposited and patterned to define the SD-contacts, indicated as ‘Metal 2’ and referenced as 440 in
Substrate 410, layer 430 with its semiconductor component 420, the contact holes for the SD metal or contacts (‘Metal 2’) 440 form a TFT stack on substrate 410.
In
Large parasitic coupling between the electrodes and the metals of the TFT component can also be reduced by providing additional shielding to de-couple the antenna structure from the TFIC component. This requires an isolated metal plate to be placed between the TFIC component and the antenna structure. This can be achieved by identifying and shielding components causing the largest parasitic capacitances or by shielding the entire TFIC component using a continuous shielding layer as shown in
In
In the embodiment of
The shielding layer 510 can either be connected to the power supply or ground. In addition, to provide better decoupling, a capacitor having a value in the range of 1 pF<CAB<CCAPID/2 may be included in the implementation shown in
Overlap of the TFIC component and the antenna structure can be minimized to reduce undesired coupling, for example, identification and re-design of components with the largest parasitic coupling can be performed. For example, long metal lines can be made narrower and shorter wherever possible without compromising the electrical properties (i.e. conductivity).
Where the antenna structure is fabricated below the TFIC component as shown in
For capacitive antennas, a PVD metal layer is used to form the antenna plate below the chip. In a specific case of a dual-gate TFT architecture, this PVD metal may be the same as the back-gate electrode layer.
Dipole antennas are also possible using the TFIC component as shown in
The thickness of the antenna structure is important, especially for the inductive implementation, where conductivity requirements dictate the need of a thicker layer. Any layer thicker than 200 nm would result in a non-planar surface prohibited for the subsequent TFT fabrication. To combat the non-planarity, a planarization layer may be added between the antenna structure and the TFT component (not shown). The material from which the planarization layer is made is required to withstand temperatures generated by the TFT components (typically, up to 400° C.) as well as photolithography chemistry of the subsequent process.
Two options may be implemented to reduce the parasitic coupling, namely: adding a shielding layer between the antenna structure and the TFIC component as illustrated in
Referring to architecture 600 of
Finally, the use of planarization layer as a de-coupling layer may be implemented as shown in
As shown in
In accordance with the present disclosure, there are three methods which can be used for the manufacture of a new thin-film tag. However, the main challenge is to obtain high antenna conductivity.
Electroplating methods may be used to form the conductive structures for monolithically integrated antennas. Electroplated metal films are deposited from metal cations reduced by the applied electric current. An important feature of this method is the use of a seed layer which is added to the monolithic structure at each point where the antenna is to be formed by electroplating, and, over which subsequent electroplating is performed. It is important that a uniform seed layer, for example, using a TiW/Cu composition, is deposited with PVD on the stack of layers forming the monolithic device to enable uniform electroplating. Subsequently, photoresist is spun and developed on the wafer. Electroplating of, for example, copper, is performed in the openings of the resist to define the antenna structure. Resist is subsequently stripped. Afterwards, the seed layer is etched leaving an antenna structure on top of a TFT stack.
PVD antenna structures may be deposited either as part of the TFT stack, or in a subsequent deposition. In the case, when antenna is deposited as a part of the TFT stack, two or more metallization layers, for example, gate metal, source drain metal, routing metal, may be stacked on top of one another to increase the integrated antenna conductivity. This may be achieved by selectively removing dielectric and semiconductor layers of the TFT stack in the antenna area as shown in
In
Similarly, in
In effect, in
In effect, as shown in
In this way, electromagnetic radiation from a reader configured for reading a tag incorporating an antenna device in accordance with the present disclosure can pass through the tag without interfering with the transistor layer component of the device. In particular, in
Additional deposition methods, such as, printing, may be used to form the conductive structures for monolithically integrated antennas in accordance with the present disclosure. Printing processes may be performed as post-process steps to the chip manufacturing. Printing may include, but not limited to: inkjet, gravure, offset, flexography and screen printing. Materials are conductive inks of metal or metal-oxide (nano-) particles in a solvent often with additional polymeric binders to adjust viscosity. The deposition process is followed by a sintering process to remove the organic binder and sinter the metal to achieve higher conductivity. The sintering process can be based on thermal anneal, microwave anneal, laser anneal or annealing with any other electromagnetic wave (e.g. visible light). The cost to realize structured metal layer is rather low compared to standard etch and lift-off techniques used for PVD metal, however, the lateral resolution is limited to several 10 μm. Whilst printing costs may be relatively low compared to PVD and electroplating, there are only a few metals that allow for easy ink formulation and sintering, such as, silver, and, to a lesser extent, copper.
Monolithic devices in accordance with the present disclosure are thinner, and, the antenna component and the chip component are manufactured on the same substrate without having to assemble the device from two separate substrates as described above with reference to
In addition, monolithic devices in accordance with the present disclosure are more mechanically robust, and, there is no need for any adhesive to connect the chip and the antenna together on a chosen substrate. Mechanical robustness will be increased as the new physical interface between the chip and the antenna will be larger, that is, greater than 10 mm2 (compared to the one in traditional assembly process of around 1 mm2).
The monolithic devices in accordance with the present disclosure can be implemented in thin-film RFID, NFC, CAPID tags. They may also be used for thin-film wireless sensors.
Although specific embodiments of the present disclosure have been described, these are by way of example only and other embodiments may be possible.
| Number | Date | Country | Kind |
|---|---|---|---|
| 17209346.0 | Dec 2017 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2018/086573 | 12/21/2018 | WO | 00 |
