Monolithically integrated semiconductor circuit including I.sup.2 L cells and other circuit parts

Abstract

Monolithically integrated semiconductor circuit having I.sup.2 L cells each including a transistor and an injector, further circuit parts, a supply voltage being a multiple of a supply voltage required for operation of individual I.sup.2 L cells in which a corresponding number of I.sup.2 L cells are connected in series in chain fashion with respect to a first and a second supply terminal of the circuit furnishing the supply voltage for the circuit and each being acted upon by an operating potential, the injector of an I.sup.2 L cell forming a first chain link being tied to the first supply terminal of the circuit; the emitter of the transistor of the I.sup.2 L cell forming the first chain link being tied to the injector of a further I.sup.2 L cell forming a second chain link; the injector of an I.sup.2 L cell forming a third chain link being tied to the emitter of the transistor of the I.sup.2 L cell forming the second chain link, further I.sup.2 L cells similarly connected to the respective preceding chain link forming a respective chain link completing the chain, the emitter of this I.sup.2 L cell being connected to the second supply terminal of the circuit carrying the reference potential of the circuit, and the injector of this last I.sup.2 L cell being connected to the emitter of the transistor of the I.sup.2 L cell forming the next to the last chain link, including a further I.sup.2 L cell assigned to at least one of the links of the chain formed by I.sup.2 L cells connected in series with respect to their supply potentials.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a monolithically integrated semiconductor circuit which includes I.sup.2 L cells and further circuit parts, the supply voltage of which is a multiple of the supply voltage required for the operation of the individual I.sup.2 L cells, in which a corresponding number of I.sup.2 L cells are accordingly connected in series in chain-fashion with respect to the two supply terminals of the circuit which furnish the supply voltage for the circuit and are acted upon by an operating potential each, in that the injector of an I.sup.2 L cell forming a first chain link is tied to the first supply terminal of the circuit; the emitter of the transistor of the I.sup.2 L cell forming the first chain link is tied to the injector of a further I.sup.2 L cell forming the second chain link; the injector of an I.sup.2 L cell forming the third chain link is tied to the emitter of the transistor of the I.sup.2 L cell forming the second chain link, in which the chain is finally completed, using further I.sup.2 L cells connected in the same manner to the respective preceding chain link and forming a respective chain link, by the I.sup.2 L cell forming the last chain link, in that the emitter of this I.sup.2 L cell is connected to the second supply terminal designated as VB* in the figures of the circuit which carries the reference potential of the circuit, while the injector of this last I.sup.2 L cell is directly connected to the emitter of the transistor of the I.sup.2 L cell forming the next to the last chain link.

2. Description of Prior Art

Details regarding I.sup.2 L cells may be found, for instance, in "Valvo Berichte", Volume XVIII, No. 1/2, (1974), pages 215 to 236. As is well known, the individual I.sup.2 L cells include a combination of a vertical npn transistor, with an injector constructed as a lateral pnp transistor. The base of each is surrounded by the emitter and the collectors of which each is surrounded by the base, the collector forming the signal output and the base terminal the signal input. The base of the lateral transistor is identical with the emitter of the vertical transistor and the collector of the lateral transistor is identical with the base of the vertical transistor.

The supply terminals of the I.sup.2 L cells are represented by the emitter of the lateral transistor, i.e. the injector, and the emitter of the vertical transistor. Since the values of binary potential states of an I.sup.2 L cell are U.sub.H =0.7 V and U.sub.L approximately--0.1 V and therefore a voltage excursion of about 0.8 V is needed, the problem arises, in a monolithic combination of I.sup.2 L cells with other digital circuit parts, of matching the I.sup.2 L cells to the supply voltage required for the overall circuit which in the case of TTL circuits is approximately 5 V, while the I.sup.2 L cell requires a voltage U.sub.I for the injector of about 0.8 V. For this reason, the construction of the I.sup.2 L circuits is carried out in accordance with the manner described hereinafore to build up a network of I.sup.2 L cells, so to speak. Pertinent details may be found, for instance, in a paper by K. Kameko, T. Okabe and M. Nagata from the literature reference "IEEE Journal of Solid State Circuits" (April 1977), SC12, pages 210 to 212.

One problem arising in such I.sup.2 L combinations is already solved in German Published Non-Prosecuted Application DEOS No. 27 23 973, using an auxiliary circuit. The price of this solution, however, is a considerable amount of circuitry.

On the basis of the description given hereinafore, the available supply voltage is subdivided by the individual links of the chain of I.sup.2 L cells connected between the two supply voltage terminals of the integrated semiconductor circuit into equal partial voltages, each of which is allocated as the supply voltage to the respective I.sup.2 L cell forming the respective chain link. The individual partial supply voltages, however, are assigned to staggered values of the potential at the emitters of the transistors of the individual I.sup.2 L cells. Since the individual I.sup.2 L cells interact as a rule with other I.sup.2 L cells and these I.sup.2 L cells are likewise connected between the two supply terminals as links of a chain of I.sup.2 L cells, with respect to the supply voltages that serve for setting their operating point, it may happen that one I.sup.2 L cell controls further I.sup.2 L cells, which are not acted upon exclusively by the same values of the potential present at their injector and the potential present at the emitter of its transistor as is the controlling I.sup.2 L cell. Thus, a cell to be controlled can be acted upon by supply potentials which are either closer to the first supply potential or closer to the second supply potential, i.e. the reference potential, than the I.sup.2 L cell under consideration. If the controlled I.sup.2 L cell is closer to the supply potential of the overall circuit with respect to its two supply potentials than the cell under consideration, this control is called an up control. It does not involve special problems and can therefore be ignored in the further consideration.

If, however, the controlled I.sup.2 L cell is closer to the second supply potential, i.e. to the reference potential of the circuit, with respect to its supply potentials, concern is raised about the so-called down control. As has already been set forth in the German Published Non-Prosecuted Application DEOS No. 27 23 973, down operation, i.e. controlling an I.sup.2 L cell belonging to a lower potential level or stack plane by an I.sup.2 L cell belonging to a higher I.sup.2 L cell goes along with a delay of the switching operation, because it then takes the transistor of the controlled I.sup.2 L cell a particularly long time to be ready for operation again when a signal provided by the controlling I.sup.2 L cell decays.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide a monolithically integrated semiconductor circuit including I.sup.2 L cells and other circuit parts which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, and to eliminate this adverse effect on the switching speed.

With the foregoing and other objects in view there is provided, in accordance with the invention, a monolithically integrated semiconductor circuit having I.sup.2 L cells each including a transistor and an injector, further circuit parts, a supply voltage being a multiple of a supply voltage required for operation of individual I.sup.2 L cells in which a corresponding number of I.sup.2 L cells are connected in series in chain fashion with respect to a first and a second supply terminal of the circuit furnishing the supply voltage for the circuit and each being acted upon by an operating potential, the injector of an I.sup.2 L cell forming a first chain link being tied to the first supply terminal of the circuit; the emitter of the transistor of the I.sup.2 L cell forming the first chain link being tied to the injector of a further I.sup.2 L cell forming a second chain link; the injector of an I.sup.2 L cell forming a third chain link being tied to the emitter of the transistor of the I.sup.2 L cell forming the second chain link, further I.sup.2 L cells similarly connected to the respective preceding chain link forming a respective chain link completing the chain, the emitter of this further I.sup.2 L cell being connected to the second supply terminal of the circuit carrying the reference potential of the circuit, and the injector of this last I.sup.2 L cell being connected to the emitter of the transistor of the I.sup.2 L cell forming the next to the last chain link, comprising a further I.sup.2 L cell assigned to at least one of the links of the chain formed by I.sup.2 L cells connected in series with respect to their supply potentials, the further I.sup.2 L cell being controlled by the chain link and the supply potentials thereof being at least as far from i.e. not closer to, the supply potential furnished by the first supply terminal of the circuit than the supply potentials of the controlling I.sup.2 L cell; and the two supply potentials of the controlled I.sup.2 L cell being combined in a single supply potential, the injector input of the controlled I.sup.2 L cell and the emitter of the transistor thereof being connected together to the emitter of the transistor of an I.sup.2 L cell belonging to the chain of I.sup.2 L cells, the supply potential acting on the emitter of the transistor of the I.sup.2 L cell belonging to the chain of I.sup.1 L cells being at least as close to, i.e. not further away from, the reference potential supplied by the second supply terminal of the circuit as the potential controlling the emitter of the transistor of the I.sup.2 L cell forming the controlling chain link.

If the totality of the I.sup.2 L cells connected with their injectors directly to the first supply terminal of the circuit is designated as the first supply level, the totality of the I.sup.2 L cells that obtain their injector supply potential from the I.sup.2 L cells of the first supply level, as the second supply level, and so forth, and finally the totality of the I.sup.2 L cells connected to the second terminal of the circuit carrying the reference potential, as the last supply level. In this case, the just given definition of the invention means that the controlled I.sup.2 L cell belongs either to the same supply level as the controlling I.sup.2 L cell or it must be counted, as a supply level which is higher-numbered in comparison to the controlling I.sup.2 L cell, i.e. is closer to the reference potential. The first-mentioned case is of interest only if the controlling I.sup.2 L cell and the controlled I.sup.2 L cell are connected together to the reference potential; the second case, namely the case in which the supply level of the controlled I.sup.2 L cell is closer to the second supply potential of the circuit, i.e. at the reference potential than the level of the controlling I.sup.2 L cell, is the more general case. The second case is always applied if the controlling transistor does not belong to the highest-numbered supply level, associated with the reference potential, of the I.sup.2 L network.

Besides the just described I.sup.2 L cells, which are controlled in down operation, I.sup.2 L cells also occur as a rule which are controlled by I.sup.2 L cells that belong to a higher-numbered supply level, which is therefore closer to the reference potential, than the controlled I.sup.2 L cell. In these cases, the controlled I.sup.2 L cells are connected in the customary manner, i.e. like the individual links of the I.sup.2 L supply chain, so that the injector and the emitter of the transistor of the respective cell are at supply potentials which are different from each other. In the case of I.sup.2 L cells controlled in up-operation, no particular measure is therefore taken, if the former is used in addition to down-operation in an I.sup.2 L circuit according to the invention.

In accordance with another feature of the invention, the potential at the emitter of the transistor of the controlled I.sup.2 L cell is closer to the reference potential of the circuit than the potential at the emitter of the transistor of the controlling I.sup.2 L cell.

In accordance with a further feature of the invention, the I.sup.2 L cells are identical.

In accordance with an added feature of the invention, the base of the transistor of the controlled I.sup.2 L cell is directly connected to the collector of the transistor of the controlling I.sup.2 L cell.

In accordance with an additional feature of the invention, there is provided a diode connecting the collector of the transistor of the controlling I.sup.2 L cell to an I.sup.2 L cell to be controlled which is closer to the reference potential.

In accordance with a concomitant feature of the invention, there is provided an injector connecting the collector of the transistor of the I.sup.2 L cell to be controlled to the base of the transistor of the controlled I.sup.2 L cell.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a monolithically integrated semiconductor circuit including I.sup.2 L cells and other circuit parts, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

BRIEF DESCRIPTION OF THE DRAWING

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:

FIGS. 1 to 3 are schematic diagrams of I.sup.2 L cells of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now more particularly to FIGS. 1 to 3 of the drawing as a whole, it is seen that the transistor T is the transistor of the controlling I.sup.2 L cell and J is its injector. The supply potential for the injector J is designated with reference symbol V.sub.JJ and corresponds to the first supply potential furnished by the first supply terminal of the circuit, if the controlling I.sup.2 L cell belongs to the first supply level. In the other cases, the supply potential V.sub.JJ for the injector of the controlling I.sup.2 L cell corresponds to the potential at the emitters of the transistors of the I.sup.2 L cells belonging to the next supply level in the direction toward the first supply potential.

The transistors of the respective controlled I.sup.2 L cell are designated with reference symbol t and their injector with j. The emitter potential for the transistor T of the controlling I.sup.2 L cell is VZ and corresponds to the potentials in the individual nodes of the I.sup.2 L network, since it is derived by voltage division of the total supply voltage supplied by the two supply terminals of the circuit.

In the embodiment shown in FIG. 1, the base of the transistor t of the cell to be controlled is directly connected to the collector of the transistor T of the controlling I.sup.2 L cell. If, however, the supply potentials of the controlling and the controlled I.sup.2 L cell are not immediately adjacent as in FIG. 1, but if one or more supply potentials must be jumped, then one or more diodes must be inserted into the connection from the collector of the controlling transistor T to the base of the controlled transistor to in such a manner that the collector or anode of the diode or the diodes is always connected to the collector of the controlling transistor T and the emitter or cathode of the diode or diodes is connected to the base of the controlled transistor t. The input of the injector j of the controlled I.sup.2 L cell and the emitter of its transistor t are at a common potential VB*. By virtue of the potential obtained due to the voltage division described above, the common potential VB* is applied to the emitter of the I.sup.2 L cells of one of the supply levels of the I.sup.2 L cells belonging to the I.sup.2 L network, which is closer to the reference potential VB of the overall circuit and the supply level V.sub.JJ /VZ to which the controlling I.sup.2 L cell belongs. Optionally, the potential VB* may be identical with the potential VB, as is easily seen. According to the invention, the emitter of the transistor t of the controlled I.sup.2 L cell is now connected, together with the input of the injector j of this cell, to the emitter supply potential VB* of a supply level which is closer to the reference potential VB than the supply potential level of the controlling I.sup.2 L cell.

In the case shown in FIG. 2, the transistor T of the controlling I.sup.2 L cell on one hand controls a cell belonging to the same supply level and on the other hand, in down operation, it controls a further I.sup.2 L cell belonging to some supply level. Similar to FIG. 1, the control is accomplished by the action of the collector of the transistor of the controlling I.sup.2 L cell on the base of the transistor t of the controlled I.sup.2 L cell.

In the embodiment set forth in FIG. 2, the collector of the transistor T of an I.sup.2 L cell simultaneously controls the input of an I.sup.2 L cell belonging to the same supply level and the input of an I.sup.2 L cell belonging to a lower supply level, i.e., one closer to the common reference potential VB. For this reason, a diode D is provided between the transistor T of the controlling I.sup.2 L cell and the transistor t of the controlled I.sup.2 L cell from the lower supply level. The diode D is not required if connected to the transistor t of the I.sup.2 L cell belonging to the same supply level as the controlling I.sup.2 L cell.

In the circuit shown in FIG. 3, an injector I is disposed between the input of the controlled I.sup.2 L cell belonging to the lower supply level and the controlling I.sup.2 L cell belonging to the higher supply level. This construction of the injector I corresponds to that of the other injectors of the I.sup.2 L cells. It is accordingly formed by a second injector zone which is disposed in the vicinity of the base zone of the transistor t that belongs to the lower supply level and is connected to the collector of the transistor T of the controlling I.sup.2 L cell in a conducting manner. Meanwhile the first injection zone forming the injector j is connected to the emitter of the transistor t of this cell and, together with the latter, is connected to the second supply potential VB* of this cell.

The objective of the invention is to attempt to clear out the charge carriers in the base of the transistors in the controlled I.sup.2 L cells as fast as possible, even if the controlled I.sup.2 L cell belongs to a lower supply level than the controlling I.sup.2 L cell, which is specifically for the case of down operation, i.e. an I.sup.2 L cell belonging to a lower supply level is controlled by an I.sup.2 L cell from a higher supply level. The achievement of the invention is that in this case the switching speed is also not slowed down more than in the case in which the controlling I.sup.2 L cell and the controlled I.sup.2 L cell belong to the same supply level.

If simultaneous logical linkages are provided between I.sup.2 L cells of the same supply level and I.sup.2 L cells of lower supply levels in changing over, the diode D shown in FIG. 2 is provided between the output of the controlling I.sup.2 L cell belonging to the higher supply level and the input of the controlled I.sup.2 L cell belonging to a lower supply level, while such a diode is not necessary for controlling the I.sup.2 L cell belonging to the same supply level as the controlling I.sup.2 L cell. The anode of the diode D is then connected to the collector of the transistor T of the controlling I.sup.2 L cell, and the cathode of this diode D is connected to the base of the transistor t of the I.sup.2 L cell belonging to the lower supply level.

The circuit is usually implemented so that the vertical transistor T or t, respectively, is of the npn type, and the lateral transistor, i.e. the injector J, j, I is of the pnp type. Conversely, the vertical transistor could also be of the pnp type and the lateral transistor of the npn type. This means a reversal of the supply voltage.

Claims

1. In a monolithically integrated semiconductor circuit, comprising a first supply voltage terminal and a second supply voltage terminal (said second supply voltage terminal carrying the reference potential for the circuit) a plurality of I.sup.2 L cells each respectively forming a vertical transistor having base, emitter and collector electrodes and an injector having an input, said first and said second supply voltage terminals being connected to each other by a chain consisting of said I.sup.2 L cells directly disposed adjacent each other in serially stacked connection, the chain including a first I.sup.2 L cell and a last I.sup.2 L cell, the first I.sup.2 L cell having the input of the injector thereof connected to said first supply voltage terminal, the last I.sup.2 L cell of said chain having the emitter electrode of the vertical transistor thereof connected to said second supply voltage terminal, and in each pair of directly adjacent I.sup.2 L cells of said chain the emitter electrode of the vertical transistor of the I.sup.2 L cell connected closer to said first supply voltage terminal being directly conductively connected to the input of the injector of the I.sup.2 L cell connected closer to said second supply voltage terminal, said integrated semiconductor circuit further comprising a controlling connection between the collector electrode of the vertical controlling transistor of an I.sup.2 L cell belonging to said chain and the base electrode of the vertical transistor of a controlled further one of said I.sup.2 L cells, which does not belong to said chain but is conductively connected at the emitter electrode of its vertical transistor to the emitter electrode of the vertical transistor of an I.sup.2 L cell, which belongs to said chain but lies closer in said chain to the second supply voltage terminal than said controlling I.sup.2 L cell, the input of the injector of said controlled I.sup.2 L cell being exclusively connected to the emitter electrode of the vertical transistor of said controlled I.sup.2 L cell.

2. Semiconductor circuit according to claim 1, wherein the collector electrode of the vertical transistor of said controlling I.sup.2 L cell is directly connected to the base electrode of the vertical transistor of said controlled I.sup.2 L cell.

3. Semiconductor circuit according to claim 2, wherein the emitter electrode of the vertical transistor of said controlled I.sup.2 L cell being connected to the emitter electrode of the vertical transistor of an I.sup.2 L cell of said chain, said I.sup.2 L cell being adjacent to the controlling I.sup.2 L cell disposed in direction toward the second supply voltage terminal.

4. Semiconductor circuit according to claim 1, wherein the emitter electrode of the vertical transistor of said controlled I.sup.2 L cell is connected to the emitter electrode of an I.sup.2 L cell belonging to said chain, which is separated at least by one I.sup.2 L cell of said chain from the controlling I.sup.2 L cell, the controlling connection between the collector of said controlling I.sup.2 L cell and the base of said controlled I.sup.2 L cell contains at least one diode.

5. Semiconductor circuit according to claim 1, wherein the controlling connection between the collector of said controlling I.sup.2 L cell and the base of said controlled I.sup.2 L cell consists of a further injector, the input of which is connected to the collector of the vertical transistor of said controlling I.sup.2 L cell and the output of which is connected to the base of the vertical transistor of said controlled I.sup.2 L cell.