Claims
- 1. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, said combined differential output current including a plurality of differential output currents, said MOS four-quadrant multiplier comprising:
- first and second two-quadrant multipliers each having a differential output;
- each of said first and second two-quadrant multipliers having first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors;
- said second pair of transistors of said first two-quadrant multiplier each having drains which are directly connected in common to a corresponding drain of said second pair of transistors in said second two-quadrant multiplier, said second pair of transistors having gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors in each of said first and second two-quadrant multipliers, said third pair of transistors of each of said first and second two-quadrant multipliers having gates connected in common to each other at an input voltage node in each of said first and second two-quadrant multipliers, wherein each differential output current of said plurality of differential output currents, which is generated in one of said first and second two-quadrant multipliers, comprises at least a drain current of said second pair of transistors included in said one of said first and second two-quadrant multipliers;
- said differential outputs of said first and second two-quadrant multipliers being provided to supply said combined differential output current;
- wherein drains of all of said third pairs of transistors of said first and second two-quadrant multipliers are directly connected in common at a first node;
- wherein said first differential input voltage is applied between the gates of said first pair of transistors in each of said first and second two-quadrant multipliers; and
- wherein said second differential input voltage is applied between the input voltage node of said first two-quadrant multiplier and the input voltage node of said second two-quadrant multiplier.
- 2. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, said combined differential output current including a plurality of differential output currents, said MOS four-quadrant multiplier comprising:
- first and second two-quadrant multipliers each having a differential output;
- each of said first and second two-quadrant multipliers including first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors;
- said second pair of transistors having gates respectively connected to drains of said first pair of transistors and sources of said third lair of transistors in each of said first and second two-quadrant multipliers, said third pair of transistors of each of said first and second two-quadrant multipliers having gates connected in common to each other at a node in each of said first and second two-quadrant multipliers;
- wherein a drain of a first transistor of said second pair of transistors in said first two-quadrant multiplier is directly connected in common at a first node to a drain of a first transistor of said third pair of transistors in said first two-quadrant multiplier, said first transistor of said second pair of transistors in said first two-quadrant multiplier including a gate which is directly connected in common to a source of said first transistor of said third pair of transistors in said first two-quadrant multiplier;
- wherein a drain of a second transistor of said second pair of transistors in said first two-quadrant multiplier is directly connected in common at a second node to a drain of a second transistor of said third pair of transistors in said first two-quadrant multiplier, said second transistor of said second pair of transistors in said first two-quadrant multiplier including a gate which is directly connected in common to a source of said second transistor of said third pair of transistors in said first two-quadrant multiplier;
- wherein a drain of a first transistor of said second pair of transistors in said second two-quadrant multiplier is directly connected at a third node to a drain of a first transistor of said third pair of transistors in said second two-quadrant multiplier, said first transistor of said second pair of transistors in said second two-quadrant multiplier including a gate which is directly connected in common to a source of said first transistor of said third pair of transistors in said second two-quadrant multiplier, said first and third nodes being directly connected in common;
- wherein a drain of a second transistor of said second pair of transistors in said second two-quadrant multiplier is directly connected in common at a fourth node to a drain of a second transistor of said third pair of transistors in said second two-quadrant multiplier, said second transistor of said second pair of transistors in said second two-quadrant multiplier including a gate which is directly connected in common to a source of said second transistor of said third pair of transistors in said second two-quadrant multiplier, said second and fourth nodes being directly connected in common;
- wherein each differential output current of said plurality of differential output currents, which is generated in a corresponding one of said first and second two-quadrant multipliers, comprises at least a drain current of said second pair of transistors included in said one of said first and second two-quadrant multipliers;
- said differential outputs of said first and second two-quadrant multipliers forming said combined differential output current;
- wherein said first differential input voltage is applied between the gates of said first pair of transistors in each of said first and second two-qauadrant multipliers; and
- wherein said second differential input voltage is applied between the node of said first two-qauadrant multiplier and the node of said second two-quadrant multiplier.
- 3. The MOS four-quadrant multiplier according to claim 1, wherein a power supply voltage is applied to the drains of the third pair of transistors in each of said first and second two-quadrant multipliers.
- 4. The MOS four-quadrant multiplier according to claim 1, further comprising a current mirror circuit for converting said combined differential output current into a single-ended output current.
- 5. A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to a product of first and second differential input voltages, comprising:
- first and second variable-gain cells for generating a differential output current at a gain depending on an applied tuning voltage in response to a first differential input voltage applied thereto;
- each of said first and second variable-gain cells comprising a tail current source, first and second pairs of transistors having sources connected in common to each other and to said tail current source, and a third pair of transistors connected in cascade to the first pair of transistors as a load on the first pair of transistors;
- said second pair of transistors having gates connected to drains of said first pair of transistors in each of said first and second variable-gain cells, said third pair of transistors in said first variable gain cell including transistors having gates which are connected in common to respective gates of the transistors of the third pair of transistors in said second variable cell at first and second nodes for applying the tuning voltage therebetween, said first pair of transistors of said first and second variable gain cells having gates for applying the first differential input voltage therebetween in each of said first and second variable-gain cells, said differential output current containing at least drain currents of the second pair of transistors;
- said first and second variable-gain cells having differential outputs which are provided to supply a combined differential output current.
- 6. The MOS four-quadrant multiplier according to claim 5, wherein a drain of each transistor of the second pair of transistors of one of said first and second variable-gain cells is connected in common to respective drains of the second and third pairs of transistors in each of said first and second variable-gain cells.
- 7. The MOS four-quadrant multiplier according to claim 5, wherein a drain of each transistor of said second pair of transistors of one of said first and second variable-gain cells is directly connected in common to a respective drain of one of the transistors of said second pair of transistors in the other of said first and second variable-gain cells.
- 8. The MOS four-quadrant multiplier according to claim 5, wherein a power supply voltage is applied to the drains of the third pair of transistors in each of said first and second variable-gain cells.
- 9. The MOS four-quadrant multiplier according to claim 5, wherein the gates of the first pair of transistors are connected in common to each other and said first differential input voltage is applied between the gates of the first pair of transistors in said first and second variable-gain cells.
- 10. The MOS four-quadrant multiplier according to claim 5, wherein said first differential input voltage is applied between the gates of the first pair of transistors.
Priority Claims (4)
Number |
Date |
Country |
Kind |
6-130469 |
Jun 1994 |
JPX |
|
6-130470 |
Jun 1994 |
JPX |
|
6-130471 |
Jun 1994 |
JPX |
|
6-301991 |
Dec 1994 |
JPX |
|
Parent Case Info
This is a Continuation Application of U.S. application Ser. No. 08/488,412, filed on Jun. 7, 1995, now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (2)
Number |
Date |
Country |
52-61946 |
May 1977 |
JPX |
4-343505 |
Nov 1992 |
JPX |
Non-Patent Literature Citations (1)
Entry |
"A CMOS Four-Quadrant Analog Multiplier", K. Bult and H. Wallinga, IEEE Journal of Solid State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 430-435. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
488412 |
Jun 1995 |
|