Patent Application
20090009643
The present invention relates to a MOS type solid-state image pickup device that includes a MOS dynamic type shift register, and to a method for driving such a device.
In recent years, an electronic shutter has been adopted for electronic aperture control of a MOS type solid-state image pickup device.
Signal charge, which has been generated and accumulated through photoelectric conversion in a photodiode of an image pickup element, is transferred to a floating diffusion when read out, and then is reset. In general, although the accumulation is started again after the reset, the signal charge can be accumulated only for a certain period of time corresponding to a frame rate.
On the other hand, the electronic shutter allows a period of time for the accumulation of the signal charge in the photodiode to be variable, by transferring the signal charge accumulated in the photodiode to the floating diffusion for resetting before the readout.
The reset and readout of the signal charge in the photodiode are performed through an electronic shutter operation by a plurality of shift registers for each line. The number of stages in each shift register is equal to the number of lines of the image pickup elements, and clock signals are set to be in synchronization with a shift operation. On account of this, when light of the same intensity enters all of the image pickup elements, the same amount of signal charge can be accumulated in each photodiode in theory.
This solid-state image pickup device is composed of: a pixel unit 100 that includes image pickup elements arranged two-dimensionally; a shift register 101 that outputs a line selection signal to select one line of the pixel unit 100 for a readout operation; a shift register 102 that outputs a line selection signal to select one line of the pixel unit 100 for an electronic shutter operation; a signal processing unit 103 that extracts a pixel signal from the selected pixel; a horizontal selection shift register 104 that outputs a column selection signal; and an amplifier circuit 105 that amplifies the extracted pixel output signal.
Moreover, each pixel is provided with: a photodiode 201 that converts the incident light into signal charge; a read transistor 202 that reads the signal charge generated in the photodiode 201; a floating diffusion unit (FD unit) 203 that holds the read signal charge; a reset transistor 204 that resets the FD unit 203 to a potential of a power signal line 209; an amplifier transistor 205 that amplifies and outputs the potential change of the FD unit 203; a vertical output signal line 206 that sends the output signal from the amplifier transistor 205 to the signal processing unit 103; a readout signal line 207 that inputs a line selection signal for the readout operation to the read transistor 202; a reset signal line 208 that sends a selection signal to the reset transistor 204; and a power signal line 209 that is power to the amplifier transistor 205.
Furthermore, a load transistor 210 that keeps the voltage of the vertical output signal line 206 constant is provided outside a pixel area. The load transistor 210 forms a source follower circuit with the amplifier transistor 205 of the selected line when the pixel output signal is read out.
The vertical output signal line 206 is provided for each column, and is connected to an output of the corresponding amplifier transistor 205 of each line.
The readout signal line 207 is provided for each line, and is connected to an input of the read transistor 202 of the corresponding line. Signals are supplied to the readout signal line 207 from the shift registers 101 and 102.
The reset signal line 208 is provided for each line, and is connected to an input of the reset transistor 204 of the corresponding line. Signals are supplied to the reset signal line 208 from the shift registers 101 and 102.
The power signal line 209 is provided for each line, and is connected to drains of the reset transistor 204 and the amplifier transistor 205 of the corresponding line.
For an electronic shutter operation, a start signal SHT is first inputted to the shift register 102 for an electronic shutter, so that a shift operation is started in synchronization with clock signals CLK1 and CLK2 for the shift operation and that the signal charges accumulated in the photodiodes of the image pickup elements are reset for each line using selection signals of SHT(1)th line to SHT(m)th line. Next, a start signal VST is inputted to the readout shift register 101, so that the shift operation is started in synchronization with the clock signals CLK1 and CLK2 and that the signal charges accumulated in the photodiodes are read out for each line using readout selection signals of READ(1)th line to READ(m)th line. Here, an accumulation time for the signal charge refers to a time lag between the start signals SHT and VST respectively inputted to the above-mentioned two shift registers. After the readout from the readout shift register for each line using the selection signal, the read signal is held by the signal processing unit 103. Then, a column is selected in accordance with a selection signal from the horizontal selection shift register 104, and the amplified signal is outputted through the amplifier circuit 105.
As compared to the solid-state image pickup device shown in
Patent Reference 1: Japanese Laid-Open Patent Application No. 2000-125203
Patent Reference 2: Japanese Laid-Open Patent Application No. 2004-312311
According to the above conventional technique, after the scanning of the pixel unit is completed, a blanking period occurs, during which each of the shift registers does not operate until a start signal is inputted for a next frame.
Due to the presence of this blanking period, the electric potential state of the vertical output signal line 206 varies between: when the electronic shutter shift register and the readout shift register are both scanning the pixel unit; and when either of the electronic shutter shift register and the readout shift register is in the blanking period. This is because the read signal line 207, the reset signal line 208, and the like cross the vertical output signal line 206, and each accordingly has a parasitic capacity. The variations in the electric potential state of the vertical output signal line 206 result in variations in the output voltage even with incident light of the same intensity, thereby causing a horizontal strip noise to an image that thus degrades the image quality.
The present invention is conceived in view of the problem described above, and has an object of providing a MOS type solid-state image pickup device for preventing occurrence of noise resulted from the electronic shutter and a method for driving such a device.
In order to solve the problem-described above, the MOS type solid-state image pickup devices of the present invention includes: a pixel unit and a plurality of shift registers, the pixel unit including image pickup elements arranged in a matrix, and the plurality of shift registers each selecting a line or a column of the pixel unit, wherein at least one of the plurality of shift registers, each of which selects a line, includes: a plurality of unit registers, each of which holds a selection signal; and a dummy signal generation circuit which outputs a dummy selection signal to a last line and a line that is at least second from the last line of the pixel unit, during a blanking period of a line scanning operation performed on the pixel unit. With this construction, the dummy selection signal is alternately outputted, during the blanking period, from the unit register that selects the last line and from the unit register that is at least one stage ahead of the unit register that selects the last line, so that the variations in the electric potential state of the vertical signal line between the valid pixel period and the blanking period is eliminated. On account of this, a horizontal strip noise in an image due to the electronic shutter operation can be prevented from occurring, and a high-quality image can be thus obtained.
It is preferable that the dummy signal generation circuit has a reset circuit which resets a unit register of a last stage and a unit register of a second-from-the-last stage using a value of the unit register that is one stage ahead of the unit register that selects the last line.
It is preferable that the dummy selection signal is outputted alternately to the last line and the line that is at least second from the last line, at constant intervals.
It is preferable that the dummy signal generation circuit: includes a unit register of a last stage and a unit register of a stage that is at least second from the last stage; and constructs a loop by inputting an output signal of the unit register of the last stage to the unit register of the stage that is at least second from the last stage.
It is preferable that the unit register of the last stage is set subsequent to the unit register that selects the last line of the pixel unit, and the output signal of the unit register of the last stage is inputted to the unit register that selects the last line and to the unit register that selects the second-from-the-last line.
The unit register of the last stage may select the last line of the pixel unit, and the output signal of the unit register of the last stage may be inputted to the unit register of the second-from-the-last stage.
It is preferable that the output signal of the unit register of the last stage is inputted to the unit register of the stage that is at least second from the last stage, via a current-entering prevention unit.
It is preferable that a value held in said unit register of the second-from-the-last stage is inputted to and held in said unit register of the last stage, in synchronization with a first signal for a shift operation of said shift register which selects a line, and a value held in said unit register of the last stage is inputted to and held in said unit register of the second-from-the-last stage, in synchronization with a second signal for a shift operation of said shift register which selects a line.
It is preferable that the dummy signal generation circuit further has a reset unit which resets the value held in the unit register of the last stage, using a start signal for the shift register.
It is preferable to further have a unit which resets an output of the unit register of the last stage using an inversion signal of the output from the reset unit.
It may have a reset unit which resets the value held in the unit register of the last stage and an output of the unit register of the last stage, using a start signal for the shift register.
It is preferable that the shift registers, each of which selects a line, includes: a readout shift register which outputs a line selection signal to select a line of the pixel unit for an operation performed to read out an output signal of the pixel unit; and an electronic shutter shift register which outputs a line selection signal to select a line of the pixel unit for an electronic shutter operation.
It is preferable that each of the readout shift register and the electronic shutter shift register outputs the dummy selection signal during the blanking period.
It is preferable that the MOS type solid-state image pickup device further includes a multiplexing unit which multiplexes, for each line, the line selection signal outputted from the readout shift register and the line selection signal outputted from the electronic shutter register and outputs the multiplexed signal to the pixel unit, wherein when a first dummy signal and a second dummy signal are outputted to the same line at the same time, the multiplexing unit cuts off one of the inputs of the first and second dummy signals, the first dummy signal being the dummy selection signal outputted from the readout shift register, and the second dummy signal being the dummy selection signal outputted from the electronic shutter shift register.
It is preferable that the multiplexing unit includes a cut-off switch which electrically cuts off one of the inputs of the first and second dummy signals outputted to the same line at the same time, by using the other one of the dummy selection signals.
It is preferable that the cut-off switch is turned on or off in accordance with the first dummy signal.
It is preferable that the multiplexing unit includes a first output circuit and a second output circuit, the first output circuit outputting the first dummy signal to a line-selection signal line in synchronization with a first drive signal, and the second output circuit outputting the second dummy signal to the line-selection signal line in synchronization with a second drive signal, and that the cut-off switch is inserted into an input signal line which transmits the second dummy signal to the second output circuit.
It is preferable that the multiplexing unit further includes a stop circuit, which stops an operation of the second output circuit when the first and second dummy signals are outputted to the same line at the same time.
It is preferable that the stop circuit further stops the second output circuit when the first dummy signal is outputted.
It is preferable that the stop circuit has an inverter for inverting the first dummy signal, and turns off the cut-off switch in accordance with the inversion signal.
It is preferable that the inverter has a load resistance and a drive transistor which are series connected between a power line and a ground line and that a resistance value of the load resistance is greater than a resistance value of the drive transistor.
It is preferable that the cut-off switch and the stop circuit are provided corresponding to a line to which the first and second dummy signals are to be outputted.
A camera of the present invention includes the above-described MOS type solid-state image pickup device of the present invention.
A driving method for the MOS type solid-state image pickup device of the present invention is a method for driving a MOS type solid-state image pickup device which includes a pixel unit and a plurality of shift registers, the pixel unit including image pickup elements arranged in a matrix, and the plurality of shift registers each selecting a line or a column of the pixel unit, and the method including a step of outputting, during a blanking period of a line scanning operation performed on the pixel unit, a dummy selection signal to at least a last line of the pixel unit from a shift register, out of the plurality of shift registers which each select a line.
It is preferable that the shift register for selecting a line outputs the dummy selection signal to the last line and a line that is at least second from the last line, the lines being included in the pixel unit.
It is preferable that the dummy selection signal is outputted alternately to the last line and the line that is at least second from the last line, at constant intervals.
It is preferable that a signal for driving at least the shift register which selects a line is externally supplied.
Another driving method for the MOS type solid-state image pickup device of the present invention is a method for driving a MOS type solid-state image pickup device which includes a pixel unit, a readout shift register, and an electronic shutter shift register, the pixel unit including image pickup elements arranged in a matrix, the readout shift register outputting a line selection signal to select one line of the pixel unit for an operation performed to read out an output signal of the pixel unit, the electronic shutter shift register outputting a line selection signal to select one line of the pixel unit for an electronic shutter operation, and the method including a step of outputting, during a blanking period of a line scanning operation performed on the pixel unit, a dummy selection signal to at least a last line of the pixel unit from each of the readout shift register and the electronic shutter shift register.
It is preferable that each of the readout shift register and the electronic shutter shift register outputs the dummy selection signal to the last line and a line that is at least second from the last line, the lines being included in the pixel unit.
It is preferable that the dummy selection signal is outputted alternately to the last line and the line that is at least second from the last line, at constant intervals.
It is preferable that signals for respectively driving at least the readout shift register and the electronic shutter shift register are externally supplied.
It is preferable that the MOS type solid-state image pickup device further includes a multiplexer which multiplexes, for each line, the line selection signal outputted from the readout shift register and the line selection signal outputted from the electronic shutter register and outputs the multiplexed signal to the pixel unit, and that the driving method further includes a step of cutting off, when a first dummy signal and a second dummy signal are outputted to the same line at the same time, one of the inputs of the first and second dummy signals to the multiplexer, the first dummy signal being the dummy selection signal outputted from the readout shift register, and the second dummy signal being the dummy selection signal outputted from the electronic shutter shift register.
It is preferable that in the cutting-off step, one of the inputs of the first and second dummy signals outputted to the multiplexer to the same line at the same time is electrically cut off by using the other one of the dummy selection signals.
It is preferable that in the cutting-off step, the input of the second dummy signal to the multiplexer is cut off in accordance with the first dummy signal.
According to the MOS type solid-state image pickup device of the present invention, the dummy selection signal is alternately outputted, during the blanking period, from the unit register that selects the last line and the unit register that is at least one stage ahead of the unit register that selects the last line, so that the variations in the electric potential state of the vertical signal line between the valid pixel period and the blanking period is eliminated. On account of this, a horizontal strip noise in an image due to the electronic shutter operation can be prevented from occurring, and a high-quality image can be thus obtained.
Moreover, the timing of the electronic shutter can be arbitrarily set within one horizontal scanning period, and in addition, the image quality can be prevented from degrading.
This solid-state image pickup device is composed of: a pixel unit 110 that includes image pickup elements arranged two-dimensionally; a shift register 111 that outputs a line selection signal to select one line of the pixel unit 110 for a readout operation; a shift register 112 that outputs a line selection signal to select one line of the pixel unit 110 for an electronic shutter operation; a signal processing unit 113 that extracts a pixel signal from the selected pixel; a horizontal selection shift register 114 that outputs a column selection signal; and an amplifier circuit 115 that amplifies the extracted pixel output signal. A construction of a pixel cell of the pixel unit 110 is the same as the one shown in
A dummy pulse generation circuit 116, which is indicated by a dash line, of the shift registers 111 and 112 has a function of generating a dummy pulse during the blanking period. When the blanking period occurs following the completion of the scanning up to the last line, a selection signal is outputted from the dummy pulse generation circuit 116 alternately to a last line (m) and a second last line (m−1) of the shift register.
This selection signal does not directly contribute to the operation for reading out the pixel output signal nor the electronic shutter operation, but is a so-called dummy signal which is outputted to keep the electric potential state of the vertical output signal line constant.
As shown in
Furthermore, the shift register is composed of a transistor TR3 which resets a value held in the register REG4 of the last stage using the output signal from the inverter circuit INV1. By resetting the value of the unit register REG4 of the last stage, a malfunction is prevented from occurring to the register loop.
Each of the unit registers REG1 to REG3 writes the value inputted to a terminal IN into the register during a High period of a clock signal CLA, and holds the value during a Low period of the signal. Then, the unit register outputs the hold signal from a terminal OUT during a High period of a clock signal CLB.
Each output terminal OUT of the unit registers REG1 to REG3 is connected, via a corresponding one of diode-connected unidirectional transistors TR4-1 to TR4-4, to the input terminal IN of a unit register of a next stage. Such a transistor having its gate and drain short circuited prevents current entry from the output of a unit register to the input of a unit register of a next stage and also prevents the value held in the register from being lost due to an output from a unit register of a previous stage.
The output OUT of the unit register REG4 of the last stage is connected, via the unidirectional transistor TR4-4, to each input terminal IN of the unit register REG3 of the second last stage and the unit register REG2 of the third last stage. A signal outputted, in synchronization with CLK1, from the unit register REG3 which selects the last line is held in the register REG4 in synchronization with CLK1. The value held in the register REG4 is next outputted in synchronization with CLK2, and held in the register REG3 in synchronization with CLK2. In this way, the loop made up of the register REG4 and the unit registers REG2 and REG3 of the previous stages allows for alternate repetitive outputs in synchronization with the clock signals CLK1 and CLK2.
Upon the input of a start signal START for the shift register, the shift operation is started in synchronization with CLK1 and CLK2 and then selection signals OUT1 to OUT3 are sequentially outputted. The selection signal OUT3 is outputted from the unit register REG3 of the last line, and the scanning in the valid pixel period is thus completed. Then, until the start signal START is inputted for a next frame, dummy selection signals OUT2 and OUT3 are outputted respectively from the unit registers REG2 and REG3 of the last and second last lines.
A circuit indicated by a dash line in the diagram functions as a dummy signal generation circuit composed of at least two unit registers that respectively output the dummy selection signals to the last line and a line that is at least second from the last line of the pixel unit. That is, in the shift register shown in this diagram, an output of a unit register REG14 of the last stage is connected to an input of a unit register REG13 of the second last stage, thus forming a register loop as in the case shown in
A circuit indicated by a dash line in the shift register shown in this diagram functions as a dummy signal generation circuit composed of at least two unit registers that respectively output the dummy selection signals to the last line and a line that is at least second from the last line of the pixel unit. An output of a unit register of the last stage is connected to an input of a unit register of the second last stage via a transistor TR21-4 as is the case with
An inverter circuit INV12 and transistors TR20, TR22, and TR23-3 of the dummy signal generation circuit make up a circuit that resets the registers REG13 and REG14 using the start signal for the shift register. This circuit resets values held in the unit registers REG13 and REG14 of the last and second last stages, using the start signal for a next frame.
Moreover, an inverter circuit INV13, transistors TR21, TR19, TR20, TR23-4, TR23-5, and an INV14 make up a reset circuit that resets a value held in the unit register REG14 of the last stage using an inversion signal of a value held in the unit register REG13 of the second last stage. The transistor TR21 resets the value held in the unit register REG14 of the last stage using the inversion signal (i.e., the output from the inverter circuit INV13) of the value held in the unit register REG13 of the second last stage. The transistor TR19 resets the value held in the unit transistor REG13 of the second last stage using the above-mentioned inversion signal (the transistor 23-5 is On at this time).
Furthermore, the inverter circuit INV14 turns off the transistor TR23-5 when an output OUT11 of the unit register REG11 is High (Accordingly, when a shift is made from the unit register REG12 to the unit register REG13, the loop made up of the inverter circuit INV13 and the transistors TR19 and TR23-5 is disconnected.).
With this construction, the circuit configuration can be simplified without adding registers, as is the case with
With this construction, no additional unit register is needed subsequent to the unit register that selects the last line, which contributes to the simplification of the circuit configuration.
As in the case shown in
According to the present embodiment as described so far, even after the end of the period for reading the pixels, both of the readout shift register and the electronic shutter shift register keep sending the selection signals to the pixel unit so that the variations in the electric potential state of the vertical output signal line caused during the scanning period of the image pickup elements are eliminated and that occurrence of noise resulting from the electronic shutter operation can be prevented. In particular, a horizontal strip noise can be prevented from occurring to an image, and thus a high-quality image can be obtained.
The above-described shift registers 111 and 112 are included in the solid-state image pickup device 72, and the clock signals CLK1 and CLK2 and the start signal START are supplied from the DSP 71.
Such a construction can prevent noise occurrence that may be caused due to the electronic shutter operation as well as preventing a horizontal strip noise in an image, and a high-quality image can be thus obtained. Therefore, it is suitable for a mobile camera incorporated into a cellular phone or the like, and for a digital steel camera.
In the case of the solid-state image pickup device of the first embodiment, the selection signals SHT(1) to SHT(m) are outputted in synchronization with the pulses of the clock signals CLK1 and CLK2. In the second embodiment, an explanation is given as to a solid-state image pickup device which allows output timings of the selection signals SHT(1) to SHT(m) not only to be in synchronization with the clock signals CLK1 and CLK2, but also to be arbitrarily set, thereby allowing a signal accumulation period to be set with more flexibility. In other words, the second embodiment describes an invention relating to an improvement of a multiplexer circuit for solving a problem as to a horizontal bright strip (bleached strip) that may appear in the lower part of an image when the multiplexer circuit shown in
The multiplexer circuit 117 is composed of a plurality ((m−2) in
In addition to the function of the unit selection circuit 117, each unit selection circuit 118a is further composed of: a switch that electrically separates one of the selection signal SHT(i) and the selection signal READ(i) when these selection signals become High level at the same time; and a ground circuit that inputs Low level instead of the separated selection signal. These additional functions are provided in order to solve the above-stated problem as to the bleached strip.
The bootstrap circuit for the selection signal READ(i) includes: a transistor Tr1E-U for controlling the input of the selection signal READ(i); a transistor Tr2E-U for holding a level of the inputted selection signal; and a transistor Tr3E-U which is of an enhancement type used as a boost capacity. Meanwhile, the bootstrap circuit for the selection signal SHT(i) is similarly composed of transistors Tr1E-L, Tr2E-L, and Tr3E-L. With this construction, the transistors Tr2E-L and Tr3E-L function as an output circuit for outputting the selection signal SHT(i) to a signal line Transout in synchronization with the drive signal ETrans. The transistors Tr2E-U and Tr3E-U function as an output circuit for outputting the selection signal READ(i) to the signal line Transout in synchronization with the drive signal Trans.
Since no dummy pulse is inputted to the unit selection circuit 117a, one of SHT(i) and READ(i) is High level and the other is Low level as shown in
Next, before the construction of the unit selection circuit 118a is described, a detailed explanation is given with reference to
This short circuit brings not only the selection signal Transout outputted from the unit selection circuit in
With the Middle-level selection signal Transout, the electronic shutter operation cannot be completely performed. To be more specific, when the Middle-level selection signal Transout is supplied to the readout signal line 207 shown in
In the diagram: READ(1) to READ(m) are m number of selection signals for readout that are outputted from the shift register 111; SHT(1) to SHT(m) are m number of selection signals for the electronic shutter that are outputted from the shift register 112; and Transout(1) to Transout(m) are m number of selection signals outputted from the unit register 117a. Note that a period of time measured from a time t(1−a) to a time t(2−a) is a first frame period, a period of time measured from the time t(2−a) to a time t(3−a) is a second frame period, and so on. Also note that a period of time measured from SHT(1) to READ(1) is an exposure time (release time) of the electronic shutter.
This diagram shows a case where the exposure time is a time T1 until the first frame period and is changed from the time T1 to a time T2 in the second frame period.
With attention being focused: on the electronic shutter operation, the shift register 112 shifts out SHT(1) to SHT(m) sequentially by the application of the start signal SHT (indicated as the start signal “START” in
Immediately before the third frame period (about the time T1 prior to the time t(2−a)), the shift register 112 stops outputting the dummy pulse by the application of the start signal SHT. In other words, the start signal SHT resets the unit registers REG(m−1) and REG(m) of the shift register 112.
Since the exposure time is changed from T1 to T2 in the second frame period, the start signal SHT is applied to the shift register 112 immediately before the second frame period (about the time T2 prior to the time t(3−a), that is, at the time t(2−b)). This start signal SHT resets the unit registers REG(m−1) and REG(m). At this point in time, however, the pulse has yet to reach the unit register REG(m−1). Moreover, immediately after the pulse reached the unit register REG(m), each of the unit registers REG(m−1) and REG(m) emit the dummy pulse. This dummy pulse is kept outputted until the start signal SHT is applied in the next third frame period after the blanking period in the second frame period (from the time t(2−c) to the time t(3−a)).
There is a possibility that both the dummy pulse of READ(m) and the dummy pulse of SHT(m) become High level at the same time during the blanking period in the second frame period. There is also a possibility that both the dummy pulse of READ(m−1) and the dummy pulse of SHT(m−1) become High level at the same time.
In
This Middle-level drive signal ETrans is inputted to all of the unit selection circuits 117a. Thus, the selection signals SHT(7), SHT(8), and SHT(9) respectively outputted from the 7th, 8th, and 9th unit selection circuits 117a which are shifting the pulses during the blanking period are all driven by the Middle-level drive signal ETrans, thereby making the selection signals Transout(7) to Transout(9) become Middle level. As a result, the shutter operation for the pixels belonging to the 7th, 8th, and 9th lines are performed incompletely, and this appears as a bleached strip on the image.
In this way, there is a problem where a bleached strip occurs to the image in the case where the solid-state image pickup device of
Next, an explanation is given as to a construction of the unit selection circuit 118a that prevents a bleached strip from occurring.
As shown in
The inverter Inv1 and the transistor Tr4 electrically separate the input signal line of the selection signal SHT(m) from the unit selection circuit 118a, by an Off state of the transistor Tr4 when the selection signal READ(m) is High level. In this case, the transistor Tr4 functions as a cutoff switch. When the selection signal READ(m) is Low level, the transistor Tr4 is in the On state.
When the selection signal READ(m) is High level, the transistor Tr5 becomes the On state. By this On state of the transistor Tr5, the inverter Inv2 and the transistor Tr5 pull down the gate of the transistor Tr2E-L to Low level so as to forcefully bring the transistor Tr2E-L into the Off state. In this way, the inverters Inv1 and Inv2 and the transistor Tr5 function as a stop circuit for forcefully stopping the operations of the transistor Tr2E-L and the transistor Tr3E-L. With this, the Transout signal line and the Etrans signal line connected to each other via the transistor Tr2E-L are electrically separated. When the selection signal READ(m) is Low level, the transistor Tr5 does not forcefully bring the transistor Tr2E-L into the Off state.
When the pulse of the drive signal ETrans is inputted in this state, a pulse is outputted to the selection signal Transout in synchronization with the pulse of the drive signal ETrans as with the case shown in
Moreover, when the selection signal READ(m) and the selection signal SHT(m) are Low level, each of the transistors Tr2E-U and Tr2E-L is in the Off state, meaning that the selection signal Transout is Low level.
When the pulse of the drive signal ETrans is inputted in this state, the selection signal Transout receives no influence since the transistor Tr2E-L is in the Off state. When the drive signal Trans is Low level, the selection signal Transout outputs Low level. Also, when the drive signal Trans is inputted as a pulse, the selection signal Transout outputs the pulse.
As described so far, when the selection signal READ(m) is Low level, the unit selection circuit 118a performs the same operation that is performed by the unit selection circuit shown in
As described so far, the solid-state image pickup device according to the present embodiment prevents the drive signals Trans and ETrans from shorting out when the selection signals READ(m) and SHT(m) are both High level, thereby eliminating a malfunction where the drive signals Trans and ETrans become Low level and thus solving the problem as to a horizontal bleached strip appearing in the lower part of an image that degrades the image quality. Accordingly, the timing of the electronic shutter can be arbitrarily set within one horizontal scanning period, and the image quality can be prevented from degrading. Moreover, the number of the unit selection circuits 118a only needs to correspond to the number of the unit registers that generate the dummy pulses. This means that an increase in the circuit size and, by extension, an increase in the chip size, can be small. In particular, since the unit selection circuits 118a can be set using free space of the top and bottom inside the chip, a circuit layout in the chip can be smaller as compared to the conventional one.
It should be noted here that in the unit selection circuit 118a shown in
As a solid-state image pickup device that prevents noise occurrence caused by an electronic shutter operation and thus obtains a high-quality image, the solid-state image pickup device of the present invention can be applied to a digital still camera, a mobile camera, and the like, and is especially useful.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-048021 | Feb 2005 | JP | national |
| 2005-320188 | Nov 2005 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2006/302721 | 2/16/2006 | WO | 00 | 8/21/2007 |
