Claims
- 1. An MOS-type solid-state imaging apparatus comprising:
unit cells arranged in an array; means for selecting one of the unit cells; selection lines connected between said selecting means and said unit cells of each row; and vertical signal lines to which outputs from said unit cells in each column are supplied, wherein each of said unit cells comprises:
a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photoelectric conversion portion is supplied, a source connected to said vertical signal line, and a drain connected to said selection line; an address capacitor connected between the gate of said amplification transistor and said selection line; and a reset transistor connected in parallel with said address capacitor.
- 2. An MOS-type solid-state imaging apparatus according to claim 1, further comprising a transfer gate circuit connected between said photoelectric conversion portion and the gate of said amplification transistor.
- 3. An MOS-type solid-state imaging apparatus according to claim 1, further comprising means for compensating for variations in amplification characteristics of the amplification transistors of said unit cells.
- 4. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a noise canceler for subtracting a noise component from an output from said unit cell.
- 5. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a noise canceler for subtracting a charge representing a noise component from a charge representing an output from said unit cell.
- 6. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 7. An MOS-type solid-state imaging apparatus according to claim 6, in which said sample/hold capacitor and said clamp capacitor are stacked on each other.
- 8. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 9. An MOS-type solid-state imaging apparatus according to claim 8, in which said compensation means comprises correction means for reducing a difference between impedances of said clamp capacitor in ON and OFF periods.
- 10. An MOS-type solid-state imaging apparatus according to claim 9, in which said correction means comprises a correction capacitor for increasing a capacitance of said clamp capacitor when said clamp transistor is off.
- 11. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 12. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a slice transistor having a gate to which an output signal from said unit cell is supplied, a slice capacitance and a slice reset transistor which are connected to a source of said slice transistor, and a slice charge transfer capacitor and a drain reset transistor which are connected to a drain of said slice transistor.
- 13. An MOS-type solid-state imaging apparatus according to claim 3, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 14. An MOS-type solid-state imaging apparatus comprising:
unit cells arranged in an array; means for selecting one of the unit cells; selection lines connected between said selecting means and said unit cells of each row; and vertical signal lines to which outputs from said unit cells in each column are supplied, wherein each of said unit cells comprises:
a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photoelectric conversion portion is supplied, a source connected to said vertical signal line, and a drain connected to said selection line; and a reset transistor connected between the gate of said amplification transistor and said selection line, and wherein said amplification transistor has a short channel effect that when a selection voltage is applied to said selection line, a channel potential under the gate changes to a voltage not less than a signal voltage of said photoelectric conversion portion.
- 15. An MOS-type solid-state imaging apparatus according to claim 14, further comprising a transfer gate circuit connected between said photoelectric conversion portion and the gate of said amplification transistor.
- 16. An MOS-type solid-state imaging apparatus according to claim 14, further comprising means for compensating for variations in amplification characteristics of the amplification transistors of said unit cells.
- 17. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a noise canceler for subtracting a noise component from an output from said unit cell.
- 18. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a noise canceler for subtracting a charge representing a noise component from a charge representing an output from said unit cell.
- 19. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 20. An MOS-type solid-state imaging apparatus according to claim 19, in which said sample hold capacitance and said clamp capacitor are stacked on each other.
- 21. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 22. An MOS-type solid-state imaging apparatus according to claim 21, in which said compensation means comprises correction means for reducing a difference between impedances of said clamp capacitor in ON and OFF periods.
- 23. An MOS-type solid-state imaging apparatus according to claim 22, in which said correction means comprises a correction capacitor for increasing a capacitance of said clamp capacitor when said clamp transistor is off.
- 24. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 25. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a slice transistor having a gate to which an output signal from said unit cell is supplied, a slice capacitor and a slice reset transistor which are connected to a source of said slice transistor, and a slice charge transfer capacitor and a drain reset transistor which are connected to a drain of said slice transistor.
- 26. An MOS-type solid-state imaging apparatus according to claim 16, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 27. An MOS-type solid-state imaging apparatus comprising:
unit cells arranged in an array; means for selecting one of the unit cells; selection lines connected between said selecting means and said unit cells of each row; and vertical signal lines to which outputs from said unit cells in each column are supplied, wherein each of said unit cells comprises:
a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photoelectric conversion portion is supplied, a source connected to said vertical signal line, and a drain connected to said selection line; and a reset transistor connected between the gate of said amplification transistor and said selection line, and wherein a switch circuit which is turned on by said selecting means is connected between said selecting means and said selection line.
- 28. An MOS-type solid-state imaging apparatus according to claim 27, further comprising a transfer gate circuit connected between said photoelectric conversion portion and the gate of said amplification transistor.
- 29. An MOS-type solid-state imaging apparatus according to claim 27, further comprising means for compensating for variations in amplification characteristics of the amplification transistors of said many unit cells.
- 30. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a noise canceler for subtracting a noise component from an output from said unit cell.
- 31. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a noise canceler for subtracting a charge representing a noise component from a charge representing an output from said unit cell.
- 32. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 33. An MOS-type solid-state imaging apparatus according to claim 32, in which said sample/hold capacitor and said clamp capacitor are stacked on each other.
- 34. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 35. An MOS-type solid-state imaging apparatus according to claim 34, in which said compensation means comprises correction means for reducing a difference between impedances of said clamp capacitor in ON and OFF periods.
- 36. An MOS-type solid-state imaging apparatus according to claim 35, in which said correction means comprises a correction capacitor for increasing a capacitance of said clamp capacitor when said clamp transistor is off.
- 37. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 38. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a slice transistor having a gate to which an output signal from said unit cell is supplied, a slice capacitor and a slice reset transistor which are connected to a source of said slice transistor, and a slice charge transfer capacitor and a drain reset transistor which are connected to a drain of said slice transistor.
- 39. An MOS-type solid-state imaging apparatus according to claim 29, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 40. An MOS-type solid-state imaging apparatus comprising:
unit cells arranged in an array; means for selecting one of the unit cells; selection lines connected between said selecting means and said unit cells of each row; and vertical signal lines to which outputs from said unit cells in each column are supplied, wherein each of said unit cells comprises:
a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photoelectric conversion portion is supplied, a source connected to said vertical signal line, and a drain connected to said selection line; and an address capacitor connected between the gate of said amplification transistor and said selection line, and wherein a negative pulse is applied to said selection line to forward-bias said photoelectric conversion portion through said address capacitor so as to discharge a signal charge from said photoelectric conversion portion.
- 41. An MOS-type solid-state imaging apparatus according to claim 40, further comprising a transfer gate circuit connected between said photoelectric conversion portion and the gate of said amplification transistor.
- 42. An MOS-type solid-state imaging apparatus according to claim 40, further comprising means for compensating for variations in amplification characteristics of the amplification transistors of said many unit cells.
- 43. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a noise canceler for subtracting a noise component from an output from said unit cell.
- 44. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a noise canceler for subtracting a charge representing a noise component from a charge representing an output from said unit cell.
- 45. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 46. An MOS-type solid-state imaging apparatus according to claim 45, in which said sample/hold capacitor and said clamp capacitor are stacked on each other.
- 47. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 48. An MOS-type solid-state imaging apparatus according to claim 47, in which said compensation means comprises correction means for reducing a difference between impedances of said clamp capacitor in ON and OFF periods.
- 49. An MOS-type solid-state imaging apparatus according to claim 48, in which said correction means comprises a correction capacitor for increasing a capacitance of said clamp capacitor when said clamp transistor is off.
- 50. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a source follower circuit to which an output signal from said unit cell is supplied, a sample/hold capacitor to which an output signal from said source follower circuit is supplied through a clamp capacitor and a sample/hold transistor, and a clamp transistor connected to a connection point between said clamp capacitor and said sample/hold transistor to turn on/off said clamp capacitor.
- 51. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a slice transistor having a gate to which an output signal from said unit cell is supplied, a slice capacitor and a slice reset transistor which are connected to a source of said slice transistor, and a slice charge transfer capacitor and a drain reset transistor which are connected to a drain of said slice transistor.
- 52. An MOS-type solid-state imaging apparatus according to claim 42, in which said compensation means comprises a sample/hold capacitor to which an output signal from said unit cell is supplied through a sample/hold transistor and a clamp capacitor, and a sample/hold transistor connected to a connection point between said sample/hold capacitor and said clamp capacitor to turn on/off the connection point.
- 53. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate; vertical address lines arranged in a row direction of said imaging region to select a row to be addressed; vertical signal lines arranged in a column direction of said imaging region to read out signals from said unit cells; load transistors each connected to one end of each of said vertical signal lines; and horizontal selection transistors each connected to the other end of each of said vertical signal lines, wherein said unit cell comprises:
a photodiode serving as the photoelectric conversion portion; an amplification transistor having a gate to which an output from said photodiode is supplied, and a source and a drain respectively connected to said vertical signal line and said vertical address line; an address capacitor connected between the gate of said amplification transistor and said vertical address line; and a reset transistor connected in parallel with said address capacitor.
- 54. An MOS-type solid-state imaging apparatus according to claim 53, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 55. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells on a semiconductor substrate, each of said unit cells comprising a photodiode, an amplification transistor having a gate to which an output from said photodiode is supplied, address means for activating said amplification transistor, and reset means for discharging a signal from said photodiode; vertical address lines arranged in a row direction of said imaging region; a vertical shift register for driving said vertical address lines; vertical signal lines arranged in a column direction in which currents are read out from said amplification transistors; load transistors each connected to one end of each of said vertical signal lines; horizontal selection transistors each connected to the other end of each of said vertical signal lines; a horizontal selection shift register for sequentially applying selection pulse signals to gates of said horizontal selection transistors; and a horizontal signal line for reading out a signal current from said vertical signal line through said horizontal selection transistor, wherein a source and a drain of said amplification transistor are respectively connected to said vertical signal line and said vertical address line, an address capacitor is connected between said vertical address line and the gate of said amplification transistor, and a reset transistor is connected in parallel with said address capacitor.
- 56. An MOS-type solid-state imaging apparatus according to claim 55, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 57. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells serving as photodiodes on a semiconductor substrate; vertical address lines arranged in a row direction of said imaging region to select a row to be addressed; vertical signal lines arranged in a column direction of said imaging region to read out signals from said unit cells; load transistors each connected to one end of each of said vertical signal lines; and horizontal selection transistors each connected to the other end of each of said vertical signal lines, wherein said unit cell comprises:
a photodiode serving as a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photodiode is supplied, and a source and a drain respectively connected to said vertical signal line and said vertical address line; and a reset transistor connected between the gate of said amplification transistor and said vertical address line, and wherein said amplification transistor has a short channel effect that when an address voltage is applied to said vertical address line, a channel potential under the gate changes to a voltage not less than a signal voltage of said photodiode.
- 58. An MOS-type solid-state imaging apparatus according to claim 57, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 59. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells on a semiconductor substrate, each of said unit cells comprising a photodiode, an amplification transistor having a gate to which an output from said photodiode is supplied, address means for activating said amplification transistor, and reset means for discharging a signal from said photodiode; vertical address lines arranged in a row direction of said imaging region; a vertical shift register for driving said vertical address lines; vertical signal lines arranged in a column direction in which currents are read out from said amplification transistors; load transistors each connected to one end of each of said vertical signal lines; horizontal selection transistors each connected to the other end of each of said vertical signal lines; a horizontal selection shift register for sequentially applying selection pulse signals to gates of said horizontal selection transistors; and a horizontal signal line for reading out signal currents from said vertical signal lines through said horizontal selection transistors, wherein a source and a drain of said amplification transistor are respectively connected to said vertical signal line and said vertical address line, a reset transistor is connected between said vertical address line and the gate of said amplification transistor, and said amplification transistor has a short channel effect that when an address voltage is applied to said vertical address line, a channel potential under the gate changes to a voltage not less than a signal voltage of said photodiode.
- 60. An MOS-type solid-state imaging apparatus according-to claim 59, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 61. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells on a semiconductor substrate, each of said unit cells comprising a photodiode, an amplification transistor having a gate to which an output from said photodiode is supplied, and reset means for discharging a signal from said photodiode; vertical address lines arranged in a row direction of said imaging region; a vertical shift register for selecting cells in a row which is to be addressed; vertical signal lines arranged in a column direction in which currents in said amplification transistors are read out; load transistors each connected to one end of each of said vertical signal lines; horizontal selection transistors each connected to the other end of each of said vertical signal lines; a horizontal selection shift register for sequentially supplying selection pulse signals to said horizontal selection transistors; and a horizontal signal line for reading out signal currents from said vertical signal line through said horizontal selection transistors, wherein a source and a drain of said amplification transistor are respectively connected to said vertical signal line and said vertical address line, and said vertical address line is connected to an address power supply through a switch circuit which is turned on by an output from said vertical shift register.
- 62. An MOS-type solid-state imaging apparatus according to claim 61, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 63. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions, in the form of a matrix, on a semiconductor substrate; vertical address lines arranged in a row direction of said imaging region to select a row to be addressed; vertical signal lines arranged in a column direction of said imaging region to read out signals from said unit cells; load transistors each connected to one end of each of said vertical signal lines; and horizontal selection transistors each connected to the other end of each of said vertical signal lines, wherein said unit cell comprises:
a photodiode serving as a photoelectric conversion portion; an amplification transistor having a gate to which an output from said photodiode is supplied, and a source and a drain respectively connected to said vertical signal line and said vertical address line; and an address capacitor connected between the gate of said amplification transistor and said vertical address line, and wherein a negative pulse is applied to said vertical address line to forward-bias said photoelectric conversion portion through said address capacitor, thereby discharging a signal charge from said photodiode into said semiconductor substrate.
- 64. An MOS-type solid-state imaging apparatus according to claim 63, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
- 65. An MOS-type solid-state imaging apparatus comprising:
an imaging region formed by two-dimensionally arranging unit cells on a semiconductor substrate, each of said unit cells comprising a photodiode, an amplification transistor having a gate to which an output from said photodiode is supplied, address means for activating said amplification transistor, and reset means for discharging a signal from said photodiode; vertical address lines arranged in a row direction of said imaging region; a vertical shift register for driving said vertical address lines; vertical signal lines arranged in a column direction in which currents are read out from said amplification transistors; load transistors each connected to one end of each of said vertical signal lines; horizontal selection transistors each connected to the other end of each of said vertical signal lines; a horizontal selection shift register for sequentially applying selection pulse signals to gates of said horizontal selection transistors; and a horizontal signal line for reading out signal currents from said vertical signal lines through said horizontal selection transistors, wherein a cell structure is formed such that a source and a drain of said amplification transistor are respectively connected to said vertical signal line and said vertical address line, an address capacitor is connected between said vertical address line and the gate of said amplification transistor, and a negative pulse is applied to said vertical address line to forward-bias said photodiode through said address capacitor, thereby discharging a signal charge from said photodiode into said semiconductor substrate.
- 66. An MOS-type solid-state imaging apparatus according to claim 65, in which a transfer transistor is connected between said photodiode and the gate of said amplification transistor.
Priority Claims (4)
Number |
Date |
Country |
Kind |
7-206140 |
Aug 1995 |
JP |
|
7-206143 |
Aug 1995 |
JP |
|
7-206144 |
Aug 1995 |
JP |
|
8-059845 |
Mar 1996 |
JP |
|
CROSS-REFERENCE TO THE RELATED APPLICATIONS
[0001] This is a continuation application of Application No. PCT/JP96/02280, filed Aug. 12, 1996, now abandoned.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09022124 |
Feb 1998 |
US |
Child |
09733917 |
Mar 2001 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/JP96/02280 |
Aug 1996 |
US |
Child |
09022124 |
Feb 1998 |
US |