Patent Application
20080094124
The invention is described further hereinafter by way of example only with reference to the accompanying drawings in which:
a and 3b comprise experimental traces obtained from a power MOSFET without and with the reverse recovery enhancement respectively.
Turning first to
In the illustration of the MOSFET device 10 there is shown a MOSFET 12 having a gate arranged to receive a gate drive signal 14 by way of a gate impedance 16 which is provided in accordance with the present invention.
Also illustrated is an operating power supply 20 and associated load 18 connected between the supply 20 and the drain of the MOSFET 12.
As with all MOSFETs, there is a drain-gate capacitance, which is represented by a capacitor 24 within
It is known that a body diode current will flow under certain conditions when the load 18 is reactive.
In accordance with the present invention, it is proposed that a bias voltage be applied to the gate of the MOSFET 12 selectively during the reverse recovery within the body diode 22 so as to improve the characteristics thereof.
One particularly advantageous manner of generating the required bias voltage is by way of an impedance 16 as illustrated in
The impedance 16 is positioned within the gate path of the device to the MOSFET 12.
A positive-going voltage appears on the MOSFET 12 drain when the body diode 22 current reaches zero and it then becomes reversed biased. This generates a current through the drain-gate capacitor 24, which serves to produce a corresponding voltage across the gate impedance 16. The raised gate potential arising in view of the voltage now arising across the impedance 16 serves to effectively soften the reverse recovery transients arising within the body diode.
The nature of the gate impedance 16 has to be selected carefully in order to optimise performance within the MOSFET 12. Ideally, the gate voltage must not be allowed to dwell at voltages near the threshold level for periods greater than that necessary to improve the reverse recovery transient or substantial channel currents may flow. This could incur unnecessary power losses.
It is found that, preferably, a bias voltage applied at the gate at a level somewhere between the source potential and the gate-source threshold voltage level during the reverse recovery event is particularly beneficial.
The use of a gate impedance 16 to provide the required bias voltage at the gate of the MOSFET 12 is further advantageous in that since the current flow from the drain-gate capacitance 24 into the gate impedance 16 is inherently transient by nature of the capacitive coupling, the resulting increase in gate voltage arising across the gate impedance 16 is similarly transient.
Selective application of the said bias gate voltage during reverse recovery within the body diode 22 therefore can be achieved somewhat automatically. Further self limitation within the device also occurs since the formation of a channel within the MOSFET 12 would support a drain-source current that would serve to oppose the rate of change of voltage with time that is causing the gate bias.
Of course, to maintain normal operation during MOSFET switching events, current must be allowed to flow freely between the gate drive 14 and the gate of the MOSFET 12 to control conduction of the channel of the MOSFET 12. The gate impedance 16 therefore must not present a significant limitation to the gate current during the MOSFET switching events if the switching speed capability of the device is to be maintained.
The present invention identifies that there are various ways to implement a suitable gate impedance 16 as illustrated in
One particular embodiment is illustrated within
As will be seen, the gate impedance 16 comprises series connected parallel diode chains of which two 26, 28 are shown. Each diode will present a well defined forward voltage drop and the characteristics therefore will also change with temperature in the same way as the MOSFET gate-source threshold voltage will change.
Thus, a degree of self-adjustment having regard to thermal effects advantageously arises within this embodiment of the present invention.
The diode chain 26, 28 may be integrated into the MOSFET structure.
One particular advantage of integrating the diode chain 26, 28 within the semiconductor is that the inductances of the interconnections can be minimised and thermal tracking between the MOSFET 12 and the diode 26, 28 will then be very close.
Of course, as an alternative, different configurations of diodes can be provided and the gate impedance could include integrated resistors within the semiconductor, which can advantageously be formed of polysilicon, or indeed a resistor-diode combination.
Remaining with
With a small positive gate bias in accordance with the present invention, electrons start to accumulate along the interface between the gate oxide and the semiconductor but such electrons do not accumulate in sufficient quantities to form a significant channel.
When the device body diode 22 is active, the small positive gate bias tends to reduce the area of the zone available for the recombination of holes and electrons at the p-n junction.
Then, the drain-source capacitance 24 becomes effective when a depletion zone forms at the instant of bias polarity reversal across the body diode junction 22.
The overall effect of the small positive bias applied to the gate in accordance with the present invention is to limit the rate at which the drain-source capacitor charges and hence also the rate at which the voltage across the device and current through the device vary with time. This in turn serves to limit consequent electromagnetic noise generation.
Turning now to
a shows the resulting traces without the reverse recovery enhancement of the present invention, while
The clear lengthening of the settling time of the reverse recovery current “undershoot” together with the minimal voltage overshoot and “ringing” without reducing the dl/dt in the device illustrate the benefits of this technique.
The present invention finds ready and advantageous use as a means for controlling so-called third quadrant effect so as to enhance the reverse recovery behaviour.
In further detail, if the MOSFET gate voltage is maintained at a small positive voltage below the threshold level while it is conducting in the reverse direction, i.e. with the body diode in the forward conduction direction, this creates the conditions where reverse recovery charge is reduced due to the ‘Third Quadrant’ (Q3) effect. This is advantageous as it reduces reverse recovery current and therefore power loss.
If this small positive gate bias voltage can be maintained up to the point where the polarity of the current in the MOSFET body diode is at the point of reversing i.e. recovering, the magnitude of the subsequent current in the first quadrant (Q1) can be reduced to such small levels that as there is very little reverse recovery current associated with diode conduction. Importantly, the positive gate bias should be reduced at the correct time to avoid the possibility of Q1 channel current flow resulting in shoot through in MOSFET forward bias conditions. Timing is critical to guarantee optimum operation under all conditions.
The incorporation of the diode structure within the MOSFET structure as described above, together with the inherent MOSFET drain-gate capacitance, produces an automatically timed and limited gate voltage pulse at the instant of body diode reverse recovery dl/dt reversal. This has the effect of permitting a small controlled momentary channel current flow that actively limits drain voltage dV/dt and overshoot and therefore reduces ‘gate bounce’.
As will be appreciated by one skilled in the art, various changes and modifications may be made to the described embodiments, and the present invention may be utilized in may different forms. For example, the biasing diode device may be external or may be integrated within the MOSFET chip, or indeed within the MOSFET driver.
In summary, it should be appreciated that the improvement in the reverse recovery transients is largely independent of body diode current and supply voltage. The use of integrated polysilicon diodes is considered to be a particularly beneficial factor since a relatively short physical connection to the gate can be achieved and can be formed by part of the metalization on the surface of the silicon. As a result, the integrated diodes will exhibit a very low inductance. Also, no further wire bond pads would be needed with such an arrangement.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0416882.9 | Jul 2004 | EP | regional |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB05/52538 | 7/28/2005 | WO | 00 | 1/29/2007 |
