Patent Application
20250241003
This application claims priority to French Application No. 2400490, filed on Jan. 18, 2024, which application is hereby incorporated herein by reference.
The present disclosure generally concerns electronic components and more particularly field-effect transistors of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type.
MOSFET-type transistors are field-effect transistors comprising an electrically-conductive gate, which is electrically insulated from a semiconductor substrate by a dielectric layer called gate insulator.
Various MOSFET transistor designs have already been provided.
It would be desirable to at least partly overcome certain disadvantages of known MOSFET transistor designs.
The improvement of the electrical performance of MOSFET transistors, for example for applications in radio frequency (RF) signal switching, advanced analog, embedded non-volatile memories.
An embodiment overcomes all or part of the disadvantages of known MOSFET transistors.
An embodiment provides a transistor comprising a drain region and a source region in a semiconductor layer, a channel-forming region extending in a first direction between the drain region and the source region, and a gate structure topping the channel-forming region and comprising a gate insulator topped with a gate region insulated from said channel-forming region by said gate insulator; the channel-forming region comprising a first channel region having a first length in the first direction and being an epitaxial region, and a second channel region in the semiconductor layer, the first channel region being between the second channel region and the gate structure; and the gate insulator comprising first portions having a first thickness on either side of the first channel region, and a second portion of a second thickness on the first channel region, the second thickness being smaller than the first thickness.
According to an embodiment, the second portion is positioned between the first portions in the first direction.
According to an embodiment, the transistor further comprises a lightly-doped drain region in the semiconductor layer, between the second channel region and each of the drain and source regions.
An embodiment provides a method of manufacturing a transistor, the method comprising: forming a first layer of insulator having a third thickness on a semiconductor layer; forming an opening in the first insulator layer, said opening having a first length in a first direction; forming, by epitaxy in the opening, a first channel region of a channel-forming region; forming a second insulator layer having a second thickness on at least the first channel region; the portions of the first insulator layer that remain on either side of the opening forming first portions of a gate insulator, said first portions having a first thickness greater than or equal to the third thickness, and greater than the second thickness, and the portion of the second insulator layer topping the first channel region forming a second portion of the gate insulator; forming a gate region on the gate insulator; and forming a drain region and a source region in the semiconductor layer, a second channel region of the channel-forming region extending in the first direction between the drain region and the source region.
According to an embodiment, the method further comprises forming, in the semiconductor layer, a lightly-doped drain region between the second channel region and each of the drain and source regions.
According to an embodiment, forming the opening comprises etching the first insulator layer throughout the third thickness and along the first length in the first direction, the etching stopping at the semiconductor layer, the etching being, for example, a wet etching.
According to an embodiment, the first thickness is substantially equal to the third thickness.
The following embodiments can apply to the transistor and to the transistor manufacturing method.
According to an embodiment, the first thickness is in the range from 5 to 10 nm, for example from 6 to 9 nm, and the second thickness is in the range from 1 to 4.5 nm, for example from 2 to 4 nm.
According to an embodiment, the gate region has a second length in the first direction, the first length being smaller than the second length.
According to an embodiment, the gate region extends above and on either side of the first channel region in the first direction.
According to a specific embodiment, the gate region is centered with respect to the first channel region.
According to an embodiment, a non-zero distance separates a side wall of the gate region and the second gate insulator portion, for example the distance being in the range from 70 to 100 nm, or from 80 to 90 nm.
According to an embodiment, the distance is greater than an overlap length of the lightly-doped drain region under the gate region.
According to an embodiment, the first epitaxial channel region is made of silicon.
According to another embodiment, the first epitaxial channel region is made of a silicon-germanium alloy.
According to an embodiment, the gate insulator is made of a silicon oxide, for example of silicon dioxide, and/or the semiconductor layer is made of silicon.
An embodiment provides an electronic device comprising at least one transistor such as described hereinabove.
An embodiment provides a radio frequency switch comprising at least one transistor such as described hereinabove.
The foregoing features and advantages, as well as others, will be described in detail in the rest of the disclosure of specific embodiments given as an illustration and not limitation with reference to the accompanying drawings, in which:
Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are described in detail. In particular, the steps of the MOSFET transistor manufacturing method have not all been described, as they can be carried out with current methods of microelectronics. Similarly, the details of MOSFET transistors have not all been described. Further, the applications that the described transistors may have not all been detailed.
Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
In the following description, where reference is made to absolute position qualifiers, such as “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative position qualifiers, such as “top”, “bottom”, “upper”, “lower”, etc., or orientation qualifiers, such as “horizontal”, “vertical”, etc., reference is made unless otherwise specified to the orientation of the drawings.
Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “in the order of” signify plus or minus 10%, preferably of plus or minus 5%.
In the following description, a length corresponds to a dimension in a first lateral direction of a MOSFET transistor (direction X indicated in the drawings), corresponding to a direction parallel to the conduction direction of the transistor, a width corresponds to a dimension in a second lateral direction (direction Y indicated in the drawings), orthogonal to the first direction, and a thickness or depth corresponds to a dimension in a third direction perpendicular to the first and second directions (vertical direction Z indicated in the figures). Thus, the dimension, along the X direction, of a channel-forming region of the transistor is referred to as the transistor channel length, substantially corresponding to the distance between a source region and a drain region of the transistor.
In the following description, in order to make it lighter, a MOSFET may be designated as a transistor.
The transistors shown in the following description are, for example, N-channel MOS transistors (NMOS), that is, transistors having N-type doped source and drain regions, for example, doped with arsenic or phosphorus atoms, while the body region is P-type doped, for example doped with boron atoms.
As a variant, the transistors shown may be P-channel MOS transistors (PMOS), that is, transistors having P-type doped source and drain regions, for example doped with boron atoms, while the body region is N-type doped, for example doped with arsenic or phosphorus atoms.
MOSFET transistor 100 is formed inside and on top of a semiconductor layer 120. The electronic device comprises a buried insulator layer 110, under semiconductor layer 120. Layers 110 and 120 correspond, for example, to a stack of SOI (Semiconductor On Insulator) type, the electronic device then comprising a substrate in contact with and under buried insulator layer 110 (substrate not shown). Semiconductor layer 120 is, for example, on top of and in contact with buried insulator layer 110.
Semiconductor layer 120 is for example made of silicon, for example of single-crystal silicon, and buried insulator layer 110 is for example made of silicon dioxide (SiO2).
Transistor 100 comprises a drain region 121 and a source region 122 formed in a region of semiconductor layer 120 called body region 123.
An upper portion 124 of body region 123, between drain region 121 and source region 122, forms the channel-forming region 124 of transistor 100, or “channel region”. As an example, drain region 121, source region 122, and body region 123 are flush with the upper surface of semiconductor layer 120.
Transistor 100 further comprises a gate structure 130 located above body region 123, preferably above channel region 124. Gate structure 130 generally comprises a conductive gate region 132, which for example comprises polysilicon and/or metal, and an insulator layer 131, called gate insulator, which insulates gate region 132 from semiconductor layer 120.
For example, gate region 132 has a length CD greater than or equal to 50 nm, or even greater than or equal to 100 nm.
For example, gate insulator 131 is made of silicon dioxide (SiO2).
For example, gate insulator 131 has a thickness in the range from approximately 1 nm to 10 nm. The gate insulator may have a thickness in the range from approximately 1 to 4.5 nm for a transistor called GO1 (“Gate Oxide 1”), that is, a transistor having a gate insulator of small thickness, or a thickness of in the range from approximately 5 to 10 nm, or even from approximately 5 to 7.5 nm, for a transistor GO2 (“Gate Oxide 2”), that is, a transistor having a gate insulator of strong thickness.
As an example, in
Gate region 132 may be topped with a conductive contact layer 133, which may be made of silicide. The drain region and the source region may also each be topped with a conductive contact layer 126, which may be made of silicide, which for example enables to decrease the access resistance.
On either side of gate region 132, on portions of semiconductor layer 120 not covered with this gate region and on the side walls (flanks) of gate region 132, transistor 100 generally comprises a thin protective oxide layer 134, for example a SiO2 layer. The thickness of thin oxide layer 134 is, for example, in the range from 2 to 10 nm, or even from 2 to 5 nm.
Further, transistor 100 comprises insulating spacers 135 which coat the flanks of gate region 132 covered by thin oxide layer 134 and which extend over the portions of semiconductor layer 120 covered by this thin oxide layer 134. Each insulating spacer 135 is, for example, made of a silicon nitride (SiN).
Extension regions 125, or LDD (Lightly Doped Drain) regions, having a doping slightly lighter than the doping of the drain and source regions, may be formed at each junction between channel region 124 and drain 121 and source 122 regions, for example to limit the lateral electric field in the MOS transistor.
LDD regions 125, and sometimes drain 121 and source 122 regions, generally exhibit an overlap under gate region 132. Indeed, during the doping operation to form LDD regions 125, or even to form the drain 121 and source 122 regions, the dopant may diffuse over a certain length under the gate region. This overlap is represented in
Although not shown in
In certain applications, it is searched for a better control of overlap capacitances, which can be designated by the term “Miller capacitances”. It may be searched for the decrease of these capacitances, in particular to avoid too large a dispersion in the performance of MOSFET transistors. A solution to decrease Miller capacitances is to increase the gate insulator thickness. However, thereby, this may result, all other things being equal, in increasing in the threshold voltage of the transistor, and in degrading certain performances of the transistor, for example its switching speed.
The inventors provide a MOSFET transistor enabling to meet the above-described improvement needs, and to overcome all or part of the disadvantages of the above-described MOSFET transistors. In particular, the inventors provide a MOSFET transistor which enables to decrease the overlap capacitances, or Miller capacitances, without for all this degrading the transistor performance, in particular without increasing the threshold voltage of the transistor. It would be desirable to have such a MOSFET transistor without complicating the transistor manufacturing method. It would be advantageous for the embodiments not to require decreasing the effective length of the channel-forming region.
Embodiments of MOSFET transistor will be described below. The described embodiments are non-limiting and various variants will occur to those skilled in the art based on the indications of the present disclosure.
The MOSFET transistor 200 of
The second channel region 224B extends under the first channel region 224A and also partly under the first gate insulator portions 231A.
Gate insulator 231 may be made of a silicon oxide, for example of SiO2.
The first portions 231A of gate insulator 231 have a first thickness e1, and the second portion 231B of gate insulator 231 has a second thickness e2 which is smaller than the first thickness e1.
For example, the first portions 231A are of GO2 type and the second portion 231B is of GO1 type.
For example, the first thickness e1 is in the range from 5 to 10 nm, or even from 6 to 9 nm, and the second thickness e2 is in the range from 1 to 4.5 nm, or even from 2 to 4 nm.
Preferably, the length L1 (first length) of the first channel region 224A, which substantially corresponds to the length of the second gate insulator portion 231B, is smaller than the length CD (second length) of gate region 132.
For example, length L1 is in the range from 1 to 2.5 μm, for example equal to approximately 1.8 μm.
The thickness of the first channel region 224A is preferably smaller than or equal to the first thickness e1. For example, the thickness of the first channel region 224A is in the range from 6 to 9 nm.
The first epitaxial channel region 224A may be made of silicon (Si). AS a variant, the first epitaxial channel region 234A may be made of a silicon-germanium (SiGe) alloy, enabling to have a stressed channel region 224, and to increase the charge mobility.
Preferably, gate region 132 is above, and overhangs on either side of, the first channel region 224A, or the second portion 231B, in the X direction, so that a non-zero distance Ov separates the side wall 132A of gate region 132 and the second gate insulator portion 231B. This distance Ov corresponds to a length in which gate region 132 is separated from semiconductor region 120, in particular from the LDD regions and from the drain and source regions, by the largest thickness (the first thickness e1) of the gate insulator, corresponding to the thickness of the first gate insulator portions 231A.
For example, gate region 132 is centered with respect to the first channel region 224A and/or to the second gate insulator portion 231B.
Preferably, distance Ov is greater than the overlap length Xj of LDD region 125, and/or of the drain 121 and source 122 regions, under gate region 132, so that this overlap occurs under the largest gate insulator thickness (thickness e1). Thus, the overlap capacitance can be decreased.
Further, due to a smaller gate insulator thickness (thickness e2) between gate region 132 and the first channel region 224A, the threshold voltage may be decreased.
It should be noted that to decrease the overlap capacitance, it is possible to decrease overlap distance Xj. A known solution is to form an offset spacer on the side walls of gate region 132 and on thin protection oxide layer 134, enabling to provide an offset during the forming of LDD regions 125, before forming insulating spacers 135 and the drain 121 and source 122 regions. Such an offset spacer forms a protective mask which continues the mask formed by gate region 132 and thin oxide layer 134 during the operation of doping of the LDD regions, to limit the dopant diffusion under the gate region. The embodiments may enable to advantageously dispense with the need for such offset spacers, particularly enabling to simplify the manufacturing method.
As an example, overlap distance Xj is in the range from 40 to 80 nm, for example equal to approximately 60 nm.
For example, distance Ov is in the range from 70 to 100 nm, for example from 80 to 90 nm, for example equal to approximately 85 nm.
The inventors have determined that the presence of a step in gate insulator 231, between each first portion 231A and second portion 231B, enables to modify the current lines and in particular to concentrate the current at the interface between the first channel region 224A and the second gate insulator portion 231B, which has a smaller thickness (thickness e2), favoring current conduction at this interface, and thus potentially to decrease the transistor threshold voltage. Further, as explained above, the overlap capacitance may be reduced due to a greater gate insulator thickness (thickness e1 of the first gate insulator portions 231A). Thus, the embodiments enable to decrease the overlap capacity without increasing the threshold voltage, or even while decreasing it.
The inventors have also determined that the embodiments could improve the reliability over time of the transistor, in particular by decreasing the charge carrier phenomenon.
Indeed, the presence of the step in gate insulator 231, particularly enabling to modify the current lines as discussed hereabove, enables to slow down charge carriers so that the latter end up in a limited area between each first gate insulator portion 231A and each LDD region 125. Thus, fewer charge carriers can accumulate between gate structure 230 and each LDD region.
The other characteristics of the MOSFET transistor 200 of
The structure of
The first insulator layer 301 may be formed by oxidizing semiconductor layer 120. The first insulator layer 301 may be formed by oxidizing semiconductor layer 120 across an initial thickness greater than the third thickness e3, for example approximately 20 nm, and then by removing part of this thickness to obtain the third thickness e3. For example, semiconductor layer 120 is made of silicon, and the first insulator layer 301 is made of a silicon oxide, for example of SiO2.
Further, an etch mask 302 is formed on the first insulator layer 301. Etch mask 302 comprises an opening 303, corresponding to the desired opening in the first insulator layer 301 at the next step.
The etching is preferably a wet etching. For example, this etching step is carried out with hydrofluoric acid, for example, for a duration in the range from 150 to 400 seconds.
The etching stops at semiconductor layer 120.
Etch mask 302 is then removed.
There has been shown in
The second channel region 224B is intended to be formed under the first channel region 224A.
The thickness of the first epitaxial channel region 224A is, for example, substantially equal to the third thickness e3. In this case, the first channel region 224A may be flush with the first gate insulator portions 231A. As a variant, the thickness of the first epitaxial channel region 224A may be smaller than the third thickness e3, for example the first channel region 224A does not completely fill opening 304.
This second gate insulator portion 231B may be formed by oxidizing the first channel region 224A. For example, the first channel region 224A is made of silicon, and the second gate insulator portion 231B is made of a silicon oxide, for example of SiO2. An oxidation may occur to a lesser extent, that is, generally less rapidly and thus across a thickness smaller than the second thickness e2, on the first gate insulator portions 231A. In this case, the thickness of the first gate insulator portions 231A may slightly increase during the oxidation to form the second gate insulator region 231B, so that the first thickness e1 is greater than the third thickness e3, and greater than the second thickness e2.
The second gate insulator portion 231B may be raised with respect to the level of the first portions 231A, as illustrated in
As a variant, the second gate insulator portion 231B may be formed by deposition of a second insulator layer on the second channel region 224A, and optionally also on the first gate insulator portions 231A.
For example, the third thickness e3 is in the range from 4.5 to 9.5 nm, the first thickness e1 is in the range from 5 to 10 nm, or even from 6 to 9 nm, and the second thickness e2 is in the range from 1 to 4.5 nm, or even from 2 to 4 nm.
During the forming of gate structure 230, a stack of one or a plurality of layers of material(s) intended to form gate region 132 may be deposited on gate insulator 231, after which this stack is laterally etched to form gate region 132 according to the desired length CD of this gate region. This etching is preferably selected so that this length CD is greater than the length L1 of the first channel region 224A. Preferably, the etching of the stack is selected so that gate region 132 overhangs on either side of second gate insulator portion 231B in the X direction, by a non-zero distance Ov. For example, gate region 132 is centered with respect to the second portion 231B.
In
For an NMOS transistor, the doping of the source and drain regions, and of the LDD regions, may use N-type dopants such as arsenic (As) or phosphorus (P). For a PMOS transistor, the doping of the source and drain regions, and of the LDD regions, may use P-type dopants such as boron (B).
Thus, the manufacturing of a MOSFET transistor according to the embodiments may be performed by implementing a standard MOSFET transistor manufacturing method.
Curves 401 and 403 correspond to the reference transistor. Curves 402 and 404 correspond to the transistor of
In
There appears from these curves that the embodiments enable to decrease the threshold voltage VT of the transistor, which has been represented by a horizontal arrow in
A transistor according to an embodiment may be embedded in an electronic device, which may further comprise one or a plurality of reference transistors, that is, with no stepped gate insulator and with no epitaxial channel region under the step.
Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art.
Finally, the practical implementation of the described embodiments and variants is within the abilities of those skilled in the art based on the functional indications given hereabove.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2400490 | Jan 2024 | FR | national |
