BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate specific embodiments of the present invention. In the Drawings:
FIG. 1 is a block diagram showing the conventional inter-picture prediction coding device;
FIG. 2 is a block diagram showing the conventional inter-picture prediction decoding device;
FIG. 3 is a block diagram showing a structure in which the inter-picture prediction coding device is connected with a frame memory;
FIG. 4 is a schematic diagram showing how pixels in one reference picture are to be transferred;
FIG. 5 is a schematic diagram showing how a memory is updated, in order to reduce a transfer amount of reference pixels;
FIG. 6 is a schematic diagram showing how stored pixels are managed, in order to reduce a capacity of the reference local memory;
FIG. 7 is a diagram showing a physical address layout around a logical boundary in the reference logical memory, when the FIFO management is used.
FIG. 8 is a block diagram showing a structure of an inter-picture prediction coding device using a motion estimation device according to the first embodiment;
FIG. 9 is a block diagram showing a structure in which the inter-picture prediction coding device is connected with a frame memory;
FIG. 10 is a schematic diagram showing memory areas in a cache memory and the reference local memory;
FIG. 11 is a schematic diagram showing a structure of rectangular areas stored in the cache memory;
FIG. 12 is a schematic diagram showing a structure of rectangular areas when next motion estimation is performed;
FIG. 13 is a schematic diagram showing positions of intermediate information of address conversion performed by the motion estimation device according to the first embodiment of the present invention;
FIGS. 14A and 14B are flowcharts of the address conversion performed by the motion estimation device according to the first embodiment of the present invention;
FIG. 15 is a schematic diagram showing a management area storing pixels of a reference picture used in a motion estimation device according to the second embodiment of the present invention;
FIG. 16 is a schematic diagram showing positions of intermediate information of address conversion performed by the motion estimation device according to the second embodiment of the present invention;
FIG. 17 is a flowchart of address conversion performed by the motion estimation device according to the second embodiment of the present invention;
FIG. 18 is a schematic diagram showing a management area storing reference picture pixels used in a motion estimation device according to the third embodiment of the present invention;
FIG. 19 is a schematic diagram showing positions of intermediate information of address conversion in the motion estimation device according to the third embodiment of the present invention;
FIG. 20 is a flowchart of address conversion performed by the motion estimation device according to the third embodiment of the present invention;
FIGS. 21A and 21B are schematic diagrams showing a structure of rectangular areas when a motion estimation range is positioned at edges of a reference picture;
FIG. 22 is a block diagram showing a structure in which an inter-picture prediction coding device is connected with a frame memory, according to the fifth embodiment of the present invention;
FIGS. 23A and 23B are schematic diagrams showing managed areas for storing pixels of a reference picture used in a motion estimation device according to the fifth embodiment of the present invention;
FIG. 24 is a block diagram showing a structure in which an inter-picture prediction coding device is connected with a frame memory, according to the sixth embodiment of the present invention;
FIGS. 25A and 25B are schematic diagrams showing managed areas for storing pixels of a reference picture used in a motion estimation device according to the sixth embodiment of the present invention;
FIGS. 26A and 26B are schematic diagrams showing variations of managed areas storing pixels of a reference picture used in a motion estimation device according to the sixth embodiment of the present invention; and
FIG. 27 is a block diagram showing a structure of an AV processing unit realizing a H.264 recorder.