Patent Application
20240388237
The present disclosure relates to a motor controller, a motor control system, and a motor control method that each control a motor.
A motor controller has been known that controls a motor that is driven by electric power supplied from a power source and converted by use of an electric-power converter device provided with an inverter. In a case in which a motor is mounted on a compressor, a failure in the compressor is caused by degradation, damage, or other unpleasant state of, for example, an inverter, a shaft bearing of the compressor, or the motor. Even in a case in which the compressor does not yet have a failure, when the compressor is still continuously driven in a state in which the inverter, the shaft bearing of the compressor, or the motor is in degradation or damage, the compressor eventually has a failure and thus causes downtime that a user does not predict. In Patent Literature 1, a failure diagnostic device has been disclosed that determines whether a compressor is in failure by operating the compressor when an air-conditioning apparatus is not in operation.
The failure diagnostic device described in Patent Literature 1 is a device that determines whether a compressor is in failure when an air-conditioning apparatus is not in operation. In other words, the failure diagnostic device described in Patent Literature 1 is a device for a scheduled maintenance checkup on the compressor. Downtime unpredictable for a user however still usually requires unscheduled arrangement for repair or other time and effort. Downtime unpredictable for a user may thus require longer time than does predictable downtime such as a scheduled maintenance checkup. To increase an overall operation rate of a device on which a motor is mounted, a likelihood of downtime unpredictable for a user thus requires to be reduced or eliminated.
The present disclosure is made to solve such an above problem and to provide a motor controller, a motor control system, and a motor control method that each reduce or eliminate a likelihood of downtime unpredictable for a user in a device on which a motor is mounted.
A motor controller according to an embodiment of the present disclosure controls a motor that is driven by electric power supplied from a power source and converted by use of an electric-power converter device provided with an inverter. The motor controller is provided with degradation estimation circuitry configured to calculate an estimated degradation level obtained by estimating a degradation level of a device on which the motor is mounted or a degradation level of the inverter;
operation decision circuitry configured to compare the estimated degradation level and a reference degradation level, which is predetermined, and set an operation mode of the motor, in a case in which the estimated degradation level is lower than the reference degradation level, to an normal operation, and set the operation mode, in a case in which the estimated degradation level is higher than or equal to the reference degradation level, to a low-noise pulse operation; and control circuitry configured to control the inverter according to the operation mode. The low-noise pulse operation is designed to reduce switching loss to be less than does the normal operation.
The motor controller according to an embodiment of the present disclosure performs the low-noise pulse operation designed to reduce switching loss to be less than does the normal operation. Progress in degradation of the inverter and the motor is thus made delayed. With a device on which the motor is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
A method of controlling a motor controller 1, a motor control system 1A, a compressor 2, and a motor 21 is described below with reference to drawings. In the drawings, components denoted by the same reference signs are the same components or equivalents. These reference signs are common through all embodiments described below. The form of a component represented in all embodiments is merely an example and the component is not limited to the form described below. In particular, combinations of the components are not intended to be limited only to combinations in the embodiments. A component described in one embodiment is applicable to another embodiment. In addition, a level of a parameter such as a pressure and a temperature is not determined in relation to a particular absolute value but is relatively determined under conditions, such as states and behavior of devices or other components.
The electric-power converter device 4 has a rectifier circuit 41, an electrolytic capacitor 42, and an inverter 43. The power source 3, the rectifier circuit 41, the electrolytic capacitor 42, the inverter 43, and the motor 21 are connected to each other by wires 44. The rectifier circuit 41 converts three-phase alternating-current electric power from the power source 3 into direct-current electric power. The electrolytic capacitor 42 smooths the direct-current electric power from the rectifier circuit 41. The inverter 43 converts the direct-current electric power from the rectifier circuit 41 into three-phase alternating-current electric power and outputs the three-phase alternating-current electric power to the compressor 2.
To the electric-power converter device 4, a current sensor 5 is provided. The current sensor 5 is provided to wires 44a. The wires 44a are portions of the wires 44 located on the way from the inverter 43 to the motor 21. The current sensor 5 detects a two-phase electric current among a three-phase alternating electric current that flows from the inverter 43 to the compressor 2. At the current sensor 5, an electric current Iu, which flows through the U-phase, and electric current Iv, which flows through the V-phase, are detected. In addition, a U-phase electric current Iu and a V-phase electric current Iv are also collectively referred to as an electric current Iuv in some cases below. The current sensor 5 sends the detected electric current Iuv to the motor controller 1.
The motor controller 1 executes a method of controlling the motor 21 by adjusting a switching pattern included in a gate pulse GP output to the inverter 43. The switching patterns are a set of switching states each in response to a single cycle of a voltage command value. The voltage command value is a signal through which an output voltage of the inverter 43 is ordered. The motor controller 1 generates a gate pulse GP for each cycle of voltage command values.
The motor controller 1 is dedicated hardware or a set of memory circuitry 180 and a central processing unit (CPU) that executes a program stored in the memory circuitry 180. In a case in which the motor controller 1 is dedicated hardware, the motor controller 1 is a circuit such as an application specific integrated circuit (ASIC) and a field-programmable gate array (FPGA).
In a case in which the motor controller 1 is a set of the memory circuitry 180 and a CPU, functions of the motor controller 1 are implemented by software, firmware, or a combination of software and firmware. Software and firmware are described as programs and stored in the memory circuitry 180. The memory circuitry 180 is, for example, a volatile or non-volatile semiconductor memory such as a RAM, a ROM, a flash memory, an EPROM, and an EEPROM.
The motor controller 1 has control circuitry 130, degradation estimation circuitry 150, degradation notification circuitry 160, and operation decision circuitry 170. The control circuitry 130, the degradation estimation circuitry 150, the degradation notification circuitry 160, and the operation decision circuitry 170 are described later. In addition, the motor controller 1 only requires to have at least the control circuitry 130, and the degradation estimation circuitry 150, the degradation notification circuitry 160, and the operation decision circuitry 170 may also be mounted on other components such as hardware.
The switching element 43a and the backflow-prevention element 43b may also have a substrate made from a wide-band-gap semiconductor as typified by material such as silicon carbide (SIC), gallium nitride (GaN) system, and a diamond. The switching element 43a and the backflow-prevention element 43b each provided with a wide-band-gap semiconductor are high in both voltage endurance and allowable electric current, and the elements are thus downsizable. By use of the downsized switching elements 43a and the downsized backflow-prevention elements 43b, a semiconductor module in which these elements are built is thus downsizable.
The switching element 43a and the backflow-prevention element 43b each provided with a wide-band-gap semiconductor are also high in heat resistance, and an unillustrated cooling mechanism required to reject heat of the inverter 43 is thus downsizable. The cooling mechanism is, for example, radiating fins, a water-cooling mechanism, or an air-cooling mechanism. In addition, by use of, for example, an air-cooling system with a simple structure as the cooling mechanism, such a cooling system is simplified and a semiconductor module in which the switching elements 43a and the backflow-prevention elements 43b are built is further downsizable.
The switching element 43a and the backflow-prevention element 43b each provided with a wide-band-gap semiconductor are also low in electric power loss and thus improves power conversion efficiency. The compressor 2 is thus driven at high conversion efficiency.
In addition, both the switching element 43a and the backflow-prevention element 43b preferably each have a wide-band-gap semiconductor. Alternatively, any one of the elements may also have a wide-band-gap semiconductor. In the first place, both the elements may also be each formed by a material other than a wide-band-gap semiconductor. As a material other than a wide-band-gap semiconductor, silicon (Si), which is also widely used, is adopted.
In a state in which the switching element 43a in the inverter 43 is degraded, electric power supplied from the inverter 43 to the motor 21 is unstable. In a state in which the switching element 43a in the inverter 43 is degraded, when the compressor 2 is continuously driven, the rotation of the motor 21 is thus unstable and the compressor 2 may be in failure. Degradation of the switching element 43a in the inverter 43 is thus a factor that may cause downtime unpredictable for a user.
The motor 21 is connected to the three-phase alternating-current wires 44a, which are referable to
The suction pipe 22 is a pipe through which low-temperature and low-pressure refrigerant is sucked in the compressor 2. The main shaft 23 is connected to the motor 21 and, via the main shaft 23, rotational energy is transferred to the compression mechanism 27. The oil pump 24 supplies lubricating oil L stored in the bottom of the compressor 2 to the main shaft 23 and the sub-shaft bearing 25 and the lubricating oil L lubricates the main shaft 23 and the sub-shaft bearing 25. In addition, as a means to confirm the amount of the lubricating oil L, a fluid-level sensor configured to detect the oil level of the lubricating oil L may also be attached to measure the amount of the lubricating oil L.
The sub-shaft bearing 25 supports a lower portion of the main shaft 23 such that the main shaft 23 is rotatable. The main shaft bearing 26 supports an upper portion of the main shaft 23 such that the main shaft 23 is rotatable. The compression mechanism 27 compresses refrigerant supplied from the suction pipe 22 and sends out the refrigerant to the discharge pipe 28. The discharge pipe 28 is a pipe through which high-temperature and high-pressure refrigerant compressed by the compression mechanism 27 is discharged out from the compressor 2.
The compressor 2 has a pressure sensor 71, a flow-rate sensor 72, a temperature sensor 73, and a humidity sensor 74. The pressure sensor 71 is attached inside the compressor 2 and measures the pressure of refrigerant inside the compressor 2. The flow-rate sensor 72 is attached to the suction pipe 22 and measures the flow rate of refrigerant that flows inside the pipe. The temperature sensor 73 is attached outside the housing of the compressor 2 and measures the temperature around the compressor 2. The humidity sensor 74 is attached outside the housing of the compressor 2 and measures the humidity around the compressor 2. In addition, to the suction pipe 22 or the discharge pipe 28, a sensor configured to measure the pressure, the temperature, or the humidity of refrigerant that flows inside the pipe may also be attached. Measurement information that indicates physical quantity such as a refrigerant pressure measured by the pressure sensor 71, a refrigerant flow rate measured by the flow-rate sensor 72, an ambient temperature measured by the temperature sensor 73, and an ambient humidity measured by the humidity sensor 74 is sent to unillustrated components such as a controller of an air-conditioning apparatus and is used for control of devices of the air-conditioning apparatus.
A positional relationship between the main shaft 23 and the main shaft bearing 26 in a case in which the compressor 2 is driven is described with reference to
As illustrated in
With reference back to
The operation modes of the motor 21 are the normal operation and the low-noise pulse operation. “OFF” of the operation-mode switching signal O_s indicates the normal operation and “ON” of the operation-mode switching signal O_s indicates the low-noise pulse operation. The normal operation is an operation in which non-synchronous PWM control is exercised. The non-synchronous PWM control does not synchronize a frequency of a carrier signal and a frequency of an output voltage of the inverter 43 with each other. The low-noise pulse operation is an operation in which synchronous PWM control is exercised. The synchronous PWM control causes a frequency of a carrier signal in PWM control to be equal to an integral multiple of a frequency of an output voltage of the inverter 43. In addition, a frequency of a carrier signal in PWM control is simply referred to as “carrier frequency” in some cases below. As described above, the control circuitry 130 causes the motor 21 to perform either one of the normal operation and the low-noise pulse operation according to an operation mode set by the operation decision circuitry 170. In addition, a process is described later in which the operation decision circuitry 170 decides and sets the operation-mode switching signal O_s to either one of “ON” and “OFF”.
With reference to
The vector control circuitry 131 exercises vector control, which is a known technique, according to the speed command value ω_ref and a two-phase electric current Iuv among a three-phase alternating electric current and outputs, to the voltage-phase arithmetic circuitry 133, a dq-axis voltage command value Vdq_ref and a reference voltage phase θv subjected to control delay correction. In addition, the control delay correction is processing in which timing of the speed command value and timing of a feedback detection value are adjusted and usually provides the value θv obtained by multiplying a value obtained by integrating the speed command value ω_ref with 1.5 in consideration of dead time.
The synchronous-pattern selection circuitry 132 generates a carrier mode ptn according to the speed command value ω_ref and sends the carrier mode ptn to the correction-amount arithmetic circuitry 134 and the carrier-wave generation circuitry 135. The carrier mode ptn indicates patterns of PWM control, which is related to motor control. Specifically, the carrier mode ptn has two patterns different in carrier frequency generated by the carrier-wave generation circuitry 135. In other words, one of the two patterns is for an operation mode in which the non-synchronous PWM control is exercised and the other one is for an operation mode in which the synchronous PWM control is exercised.
The first pattern in the carrier mode ptn indicates the non-synchronous PWM control in which a carrier frequency is set irrespective of a frequency of an output voltage of the inverter 43. As described above, the normal operation uses the non-synchronous PWM control, and the first pattern in the carrier mode ptn is thus generated when the motor 21 is caused to perform the normal operation.
The second pattern in the carrier mode ptn indicates the synchronous PWM control in which a carrier frequency is set to be equal to an integral multiple of a frequency of an output voltage of the inverter 43. As described above, the low-noise pulse operation uses the synchronous PWM control, and the second pattern in the carrier mode ptn is thus generated when the motor 21 is caused to perform the low-noise pulse operation. In addition, as the synchronous PWM control, a synchronous 9 pulse mode in which a carrier frequency is set to be nine times larger than a frequency of an output voltage of the inverter 43 and a synchronous 3 pulse mode in which a carrier frequency is set to be three times larger than a frequency of an output voltage of the inverter 43 are used. The synchronous 9 pulse mode is simply referred to as “synchronous 9 pulse” and the synchronous 3 pulse mode is simply referred to as “synchronous 3 pulse” in some cases below.
The synchronous-pattern selection circuitry 132 specifically generates a carrier mode ptn as follows. The synchronous-pattern selection circuitry 132 generates, as a carrier mode ptn, 0, which indicates a non-synchronization mode, in a case in which the speed command value ω_ref is higher than or equal to 0 [rps] and lower than ω_ref1 [rps]. The synchronous-pattern selection circuitry 132 generates, as a carrier mode ptn, 9, which indicates a synchronous 9 pulse in the synchronization mode, in a case in which the speed command value ω_ref is higher than or equal to ω_ref1 [rps] and lower than ω_ref2 [rps]. The synchronous-pattern selection circuitry 132 generates, as a carrier mode ptn, 3, which indicates a synchronous 3 pulse in the synchronization mode, in a case in which the speed command value ω_ref is higher than or equal to ω_ref2 [rps]. The carrier mode ptn is thus 0 during the non-synchronization mode and is thus either one value of 3 and 9 during the synchronization mode. The synchronous-pattern selection circuitry 132 sends a carrier mode ptn to the correction-amount arithmetic circuitry 134 and the carrier-wave generation circuitry 135 every time the carrier mode ptn is switched.
The voltage-phase arithmetic circuitry 133 calculates a voltage phase θv2 subjected to phase adjustment by use of the dq-axis voltage command value Vdq_ref and the reference voltage phase θv received from the vector control circuitry 131. The voltage phase θv2 is defined by, for example, a phase to which a 90 [deg] phase is shifted from the reference voltage phase θv. The voltage-phase arithmetic circuitry 133 sends the voltage phase θv2 to the correction-amount arithmetic circuitry 134.
The voltage-phase arithmetic circuitry 133 also converts the dq-axis voltage command value Vdq_ref into a three-phase coordinate system by use of the voltage phase θv2 and thus arithmetically determines a three-phase voltage command value Vuvw_ref. The voltage-phase arithmetic circuitry 133 sends the three-phase voltage command value Vuvw_ref to the gate-pulse generation circuitry 136.
The correction-amount arithmetic circuitry 134 arithmetically determines a carrier-cycle correction amount Δtc on the basis of the voltage phase θv2 received from the voltage-phase arithmetic circuitry 133 and the carrier mode ptn received from the synchronous-pattern selection circuitry 132. The carrier-cycle correction amount Δtc is to be used to correct a difference between the voltage phase θv2 and a phase command value θv2_ref, which corresponds to the carrier mode ptn. The correction-amount arithmetic circuitry 134 sends the carrier-cycle correction amount Δtc, which is arithmetically determined, to the carrier-wave generation circuitry 135.
An arithmetic operation of the carrier-cycle correction amount Δtc is specifically described. The correction-amount arithmetic circuitry 134 generates a phase command value θv2_ref for every synchronization pulse and thus generates a carrier wave. In other words, the correction-amount arithmetic circuitry 134 generates, every time the carrier mode ptn is switched, a phase command value θv2_ref that corresponds to the switched carrier mode ptn. In a case in which, for example, control is exercised in the synchronous 9 pulse, a voltage phase θv2 is preset for every 40=360/9 [deg] in response to a single cycle of a carrier wave. Such an arithmetic operation ensures continuity while a carrier mode is being switched.
In such an arithmetic operation, a difference may arise between a phase command θv2_ref and the voltage phase θv2. The correction-amount arithmetic circuitry 134 performs processing described below to promptly eliminate the difference. By use of, for example, an equation (1) described below, a phase difference value ΔP, which corresponds to the difference between the phase command θv2_ref and the voltage phase θv2, is first calculated.
The correction-amount arithmetic circuitry 134 next calculates a carrier-cycle correction amount Δtc by use of, for example, an equation (2) described below. In the equation (2), GAIN is a carrier-cycle gain. The correction-amount arithmetic circuitry 134 multiplies the phase difference value by GAIN and thus converts the phase difference value into a cycle difference amount. In addition, as long as the phase difference value ΔP falls within the entire operation areas, a fixed value or a variable value may also be set as the carrier-cycle gain GAIN. In a case in which, for example, the carrier-cycle gain GAIN is set to a variable value, the carrier-cycle gain GAIN may also be set such as the carrier-cycle gain GAIN is adjusted according to the speed command value ω_ref. The correction-amount arithmetic circuitry 134 sends the carrier-cycle correction amount Δtc to the carrier-wave generation circuitry 135 as well.
A method by which the correction-amount arithmetic circuitry 134 generates the carrier-cycle correction amount Δtc is described below with reference to
The carrier-wave generation circuitry 135 generates a carrier wave Carrier on the basis of a carrier mode ptn received from the synchronous-pattern selection circuitry 132, the carrier-cycle correction amount Δtc received from the correction-amount arithmetic circuitry 134, and a speed command value ω_ref. Specifically, the carrier-wave generation circuitry 135 calculates a carrier cycle tc by use of an equation (3).
The carrier-wave generation circuitry 135 then outputs a carrier wave Carrier on the basis of a carrier cycle to set such as the carrier-cycle correction amount Δtc falls into 0. Through procedures described above, a frequency of the carrier wave Carrier output from the carrier-wave generation circuitry 135 promptly falls into a frequency of ptn×ω_ref, which is an accurate frequency in the synchronization pulse, after the carrier mode is switched. The carrier-wave generation circuitry 135 sends the carrier wave Carrier to the gate-pulse generation circuitry 136. The carrier-wave generation circuitry 135 also sends, in a case in which the carrier mode ptn is 0, which indicates the non-synchronization mode, a fixed carrier frequency Carrier to the gate-pulse generation circuitry 136.
The gate-pulse generation circuitry 136 compares a three-phase voltage command value Vuvw_ref received from the voltage-phase arithmetic circuitry 133 and the carrier wave Carrier received from the carrier-wave generation circuitry 135 with each other and thus outputs a gate pulse GP. In this procedure, the gate-pulse generation circuitry 136 uses, as a comparison target, any one of a fixed carrier frequency in the normal operation and a carrier frequency in the low-noise pulse operation according to an operation-mode switching signal O_s received from the operation decision circuitry 170. Specifically, in a case in which the operation-mode switching signal O_s is “OFF”, the gate-pulse generation circuitry 136 uses a fixed carrier frequency Carrier in the normal operation as a comparison target and thus outputs a gate pulse GP. At this time, the motor 21 performs the normal operation. Also, in a case in which the operation-mode switching signal O_s is “ON”, the gate-pulse generation circuitry 136 uses a carrier frequency Carrier in the low-noise pulse operation as a comparison target and thus outputs a gate pulse GP. At this time, the motor 21 performs the low-noise pulse operation.
With reference back to
Specifically, in a two-phase electric current Iuv among a three-phase alternating electric current, sideband waves centered on a specific frequency appear for each estimation target. The degradation estimation circuitry 150 analyzes the strength level of the sideband waves, which appear in the electric current Iuv, and thus acquires an estimated degradation level W_est. In addition, with regard to the estimated degradation level W_est, in a case in which estimation targets of a plurality of type exist, for example, an estimated degradation level W_est is only required to be calculated for each type of the estimation targets and the highest estimated degradation level W_est is thus calculated.
The degradation estimation circuitry 150 may also calculate an estimated degradation level W_est on the basis of an imbalance level of a three-phase electric current Iuvw. The imbalance level of a three-phase electric current Iuvw is calculated on the basis of a U-phase and V-phase electric current Iuv and a W-phase electric current Iw acquired by use of an equation (4). In addition, the degradation estimation circuitry 150 may also calculate an estimated degradation level W_est on the basis of a value acquired by converting a three-phase electric current into a frequency area.
In addition, the imbalance level of a three-phase electric current Iuvw is caused as follows.
With reference to
The degradation notification circuitry 160 causes, according to an estimated degradation level W_est received from the degradation estimation circuitry 150, a user terminal 200 to turn on a notification display that indicates that a device on which the motor 21 is mounted degrades. Specifically, the degradation notification circuitry 160 judges whether the estimated degradation level W_est is higher than or equal to the preset reference degradation level x. In a case in which the estimated degradation level W_est is higher than or equal to the preset reference degradation level x, the degradation notification circuitry 160 causes the user terminal 200, which is referable to
The user terminal 200 receives operation from a user who confirms the notification display G on whether the low-noise pulse operation is allowed to start. In a case in which the user allows the life-extending operation, that is, the user selects “YES” illustrated in
In a case in which the estimated degradation level W_est is higher than or equal to the reference degradation level x, the speed command value ω_ref is higher than or equal to the switching speed ω_ref1, and “ON” of the low-noise pulse-operation start signal L_s is output, the operation decision circuitry 170 sends an “ON” signal of the operation-mode switching signal O_s to the control circuitry 130. In a case in which conditions described above are not satisfied, the operation decision circuitry 170 sends an “OFF” signal of the operation-mode switching signal O_s to the control circuitry 130. When the control circuitry 130 receives the “ON” signal of the operation-mode switching signal O_s thus input, the control circuitry 130 causes the low-noise pulse operation to be performed. When the control circuitry 130 receives the “OFF” signal of the operation-mode switching signal O_s thus input, the control circuitry 130 causes the normal operation to be performed.
In a case in which the estimated degradation level W_est is higher than or equal to the reference degradation level x, the operation decision circuitry 170 causes a management device, such as a management terminal 300, which is referable to
With reference to
In the normal operation in which the non-synchronous PWM control is exercised, when the rotation frequency of the motor 21 increases and a pulse number of the output voltage reduces, as illustrated in
On the other hand, in the low-noise pulse operation in which the synchronous PWM control is exercised, as illustrated in
In the low-noise pulse operation, a carrier mode ptn is also generated such that, as the speed command value ω_ref increases, a frequency ratio between a carrier signal and an output voltage of the inverter 43 sequentially and gradually reduces. As the speed command value ω_ref increases, the frequency of the carrier signal thus reduces. The carrier signal is small and a switching count of the inverter 43, which is the number of switching operations of the inverter 43, thus reduces, and switching loss consequently reduces. As described above, the switching pattern of the inverter 43 is adjusted such that the switching loss in the low-noise pulse operation reduces to be less than in a case of the normal operation.
The switching loss reduces and the switching elements 43a and the backflow-prevention elements 43b in the inverter 43 are thus prevented from increasing in temperature. Progress in degradation of the inverter 43 is thus made delayed. The switching loss reduces and a switching noise, which may be produced as a transient phenomenon during the same switching is thus also reduced or eliminated and progress in degradation of the motor 21 and the main shaft bearing 26 is consequently made delayed.
In addition, in the synchronous PWM operation, switching elements 43a in the inverter 43 that are located in an up-down direction are substantially equal to each other in pulse output of the output voltage, a difference in progress in degradation of the switching elements 43a located in the up-down direction is thus reduced or eliminated. As described above, the low-noise pulse operation delays progress in degradation of the inverter 43, the main shaft bearing 26 of the compressor 2, and the motor 21, which are estimation targets.
With reference to
The operation decision circuitry 170 next judges whether the speed command value ω_ref is higher than or equal to the switching speed ω_ref1 (step S13). In a case in which the speed command value ω_ref is lower than the switching speed ω_ref1 (NO in step S13), the operation decision circuitry 170 sends an “OFF” signal of the operation-mode switching signal O_s to the control circuitry 130 (step S16). Such behavior causes the motor 21 to perform the normal operation. In a case in which the speed command value ω_ref is higher than or equal to the switching speed ω_ref1 (YES in step S13), the operation decision circuitry 170 judges whether the low-noise pulse-operation start signal L_s received from the degradation notification circuitry 160 is “ON” (step S14).
In a case in which the low-noise pulse-operation start signal L_s received from the degradation notification circuitry 160 is “OFF” (NO in step S14), the operation decision circuitry 170 sends an “OFF” signal of the operation-mode switching signal O_s to the control circuitry 130 (step S16). Such behavior causes the motor 21 to perform the normal operation. In a case in which the low-noise pulse-operation start signal L_s received from the degradation notification circuitry 160 is “ON” (YES in step S14), the operation decision circuitry 170 sends an “ON” signal of the operation-mode switching signal O_s to the control circuitry 130 (step S15). Such behavior causes the motor 21 to perform the low-noise pulse operation.
As described above, the motor controller 1 according to Embodiment 1 performs the low-noise pulse operation, in which the switching pattern of the inverter 43 is adjusted such that the switching loss reduces to be less than in a case of the normal operation. Degradation of the inverter 43 and the motor 21 is thus made delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
In addition, in a case in which the motor 21 is mounted on the compressor 2, degradation of a shaft bearing of the compressor 2 is delayed. With the compressor 2, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
In addition, as described above, the motor controller 1 according to Embodiment 1 executes a method of controlling the motor 21 such that the motor 21 operated by electric power supplied from the power source 3 and converted by use of the electric-power converter device 4 provided with the inverter 43 is controlled. Specifically, in the method of controlling the motor 21, an estimated degradation level obtained by estimating a degradation level of a device on which the motor 21 is mounted or a degradation level of the inverter 43 is first calculated. The estimated degradation level and a reference degradation level, which is predetermined, are next compared with each other and, in a case in which the estimated degradation level is lower than the reference degradation level, an operation mode of the motor 21 is set to the normal operation, and, in a case in which the estimated degradation level is higher than or equal to the reference degradation level, the operation mode is set to the low-noise pulse operation. The inverter 43 is then controlled according to the operation mode thus set. The low-noise pulse operation reduces the switching loss to be less than in a case of the normal operation. Degradation of the inverter 43 and the motor 21 is thus made delayed. By the method of controlling the motor 21 according to Embodiment 1, with a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
The motor controller 1 according to Embodiment 2 performs the low-noise pulse operation designed to reduce switching loss to be less than in a case of the non-synchronous PWM control by use of what is referred to as an artificial intelligence (AI) through a gate pulse GP sent to the inverter 43. To a configuration of the hardware in the motor controller 1, a graphics processing unit (GPU) may also be added in addition to components described in Embodiment 1.
Unlike the voltage-phase arithmetic circuitry 133 in Embodiment 1, the voltage-phase arithmetic circuitry 133 in Embodiment 2 does not calculate a voltage phase θv2.
The gate-pulse generation circuitry 136 has the inference circuitry 142. The gate-pulse generation circuitry 136 outputs a different gate pulse GP according to whether either operation mode of the normal operation and the low-noise pulse operation is to be performed in accordance with an operation-mode switching signal O_s. For the normal operation, a gate pulse GP with which the non-synchronous PWM control described in Embodiment 1 is exercised is output. For the low-noise pulse operation, a gate pulse GP based on information obtained through processing performed by the inference circuitry 142 is output. The inference circuitry 142 is described later.
The learning circuitry 141 is configured to generate a learned model PGF used to generate a switching pattern in a gate pulse GP by use of a method of supervised learning. The learned model PGF is a program that includes a function used to generate a switching pattern by use of a parameter adjusted through a learning process. The learning circuitry 141 generates the learned model PGF when the motor 21 stably operates, in other words, when the load and the speed of the motor 21 vary slightly. A description is made below on case in which, as long as the three-phase voltage command value Vuvw_ref varies in a range lower than or equal to a predetermined value, the load and the speed of the motor 21 is determined to vary slightly, and the learning circuitry 141 thus generates the learned model PGF.
A method of generating the learned model PGF is specifically described below. The learning circuitry 141 uses, as learning data, a data set D_set obtained by adjusting three-phase voltage command values Vuvw_ref and switching patterns in gate pulses GP for a plurality of respective cycles. A control system used for the data set D_set is, for example, model predictive control, low-order harmonic elimination, and optimized pulse patterns. These control systems each reduce switching loss of the inverter 43 to be less than in a case of the non-synchronous PWM control. A switching pattern reproduced in advance and obtained in a simulation environment in which a device simulates degradation may also be used as the data set D_set. In addition, the data set D_set is stored in the memory circuitry 180 in advance.
Specifically, the data set D_set is a data set in which a plurality of switching patterns are described for respective cycles in a case in which, at an arbitrary cycle t, each of the plurality of switching patterns is in a gate pulse GP_tr(t) generated in the arbitrary cycle t when a switching pattern in a gate pulse GP_tr(t−1) generated in the previous cycle t−1 and a three-phase voltage command value Vuvw_ref_tr(t) at the arbitrary cycle t are defined.
The learning circuitry 141 has data acquisition circuitry 141a and model generation circuitry 141b. The data acquisition circuitry 141a acquires, from the data set D_set, as input data, a switching pattern in a gate pulse GP_tr(t−1) generated in the previous cycle t−1, which is immediately prior to the arbitrary cycle, and a three-phase voltage command value Vuvw_ref_tr(t) at the arbitrary cycle t. The data acquisition circuitry 141a also acquires, as a label, a switching pattern in a gate pulse GP_tr(t) generated in the arbitrary cycle t. The data acquisition circuitry 141a acquires a plurality of teaching data sets, which contain these input data and labels from the data set D_set, in which a plurality of switching patterns in gate pulses GP are described for respective cycles.
The model generation circuitry 141b proceeds a learning process such that, in a model used to output a switching pattern in a gate pulse GP(t), the switching pattern in the gate pulse GP(t) approaches a switching pattern in a gate pulse GP_tr(t) in a teaching data set on the basis of the switching pattern in the gate pulse GP_tr(t−1) generated in the previous cycle t−1, which is immediately prior to the arbitrary cycle, and the three-phase voltage command value Vuvw_ref_tr(t) at the arbitrary cycle t in the teaching data set. The model generation circuitry 141b performs a learning process for a model on the basis of teaching data sets for a plurality of cycles.
Specifically, the model is formed by a neural network composed of a plurality of combined perceptrons each to which a bias value and a weighting coefficient are set. The bias value and the weighting coefficient are each a parameter adjusted through a learning process. In the learning process, a plurality of pieces of teaching data are supplied to a neural network and a bias value and a weighting coefficient for each perceptron are adjusted such that an output of the neural network approaches the label. As a method of adjusting a bias value and a weighting coefficient for a perceptron, for example, back-propagation is used. In the back-propagation, the bias value and the weighting coefficient are adjusted such that a difference between the output of the neural network and the label reduces to be small.
In addition, the model generation circuitry 141b may also have multi-layered neural networks for a learning process and be thus configured to perform the learning process through what is referred to as deep learning.
Through a method described above, the model generation circuitry 141b generates a learned model PGF used to infer a switching pattern in an arbitrary cycle by use of learning data that includes a voltage command value in the arbitrary cycle and a switching pattern in a previous cycle, which is immediately prior to the arbitrary cycle. That is, the learned model PGF is used to learn a feature of the teaching data set and to output, at a time of control, the switching pattern in the gate pulse GP(t) on the basis of the switching pattern in the gate pulse GP(t−1) determined in the previous cycle and the three-phase voltage command value Vuvw_ref_tr(t) at the time of control. The learned model PGF is stored in the memory circuitry 180. The learned model PGF is used by the inference circuitry 142 to generate a gate pulse GP. In addition,
The inference circuitry 142 inputs, to the learned model PGF, the switching pattern in the gate pulse GP(t−1) determined in the previous cycle and the three-phase voltage command value Vuvw_ref_tr(t) at a time of control and thus acquires, at the time of control, the switching pattern in the gate pulse GP(t) to be output.
As described above, the data set D_set used for the learning process is a control pattern in a control system used to output a gate pulse GP with which switching loss of the inverter 43 reduces to be less than in a case of the non-synchronous PWM control. The learned model PGF is thus also used to output a gate pulse GP with which the switching loss of the inverter 43 reduces to be less than in a case of the non-synchronous PWM control. Control of the inverter 43 executed by the gate-pulse generation circuitry 138, which has the inference circuitry 142, by use of the learned model PGF is also referred as AI switching control in some cases below.
In addition, the learning circuitry 141 may also construct a plurality of learned models PGF for respective types of the control systems for the learning process. For example, not only a learned model PGF used to reduce switching loss but also a learned model PGF used to achieve other purpose that corresponds to a demand from a user such as reduction in oscillation of the compressor 2 may also be constructed. In a case in which a plurality of learned models PGF are constructed, a pattern table in which the learned models PGF and individual numbers assigned to respective learned models PGF correspond to each other is stored in the memory circuitry 180.
In a case in which a plurality of learned models PGF are constructed, the inference circuitry 142 generates a type-selection command TSC for a learned model PGF and outputs the type-selection command TSC to the memory circuitry 180 and thus acquires the learned model PGF that corresponds to the type-selection command TSC from the memory circuitry 180. The type-selection command TSC includes the individual numbers assigned to respective learned models PGF in the pattern table and the memory circuitry 180 is thus configured to read out the corresponding learned model PGF. In addition,
As illustrated in
In a case in which a learning process is not to be performed (NO in step S21), as illustrated in
In a case in which the operation-mode switching signal O_s is “ON” (YES in step S31), the gate-pulse generation circuitry 136 acquires the learned model PGF stored in the memory circuitry 180 (step S33). Subsequently, the gate-pulse generation circuitry 136 acquires the switching pattern in the gate pulse GP(t−1) generated in the previous cycle, which is immediately prior to a time of control, and the three-phase voltage command value Vuvw_ref_tr(t) at the time of control, which are input data (step S34). The gate-pulse generation circuitry 136 inputs the input data into the learned model PGF and thus generates a switching pattern in a gate pulse based on the AI switching control (step S35). The gate-pulse generation circuitry 136 then controls the inverter 43 by use of the gate pulse based on the AI switching control (step S36), and thus causes the inverter 43 to perform the low-noise pulse operation.
The motor controller 1 according to Embodiment 2 also performs, similarly to Embodiment 1, the low-noise pulse operation, in which the switching pattern of the inverter 43 is adjusted such that the switching loss reduces to be less than in a case of the normal operation. Progress in degradation of the inverter 43 and the motor 21 is thus made delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
Also in Embodiment 2, a plurality of learned models PGF are generated for respective purposes and various advantageous effects according to a demand from a user such as reduction in oscillation of the compressor 2 are thus obtained.
The motor controller 1 according to Embodiment 3 corresponds to the motor controller 1 according to Embodiment 2 additionally configured to perform reinforcement learning. The reinforcement learning is a learning method in which an agent is caused to perform a learning process such that a value is maximized to an extent possible in a given environment. As a representative method of the reinforcement learning, Q-learning and TD-learning are known. In the above description, the given environment corresponds to an electric current that flows through the motor 21, that is, a state of the compressor 2, the value corresponds to reduction in switching loss of the inverter 43, and the agent corresponds to the learned model PGF. That is, in Embodiment 3, while the motor 21 is controlled according to the learned model PGF generated through the supervised learning, the reinforcement learning in the low-noise pulse operation is also repeated according to the learned model PGF such that the switching loss is further reduced.
The gate-pulse generation circuitry 136 acquires a learned model PGF in an initial state of the motor controller 1. The learned model PGF in the initial state is, for example, a learned model PGF acquired first after the motor 21 starts stably operating.
The gate-pulse generation circuitry 136 sends, to the inverter 43 and the state observation circuitry 137, a gate pulse GP in the non-synchronous PWM control or a gate pulse GP from the learned model PGF in the initial state of the motor controller 1, according to the operation-mode switching signal O_s. In a case in which, the learned model PGF is used, as described above, the switching pattern in the gate pulse GP(t) is output at a time of control from the switching pattern in the gate pulse GP(t−1) determined in the previous cycle and the three-phase voltage command value Vuvw_ref_tr(t) at the time of control. The gate pulse GP is output to the inverter 43, the motor 21 of the compressor 2 is driven at a speed that corresponds to the three-phase voltage command value Vuvw_ref (t).
The state observation circuitry 137 counts a switching count Sw_count from a gate pulse GP. The state observation circuitry 137 also acquires, on the basis of a resultant frequency into which any one-phase electric current of a three-phase alternating electric current Iuvw is converted, a sideband-wave strength level Sw_level, which indicates a strength level of sideband waves a of a basic frequency fa. A case in which a target converted into a frequency is a U-phase electric current Iu is described above as an example. Alternatively, a target converted into a frequency may also be another phase electric current.
With reference to
As illustrated in
The reward calculation circuitry 141c determines a reward on the basis of the sideband-wave strength level Sw_level arithmetically determined by the state observation circuitry 137. Specifically, the reward calculation circuitry 141c judges whether the sideband-wave strength level Sw_level arithmetically determined by the state observation circuitry 137 is lower than or equal to a default value. In a case in which the reward calculation circuitry 141c judges that the sideband-wave strength level Sw_level is lower than or equal to the default value, the reward calculation circuitry 141c increases an amount of change Δ1 preset as a reward. In contrast, in a case in which the reward calculation circuitry 141c judges that the sideband-wave strength level Sw_level is higher than the default value, the reward calculation circuitry 141c reduces the preset amount of change Δ1.
Similarly, the reward calculation circuitry 141c determines a reward on the basis of the switching count Sw_count arithmetically determined by the state observation circuitry 137. Specifically, the reward calculation circuitry 141c judges whether the switching count Sw_count arithmetically determined by the state observation circuitry 137 reduces from a switching count Sw_count based on a pre-update learned model PGF. In a case in which the switching count Sw_count reduces from the switching count Sw_count based on the pre-update learned model PGF, the reward calculation circuitry 141c increases an amount of change Δ2 preset as a reward. In contrast, in a case in which the switching count Sw_count increases from the switching count Sw_count based on the pre-update learned model PGF, the reward calculation circuitry 141c reduces the preset amount of change 42. In addition, a reward based on the switching count Sw_count may also be determined through comparison to a specified value, which is predetermined.
The function update circuitry 141d updates a value function on the basis of the amount of change Δ1 and the amount of change Δ2 obtained as the reward by the reward calculation circuitry 141c. Specifically, a weighting coefficient and a bias are adjusted such that the amount of change Δ1 and the amount of change Δ2 are to be maximized to an extent possible. Such adjustment updates the value function such that the switching count reduces while the strength level of sideband waves a remains in a range lower than or equal to the default value. In addition, such reduction in the switching count also causes reduction in the switching loss. The learned model is then updated on the basis of the updated value function. The value function is used for, for example, Q-learning, which is publicly known. Such update of the learned model is adjustment of the weighting coefficient and the bias for each perceptron in the neural network that forms the learned model.
The learning circuitry 141 first acquires a learned model PGF in an initial state of the motor controller 1 (step S41). The learning circuitry 141 next determines a switching pattern on the basis of the acquired learned model PGF (step S42) and the state observation circuitry 137 then acquires the strength level of sideband waves in an electric current that flows through the motor 21 at this time (step S43).
The reward calculation circuitry 141c in the learning circuitry 141 judges whether the strength level of sideband waves in an electric current that flows through the motor 21 is higher than or equal to a specified value (step S44). In a case in which the strength level of sideband waves in an electric current that flows through the motor 21 is lower than or equal to the specified value (YES in step S44), the reward calculation circuitry 141c increases a reward (step S45). In a case in which the strength level of sideband waves in an electric current that flows through the motor 21 is lower than the specified value (NO in step S44), the reward calculation circuitry 141c reduces the reward (step S46).
The reward calculation circuitry 141c judges whether the switching count in response to a voltage command reduces from the switching count Sw_count based on a pre-update learned model PGF (step S47). In a case in which the switching count in response to a voltage command reduces from the switching count Sw_count based on a pre-update learned model PGF (YES in step S47), the reward calculation circuitry 141c increases the reward (step S48). In a case in which the switching count in response to a voltage command increases from the switching count Sw_count based on a pre-update learned model PGF (NO in step S47), the reward calculation circuitry 141c reduces the reward (step S49). The function update circuitry 141d in the learning circuitry 141 updates the learned model PGF on the basis of the reward given on the basis of the strength level of sideband waves in an electric current that flows through the motor 21 and the reward given on the basis of the switching count in response to a voltage command. The processing from step S42 to step S50 is then repeated and a learned model PGF is thus obtained that forms a switching pattern with which the switching loss is further reduced.
The motor controller 1 according to Embodiment 3 also performs, similarly to Embodiments 1 and 2, the low-noise pulse operation, in which the switching pattern of the inverter 43 is adjusted such that the switching loss reduces to be less than in a case of the normal operation. Progress in degradation of the inverter 43 and the motor 21 is thus made delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
Also in Embodiment 3, the learned model generated in Embodiment 2 is updated. In Embodiment 3, every time the learned model PGF is updated, the switching loss of the inverter 43 thus reduces to be less than in a case of the learned model in Embodiment 2.
The degradation estimation circuitry 150 specifies a degraded location W_point on the basis of a resultant frequency into which a U-phase electric current Iu of a three-phase alternating electric current is converted. A case in which a target converted into a frequency is a U-phase electric current Iu is described above as an example. Alternatively, a target converted into a frequency may also be another phase electric current. The degradation estimation circuitry 150 outputs the degraded location W_point thus specified to the operation decision circuitry 170. The degraded location W_point includes information that indicates either one of the motor 21 and the inverter 43.
With reference to
The degradation notification circuitry 160 causes, according to the degraded location W_point, the user terminal 200 to turn on a notification display that indicates that either one of the motor 21 and the inverter 43 degrades.
The control circuitry 130 totals up a driving time D_time of the compressor 2. The driving time D_time is obtained by, for example, counting an actual driving time of the compressor 2 according to factors such as a gate pulse GP generated at the control circuitry 130 and a two-phase electric current Iuv among a three-phase alternating electric current. The control circuitry 130 outputs the driving time D_time to the operation decision circuitry 170.
The control circuitry 130 also performs the normal operation, the low-noise pulse operation based on the synchronous PWM control described in Embodiment 1, or the low-noise pulse operation based on the AI switching control described in Embodiments 2 and 3. The operation mode is determined by the operation-mode switching signal O_s received from the operation decision circuitry 170. The operation-mode switching signal O_s indicates either one of “1”, which indicates the normal operation, “2”, which indicates the low-noise pulse operation based on the synchronous PWM control, and “3”, which indicates the low-noise pulse operation based on the AI switching control.
The operation decision circuitry 170 switches the operation-mode switching signal O_s to either one of “1”, “2”, and “3” on the basis of the estimated degradation level W_est, the driving time D_time, the low-noise pulse-operation start signal L_s, and the degraded location W_point and then outputs the operation-mode switching signal O_s to the control circuitry 130. Specifically, in a case in which one of degradation estimation conditions described below is satisfied and an “ON” signal of the low-noise pulse-operation start signal L_s is output, the operation decision circuitry 170 sends a “2” signal or a “3” signal of the operation-mode switching signal O_s to the control circuitry 130. The first one of the degradation estimation conditions is a case in which the estimated degradation level W_est is higher than or equal to the reference degradation level x. The second one of the degradation estimation conditions is a case in which the driving time D_time is equal to a reference driving time y. The reference driving time y is preset through experimentation or other procedure such that, when a culminated driving time period of the compressor 2 is equal to the reference driving time y, a time period until which such a compressor 2 fails is substantially a predetermined time period. The predetermined time period is, for example, a time period considered sufficient for a user to complete plans and preparations such as arrangement for repair. In a case in which one of the degradation estimation conditions is satisfied, the operation decision circuitry 170 provides notification to a manager irrespective of the low-noise pulse-operation start signal L_s.
In addition, when the estimation target indicated by the degraded location W_point is the motor 21, the operation decision circuitry 170 sends a “2” signal of the operation-mode switching signal O_s to the control circuitry 130. When the control circuitry 130 receives the “2” signal of the operation-mode switching signal O_s thus input, the control circuitry 130 performs the low-noise pulse operation based on the synchronous PWM control. In contrast, when the estimation target indicated by the degraded location W_point is the inverter 43, the operation decision circuitry 170 sends a “3” signal of the operation-mode switching signal O_s to the control circuitry 130. When the control circuitry 130 receives the “3” signal of the operation-mode switching signal O_s thus input, the control circuitry 130 performs the low-noise pulse operation based on the AI switching control.
In a case in which the degradation estimation conditions are not satisfied or an “OFF” signal of the low-noise pulse-operation start signal L_s is output, the operation decision circuitry 170 sends a “1” signal of the operation-mode switching signal O_s to the control circuitry 130. When the control circuitry 130 receives the “1” signal of the operation-mode switching signal O_s thus input, the control circuitry 130 performs the normal operation.
The operation decision circuitry 170 first decides whether the degradation estimation conditions are satisfied (step S51). In a case in which the degradation estimation conditions are not satisfied (NO in step S51), the operation decision circuitry 170 sends a “1” signal of the operation-mode switching signal O_s, which indicates the normal operation, to the control circuitry 130 (step S52). In a case in which one of the degradation estimation conditions is satisfied (YES in step S51), the operation decision circuitry 170 provides notification to a manager (step S53) and judges whether the low-noise pulse-operation start signal L_s is “ON” (step S54). In a case in which the low-noise pulse-operation start signal L_s is “OFF” (NO in step S54), the operation decision circuitry 170 sends a “1” signal of the operation-mode switching signal O_s, which indicates the normal operation, to the control circuitry 130 (step S52).
In a case in which the low-noise pulse-operation start signal L_s is “ON” (YES in step S54), the operation decision circuitry 170 judges the estimation target indicated by the degraded location W_point (step S55). In a case in which the degraded location W_point indicates the motor 21 (“MOTOR 21” in step S55), a “2” signal of the operation-mode switching signal O_s, which indicates the low-noise pulse operation based on the synchronous PWM control, is sent to the control circuitry 130 (step S56). In a case in which the degraded location W_point indicates the inverter 43 (“INVERTER 43” in step S55), a “3” signal of the operation-mode switching signal O_s, which indicates the low-noise pulse operation based on the AI switching control, is sent to the control circuitry 130 (step S57).
The motor controller 1 according to Embodiment 4 also performs, similarly to Embodiments 1 and 3, the low-noise pulse operation, in which the switching pattern of the inverter 43 is adjusted such that the switching loss reduces to be less than in a case of the normal operation. Progress in degradation of the inverter 43 and the motor 21 is thus made delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
The motor controller 1 according to Embodiment 4 is also configured to judge the degraded location on the basis of an electric current output to the motor 21. The motor controller 1 according to Embodiment 4 further switches, for the corresponding one of the degraded locations, the low-noise pulse operation based on the synchronous PWM control and the low-noise pulse operation based on the AI switching control. Incidentally, the synchronous PWM control determines switching on the basis of a basic wave frequency, which is also referred as a driving rotation frequency, and is thus suited to lower noises in driving of the motor 21. In contrast, the AI switching control also counts the carrier frequency, that is, sideband waves in a high frequency around the basic wave frequency, which is also referred as a driving rotation frequency, and is thus suited to lower noises related to the inverter 43. As described above, the low-noise pulse operation suited to the degraded location is performed and progress in degradation of the inverter 43 and the motor 21 is thus made further delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus further reduced or eliminated until time elapses to a scheduled maintenance checkup.
The control circuitry 130 and the degradation estimation circuitry 150 of the motor controller 1, the power source 3, and the electric-power converter device 4 are, as the control unit 10, installed in a control box. Embodiment 5 is described with a case in which the compressor 2 is installed in an air-conditioning apparatus and the air-conditioning apparatus is installed in a facility such as a building. The control unit 10 is installed outside a facility such as on a roof of a building. The degradation estimation circuitry 150 in the control unit 10 sends an estimated degradation level W_est to the degradation notification circuitry 160 and the operation decision circuitry 170. In addition, the control circuitry 130 in the control unit 10 receives an operation-mode switching signal O_s from the operation decision circuitry 170.
The degradation notification circuitry 160 is, for example, as a functional section of a management panel 400 installed indoors such as inside a management room or other facility, software or other programs installed in a controller of the management panel 400. To the management panel 400, a display and operation buttons are provided, by which a user is allowed to confirm and input a setting for behavior of an air-conditioning apparatus. The management panel 400 may also have a touch display rather than combination of a display and operation buttons. The degradation notification circuitry 160 establishes wired or wireless communication with the control unit 10 and receives the estimated degradation level W_est from the degradation estimation circuitry 150 in the control unit 10. The degradation notification circuitry 160 causes, according to the received estimated degradation level W_est, the display to turn on a notification display that indicates that a device on which the motor 21 is mounted degrades. The display of the management panel 400 is an example of “a display device” of the present disclosure.
The operation decision circuitry 170 is, for example, as a functional section of a server device, software or other programs installed in the server device. The operation decision circuitry 170 establishes communication via the Internet with the control unit 10 and receives the estimated degradation level W_est from the degradation estimation circuitry 150 in the control unit 10. The operation decision circuitry 170 also sends the operation-mode switching signal O_s to the control unit 10. Specific behavior is the same as described in Embodiments 1 to 4. In addition, the operation decision circuitry 170 may also be a functional section in a cloud server rather than a functional section in a physical server.
The motor control system 1A according to Embodiment 5 also performs, similarly to Embodiments 1 and 4, the low-noise pulse operation, in which the switching pattern of the inverter 43 is adjusted such that the switching loss reduces to be less than in a case of the normal operation. Progress in degradation of the inverter 43 and the motor 21 is thus made delayed. With a device on which the motor 21 is mounted, a likelihood of downtime unpredictable for a user is thus reduced or eliminated until time elapses to a scheduled maintenance checkup.
Each embodiment presently disclosed is an example at all points and should be considered nonlimiting. The scope of the present disclosure is not specified by the description made above but is specified by the scope of claims. It is also specified that the scope of the present disclosure includes equivalence in meaning to the scope of claims and all changes within the scope of the claims. In addition, it is also specified that forms described in embodiments and modifications are established, to an extent possible, both in a case in which the forms are singly used and in a case in which the forms are combined with each other. For example, in each embodiment, a period before which the inverter 43 or the compressor 2 is usually replaced, a timing of replacement recommend on the basis of an estimated degradation level W_est and a reference degradation level x, or a timing of replacement recommend on the basis of a driving time D_time and a reference driving time y may also be presented.
In addition, in each embodiment, a mobile terminal, which a user carries, may also be configured to turn on a notification display. In this case, the degradation notification circuitry 160 is dedicated software installed in the mobile terminal, which the user carries. In this case, the user is allowed to recognize degradation of the inverter 43 and the motor 21 even from a remote location. Arrangement for repair and maintenance work are thus speeded up. In addition, the display of the mobile terminal is an example of “a display device” of the present disclosure.
In addition, a method of acquiring an estimated degradation level W_est in Embodiment 1 may also be changed as follows.
In addition, in Embodiment 2, a learned model PGF may also be generated for, in addition to reduction in switching loss, another purpose on the basis of the electric current Iuv, the bus voltage Vdc, the refrigerant pressure Rp, the refrigerant flow rate Rfr, the ambient temperature Tmp, and the ambient humidity Hud. Such a purpose other than reduction in switching loss is, for example, either one of a driving sound, oscillation, and an electric current harmonic of the compressor 2 and a voltage applied to the inverter 43. In this case, the electric current Iuv, the bus voltage Vdc, the refrigerant pressure Rp, the refrigerant flow rate Rfr, the ambient temperature Tmp, and the ambient humidity Hud are used as input data to the learned model PGF.
In addition, in Embodiment 5, a form in which the operation decision circuitry 170 and the degradation notification circuitry 160 are located outside the control unit 10, which is formed by the control circuitry 130, the degradation estimation circuitry 150, the power source 3, and the electric-power converter device 4, is referred to as the motor control system 1A. The motor control system is, however, not limited to the form described above. The motor control system is only required to have either one of the degradation estimation circuitry 150, the degradation notification circuitry 160, and the operation decision circuitry 170 outside the control unit 10 formed by the control circuitry 130, the power source 3, and the electric-power converter device 4. In this case, the degradation estimation circuitry 150, the degradation notification circuitry 160, or the operation decision circuitry 170 is, for example, software or other programs as a functional section of a hardware device or a CPU, which is different from a motor controller on which the control circuitry 130 is mounted, or a server device such as a cloud server. In addition, with the motor control system, a feature of the motor controller 1 described in Embodiments 1 to 4 may also be combined.
In addition, in each embodiment, according to an extent to which an estimated degradation level exceeds the reference degradation level, the operation decision circuitry 170 may also change a content to be notified to the management terminal 300. Similarly, the degradation notification circuitry 160 may also change a notification display to be turned on on a display device. For example, the further the estimated degradation level exceeds the reference degradation level, the larger the number of notification may also be made or the shorter a notification interval may also be made. In addition, a text to be displayed on the management terminal 300 or a display device may also be changed such that a sense of unease is felt over a likelihood that a device on which the motor 21 is mounted may degrade.
In addition, in Embodiments 2 to 5, a case is described above in which the learning circuitry 141 in the control circuitry 130 has the data acquisition circuitry 141a configured to acquire learning data that includes a voltage command value in an arbitrary cycle and the switching pattern in a previous cycle, which is immediately prior to the arbitrary cycle, and the model generation circuitry 141b configured to generate a learned model used to infer the switching pattern in the arbitrary cycle by use of the learning data. From the learning circuitry 141, however, the data acquisition circuitry 141a and the model generation circuitry 141b may also be omitted. Specifically, a learned model may also be stored in advance in the memory circuitry 180 in the motor controller 1 or the motor control system 1A. The learned model stored in the memory circuitry 180 is, similarly to one described in Embodiments 2 to 5, one used to infer the switching pattern in an arbitrary cycle by use of learning data that includes the voltage command value in the arbitrary cycle and the switching pattern in a previous cycle, which is immediately prior to the arbitrary cycle. The learned model stored in the memory circuitry 180 is, for example, one obtained through a learning process performed by a computer provided outside the motor controller 1 or the motor control system 1A.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/042728 | 11/22/2021 | WO |
