Patent Application
20240313687
This application claims priority benefit of Japanese Patent Application No. JP 2023-038908 filed in the Japan Patent Office on Mar. 13, 2023. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.
The present disclosure relates to a motor driver circuit.
Linear motors (linear actuators) that position a target object are used for various pieces of electronic equipment and industrial machines. A voice coil motor is one kind of the liner motors and can control the position of a movable element according to a supplied drive current. A drive circuit of the voice coil motor executes feedback control of a current that flows in the voice coil motor, to cause the current to come close to a target current that defines a target position.
The drive system of the motor is roughly classified into the pulse width modulation (PWM) drive system and the linear drive system. The PWM drive system is excellent in efficiency although being inferior in accuracy of positioning. The linear drive system is excellent in the accuracy of positioning although having high power consumption. Among motor driver circuits, there is one in which switching between the PWM drive system and the linear drive system is possible.
An example of the related art is disclosed in Japanese Patent Laid-open No. 2020-54110.
An outline of several illustrative embodiments of the present disclosure will be described. This outline explains several concepts of one or a plurality of embodiments in a simplified manner for the purpose of allowing basic understanding of the embodiments as an introduction of a detailed explanation to be described later, and does not limit the extent of the technology or the disclosure. This outline neither gives a comprehensive outline of all embodiments that are conceivable nor intends to identify important factors of all embodiments or delimit the range of a part or all of modes. For convenience, “one embodiment” is used to refer to one embodiment (embodiment example or modification example) or a plurality of embodiments (embodiment examples or modification examples) disclosed in the present specification in some cases.
A motor driver circuit according to one embodiment is a motor driver circuit in which switching between a pulse width modulation mode and a linear mode is possible. The motor driver circuit includes an output stage including a high-side transistor and a low-side transistor that are connected to a coil of a motor, a control circuit that generates a control signal to give an instruction on a drive voltage to be applied to the coil, a pulse width modulation drive circuit that becomes active in the pulse width modulation mode and generates a pulse signal having a duty cycle according to the control signal, to execute switching of the high-side transistor and the low-side transistor, and a linear drive circuit that becomes active in the linear mode and controls a gate voltage of the high-side transistor and the low-side transistor to cause the drive voltage to come close to a target voltage according to the control signal. The linear drive circuit includes a first current source driver that sources a first source current to a gate of the high-side transistor, a first current sink driver that sinks a first sink current from the gate of the high-side transistor, a second current source driver that sources a second source current to a gate of the low-side transistor, a second current sink driver that sinks a second sink current from the gate of the low-side transistor, and a differential amplifier that controls the first current source driver, the first current sink driver, the second current source driver, and the second current sink driver to cause the drive voltage to come close to the target voltage according to the control signal. The current supply ability of the first current source driver and the second current source driver becomes higher than the current supply ability in normal times when a transition from the pulse width modulation mode to the linear mode is made.
According to this mode, enhancing the current supply ability of the first current source driver/second current source driver when switching from the PWM mode to the linear mode is executed makes it possible for the gate voltage of the high-side transistor/low-side transistor to rise at high speed in the case in which the gate voltage is at the low level in the immediately prior PWM mode. This can cause the gate voltage to promptly converge on the optimum voltage level and suppress fluctuation of the output current.
In one embodiment, the first current source driver may source the first source current obtained by multiplying one of differential currents generated by the differential amplifier by a first coefficient to the gate of the high-side transistor. The first current sink driver may sink the first sink current obtained by multiplying the other of the differential currents by a second coefficient from the gate of the high-side transistor. The second current source driver may source the second source current obtained by multiplying the other of the differential currents by a third coefficient to the gate of the low-side transistor. The second current sink driver may sink the second sink current obtained by multiplying the one of the differential currents by a fourth coefficient from the gate of the low-side transistor. The first coefficient and the third coefficient may become larger than the first coefficient and the third coefficient in normal times when a transition from the pulse width modulation mode to the linear mode is made.
In one embodiment, the first current source driver may include a first current mirror circuit that returns the one of the differential currents. The second current source driver may include a second current mirror circuit that returns the other of the differential currents. The mirror ratio of the first current mirror circuit and the second current mirror circuit may be switchable.
In one embodiment, the first current source driver may include a first constant current source that becomes active when a transition from the pulse width modulation mode to the linear mode is made and sources a first auxiliary source current to the gate of the high-side transistor. The second current source driver may include a second constant current source that becomes active when a transition from the pulse width modulation mode to the linear mode is made and sources a second auxiliary source current to the gate of the low-side transistor.
In one embodiment, the linear drive circuit may further include a first discharge circuit that is connected to and between a gate and a source of the high-side transistor and is allowed to be switched on and off and a second discharge circuit connected to and between a gate and a source of the low-side transistor. The first discharge circuit and the second discharge circuit may be turned on when a transition from the pulse width modulation mode to the linear mode is made.
According to this mode, turning on the first discharge circuit and the second discharge circuit when switching from the PWM mode to the linear mode is executed makes it possible for the gate voltage of the high-side transistor/low-side transistor to lower at high speed in the case in which the gate voltage is at the high level in the immediately prior PWM mode. This can cause the gate voltage to promptly converge on the optimum voltage level and suppress fluctuation of the output current.
In one embodiment, the motor may be a linear motor. In one embodiment, the linear motor may be a voice coil motor.
In one embodiment, the motor driver circuit may be monolithically integrated on one semiconductor substrate. “Monolithically integrated” includes the case in which all of constituent elements of the circuit are formed on the semiconductor substrate and the case in which major constituent elements of the circuit are integrated, and some of resistors, capacitors, and so forth may be disposed outside the semiconductor substrate for adjustment of the circuit constant. Integrating the circuit on one chip makes it possible to reduce the circuit area and keep characteristics of circuit elements uniform.
A positioning device according to one embodiment includes a linear motor and any of the above-described motor driver circuits that drives the linear motor.
A hard disk device according to one embodiment includes the above-described positioning device.
A preferred embodiment will be described below with reference to the drawings. The same or equivalent constituent elements, components, and processing illustrated in the respective drawings are given the same numeral or symbol, and overlapping description is omitted as appropriate. Moreover, the embodiment does not limit the disclosure and the technology and is an exemplification, and all characteristics described in the embodiment and combinations thereof are not necessarily essential matters of the disclosure and the technology.
In the present specification, the “state in which component A is connected to component B” includes the case in which component A and component B are directly connected physically and also the case in which component A and component B are indirectly connected with the interposition of another component that does not have a substantial influence on the electrical connection state of component A and component B or does not impair functions and effects provided by the coupling of component A and component B.
Similarly, the “state in which component C is disposed between component A and component B” includes, besides the case in which component A and component C or component B and component C are directly connected, also the case in which component A and component C or component B and component C are indirectly connected with the interposition of another component that does not have a substantial influence on the electrical connection state of the relevant components or does not impair functions and effects provided due to the coupling of the relevant components.
Further, the ordinate axis and the abscissa axis of a waveform diagram or a time chart illustrated in the present specification are made through appropriate enlargement or contraction for facilitation of understanding, and the respective waveforms illustrated are also simplified for facilitation of understanding.
The host controller 104 comprehensively controls the positioning device 100. The host controller 104 generates a position control code POS indicating a target position of the linear motor 102 and transmits the position control code POS to the motor driver circuit 200. The host controller 104 includes a microcontroller, a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC), for example.
The motor driver circuit 200 receives the position control code POS and supplies a drive current IDRV with a quantity according to the position control code POS to the linear motor 102. The linear motor 102 is, for example, a voice coil motor, and a movable element thereof is displaced by a quantity according to the drive current IDRV that flows in the linear motor 102.
Next, the configuration of the motor driver circuit 200 will be described. The motor driver circuit 200 includes a current command generating part 210, a control circuit 220, output stages 260A and 260B, and a current detecting circuit 290 and is a functional integrated circuit (IC) integrated on one semiconductor substrate.
The motor driver circuit 200 has two output terminals AOUT and BOUT. The linear motor 102 and a sense resistor Rs for current detection are connected to and between the first output terminal AOUT and the second output terminal BOUT. A voltage drop (current detection signal VCS) proportional to the drive current IDRV is generated across the sense resistor Rs. Current detection pins ISNS and KSNS are connected to the sense resistor Rs, and the current detection signal VCS is input thereto.
The current command generating part 210 generates an analog command signal VDAC indicating a target value of the drive circuit IDRV supplied to the linear motor 102. For example, the current command generating part 210 includes an interface circuit 212, a logic circuit 214, and a digital-to-analog (D/A) converter 216. The interface circuit 212 is connected to the host controller 104 and receives control data. For example, the interface circuit 212 may be an inter IC (I2C) interface or may be a serial peripheral interface (SPI). The control data from the interface circuit 212 includes the position control code POS indicating the target position of the movable element of the linear motor 102. The logic circuit 214 outputs a control code CODE based on a received code to the D/A converter 216. The control code CODE may be the same as the position control code POS received from the host controller 104 or may be a different code obtained through computation of the position control code POS. The D/A converter 216 converts the control code CODE generated by the logic circuit 214 to the analog command signal VDAC.
The configuration of the current command generating part 210 is not limited to the abovementioned one and may be a configuration that directly receives the analog command signal VDAC from the external.
The current detecting circuit 290 generates a current feedback signal VFB indicating the drive current IDRV that flows in the linear motor 102. For example, the current feedback signal VFB is represented by the following expression. k and VCMREF are freely-selected constants.
The control circuit 220 receives the current feedback signal VFB and the analog command signal VDAC and generates a control signal VCTRL. The control signal VCTRL is a command value of a drive voltage VDRV that should be applied across the linear motor 102. The control circuit 220 may be configured by a digital circuit. In this case, the control circuit 220 can be configured by a combination of a proportional-integral (PI) controller (compensator), a D/A converter, an analog-to-digital (A/D) converter, and so forth. The control circuit 220 may be configured by an analog circuit. In this case, the control circuit 220 possibly includes an error amplifier.
The motor driver circuit 200 is configured to be capable of switching between a PWM mode and a linear mode.
The first output stage 260A and the second output stage 260B have a bridge-tied load (BTL) form. The first output stage 260A receives the control signal VCTRL and generates a first drive voltage VOUTA according to the control signal VCTRL at the first output terminal AOUT. The second output stage 260B receives the control signal VCTRL and generates a second drive voltage VOUTB according to the control signal VCTRL at the second output terminal BOUT. The first drive voltage VOUTA and the second drive voltage VOUTB are in opposite phases and the drive voltage VDRV (=VOUTA−VOUTB) proportional to the control signal VCTRL is applied across the linear motor 102.
The first output stage 260A includes a first high-side transistor M1A, a first low-side transistor M2A, and a first pre-driver 270A. The first high-side transistor M1A and the first low-side transistor M2A are connected in series between a power supply line and a ground line and configure a switching circuit of a push-pull type.
The first pre-driver 270A includes a first PWM circuit 272A and a first linear drive circuit 280A. The first PWM circuit 272A becomes active in the PWM mode and controls the first high-side transistor M1A and the first low-side transistor M2A to generate the pulsed first drive voltage VOUTA having the duty cycle according to the control signal VCTRL.
The first linear drive circuit 280A becomes active in the linear mode and controls the first high-side transistor M1A and the first low-side transistor M2A to generate the first drive voltage VOUTA that linearly changes with respect to the control signal VCTRL.
The second output stage 260B has a configuration similar to that of the first output stage 260A.
The first linear drive circuit 280A includes resistors R11, R12, R13, and R14, a differential amplifier 282, a first current source driver CS11, a first current sink driver CS12, a second current source driver CS21, a second current sink driver CS22, a first discharge circuit 284, and a second discharge circuit 286.
The first current source driver CS11 sources a first source current ISRC1 to the gate of the high-side transistor M1A. The first current sink driver CS12 sinks a first sink current ISNK1 from the gate of the high-side transistor M1A.
The second current source driver CS21 sources a second source current ISRC2 to the gate of the low-side transistor M2A. The second current sink driver CS22 sinks a second sink current ISNK2 from the gate of the low-side transistor M2A.
The resistor R11 is connected to and between the inverting input node of the differential amplifier 282 and a reference voltage node VCOM. The resistor R12 is connected to and between the inverting input node of the differential amplifier 282 and the first output terminal AOUT. The resistor R14 is connected to and between the non-inverting input terminal of the differential amplifier 282 and the ground. The control signal VCTRL is input to the non-inverting input terminal of the differential amplifier 282 through the resistor R13. The first current source driver CS11, the first current sink driver CS12, the second current source driver CS21, and the second current sink driver CS22 operate according to differential currents Idiff1 and Idiff2 generated by the differential amplifier 282.
By the differential amplifier 282, the first current source driver CS11, the first current sink driver CS12, the second current source driver CS21, and the second current sink driver CS22 are controlled to cause the first drive voltage VOUTA to come close to a target voltage according to the control signal VCTRL.
The first current source driver CS11 and the second current source driver CS21 are each configured in such a manner that the current supply ability thereof can be switched to at least two stages. The current supply ability of the first current source driver CS11 and the second current source driver CS21 is controlled by the logic circuit 214. When a transition from the PWM mode to the linear mode is made, the logic circuit 214 makes the current supply ability of the first current source driver CS11 and the second current source driver CS21 higher than the current supply ability in normal times during a predetermined period of time (referred to also as a clamp period). For example, the predetermined period of time is several hundreds of nanoseconds to several microseconds and may be set to 1 μs, for example.
The control of the current supply ability can be executed as follows. For example, the first current source driver CS11 sources the first source current ISRC1 obtained by multiplying one of the differential currents generated by the differential amplifier 282, i.e., the differential current Idiff2, by a first coefficient K1 to the gate of the high-side transistor M1A. Further, the first current sink driver CS12 sinks the first sink current ISNK1 obtained by multiplying the other of the differential currents, i.e., the differential current Idiff1, by a second coefficient K2 from the gate of the high-side transistor M1A.
The second current source driver CS21 sources the second source current ISRC2 obtained by multiplying the other of the differential currents, i.e., the differential current Idiff1, by a third coefficient K3 to the gate of the low-side transistor M2A. The second current sink driver CS22 sinks the second sink current ISNK2 obtained by multiplying the one of the differential currents, i.e., the differential current Idiff2, by a fourth coefficient K4 from the gate of the low-side transistor M2A.
In one embodiment example, the first coefficient K1 and the third coefficient K3 are made larger than those in normal times when a transition from the pulse width modulation mode to the linear mode is made. This increases the current supply ability.
The first discharge circuit 284 is connected to and between the gate and the source of the first high-side transistor M1A. The second discharge circuit 286 is connected to and between the gate and the source of the first low-side transistor M2A. The first discharge circuit 284 and the second discharge circuit 286 include a voltage clamp circuit and clamp the gate-source voltage at a predetermined voltage Vclp in the on-state. The first discharge circuit 284 and the second discharge circuit 286 can be switched on and off and are controlled by the logic circuit 214. The logic circuit 214 sets the first discharge circuit 284 and the second discharge circuit 286 to the on-state during a predetermined period of time when a transition from the PWM mode to the linear mode is made. It is preferable that the predetermined voltage Vclp be set in the vicinity of the convergence range of the gate voltage in the linear mode.
The first current source driver CS11 includes current mirror circuits CM1 and CM2. The current mirror circuit CM1 includes transistors M34 and M35 and returns the one of the differential currents Idiff, i.e., the differential current Idiff2, generated by the differential amplifier 282. The current mirror circuit CM2 includes transistors M37 and M38 and returns the output current of the current mirror circuit CM1 to generate the first source current ISRC1.
When the mirror ratios (current amplification factors) of the current mirror circuits CM1 and CM2 are defined as α1 and α2, respectively, the following expressions hold.
It suffices to make at least one of α1 and α2 variable for switching the current amplification factor K1 as described above. In the example of
The first current sink driver CS12 includes current mirror circuits CM3, CM4, and CM5. The current mirror circuit CM3 includes transistors M31 and M33 and returns the other of the differential currents Idiff, i.e., the differential current Idiff1, generated by the differential amplifier 282. The current mirror circuit CM4 includes transistors M39 and M40 and returns the output current of the current mirror circuit CM3. The current mirror circuit CM5 includes transistors M41 and M42 and returns the output current of the current mirror circuit CM4 to generate the first sink current ISNK1.
When the mirror ratios (current amplification factors) of the current mirror circuits CM3, CM4, and CM5 are defined as α3, α4, and α5, respectively, the following expressions hold.
The second current source driver CS21 includes current mirror circuits CM6 and CM7. The current mirror circuit CM6 includes the transistors M31 and M32 and returns the other of the differential currents Idiff, i.e., the differential current Idiff1, generated by the differential amplifier 282. The current mirror circuit CM7 includes transistors M43 and M44 and returns the output current of the current mirror circuit CM6 to generate the second source current ISRC2.
When the mirror ratios (current amplification factors) of the current mirror circuits CM6 and CM7 are defined as α6 and α7, respectively, the following expressions hold.
It suffices to make at least one of α6 and α7 variable for switching the current amplification factor K3 as described above. In the example of
The second current sink driver CS22 includes a current mirror circuit CM8. The current mirror circuit CM8 includes transistors M34 and M36 and returns the one of the differential currents Idiff, i.e., the differential current Idiff2, generated by the differential amplifier 282, to generate the second sink current ISNK2.
When the mirror ratio (current amplification factor) of the current mirror circuit CM8 is defined as α8, the following expressions hold.
The switches SW31 and SW32 are turned on in the PWM mode and are turned off in the linear mode.
Similarly, the second discharge circuit 286 includes a switch SW5 and a diode D5 connected in series between the gate and the source of the first low-side transistor M2A.
In
The above is the configuration of the motor driver circuit 200. Next, the operation thereof will be described.
The drive current IDRV is illustrated at the uppermost stage of
A clock time t0 represents the timing of the switching from the PWM mode to the linear mode. AOUT and BOUT are both at the low level immediately prior to the switching.
In the comparative technique, the rate of rise of the output voltages VOUTA and VOUTB is lower than in the embodiment. Thus, the drive current IDRV gently rises toward a target level. In contrast, in the present embodiment, the rate of rise of the output voltages VOUTA and VOUTB is higher than that in the comparative technique. As a result, the drive current IDRV can be made to rapidly converge on the target level.
AOUT and BOUT are both at the low level immediately prior to the mode switching at the clock time t0. Thus, the gate-source voltages LGA and LGB of the low-side transistors M2A and M2B are both at the high level, and the gate-source voltages HGA-AOUT and HGB-BOUT of the high-side transistors M1A and M1B are both at the low level.
The gate voltage of the low-side transistors M2A and M2B lowers at high speed due to the discharge circuits 284 and 286 in both the embodiment and the comparative technique. However, in the comparative technique, the rise of the gate voltage of the high-side transistors M1A and M1B is slow. Due to this, the rise of the output voltages AOUT and BOUT is slow.
In contrast, in the present embodiment, the current supply ability of the first current source driver CS11 and the second current source driver CS21 becomes higher during the clamp period. Therefore, the rise of the gate voltage of the high-side transistors M1A and MIB becomes faster than in the comparative technique. Owing to this, the rise of the output voltages AOUT and BOUT becomes faster, and the length of time taken for the drive current IDRV to converge on the target level is shortened.
Here, LGA, LGB, HGA-AOUT, and HGB-BOUT all converge on substantially the same voltage level Vclp that depends on the first discharge circuit 284 or the second discharge circuit 286. Setting this voltage level Vclp in the vicinity of the convergence range of the gate-source voltage in the linear mode makes it possible to cause the feedback control in the linear mode to converge on a stable state in a short period of time.
Next, a modification example of the motor driver circuit 200 will be described.
The method for enhancing the current supply ability of the first current source driver CS11 and the second current source driver CS21 is not limited to that described in the embodiment.
During the clamp period, the first source current ISRC1 becomes larger by the amount of auxiliary current IAUX. As a result, the charging speed of the gate capacitance of the first high-side transistor M1A is increased, and thus, the gate voltage can be raised in a short period of time.
The second current source driver CS21 has a configuration similar to that of the first current source driver CS11.
The seek motor 912 is a voice coil motor. The motor driver circuit 200 according to the embodiment is incorporated in the motor driver circuit 920 and drives the seek motor 912. The seek motor 912 positions the head 906 through the swing arm 904.
In the present disclosure, the configuration and type of the linear motor that is the driving target are not particularly limited to any kind. For example, the present disclosure can be applied also to driving of a voice coil motor of a spring return system and other linear actuators. Alternatively, the motor of the driving target may be a spindle motor.
The use purpose of the positioning device 100 is also not limited to the hard disk device, and the positioning device 100 can be applied also to a positioning mechanism for a lens of a camera and so forth.
The present specification discloses the following technology.
A motor driver circuit in which switching between a pulse width modulation mode and a linear mode is possible, the motor driver circuit including:
The motor driver circuit according to item 1, in which
The motor driver circuit according to item 2, in which
The motor driver circuit according to item 1, in which
The motor driver circuit according to any one of items 1 through 4, in which
The motor driver circuit according to any one of items (1) through 5), in which
The motor driver circuit according to item 6, in which
The motor driver circuit according to any one of items (1) through (7), in which
A positioning device including:
A hard disk device including:
According to a certain mode of the present disclosure, the followability of the output current when switching from the PWM drive system to the linear drive system is executed can be improved.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-038908 | Mar 2023 | JP | national |
