BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a representative motor speed control system according to the present invention;
FIG. 2 is a schematic diagram of a controller;
FIG. 3 is an explanatory view illustrating the principle of operation of a pulse interval determining device;
FIG. 4(A) is a schematic circuit diagram of a motor drive circuit;
FIG. 4(B) is an explanatory view illustrating a gate pulse adjuster;
FIG. 5 is a schematic perspective view of an encoder;
FIG. 6(A) is a schematic block diagram of a known motor speed control system;
FIG. 6(B) is a schematic view illustrating how a pulse interval is determined by the known system; and
FIG. 7 is a block diagram of another known control system.