Multi-bit memory technology (MMT) and cells

Information

  • Patent Application
  • 20080081410
  • Publication Number
    20080081410
  • Date Filed
    October 02, 2006
    17 years ago
  • Date Published
    April 03, 2008
    16 years ago
Abstract
As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell is approaching its scaling limitations, multi-bit storage in a single memory cell has become the norm. The use of a Nitride layer or a silicon-nodule layer capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer.
Description

DESCRIPTION OF DRAWINGS


FIG. 1. Cross section along the diffusions of a Prior art NROM or Mirror Bit cell storing two bits of data



FIG. 2. Cross section through the storage element across the cell of the Prior art NROM or Mirror Bit cell in FIG. 1.



FIG. 3. Cross section along the diffusions of a MMT-1 cell, a two bit programmable cell with optimized select/program elements and storage element having external diffusion contacts.



FIG. 4. Cross section across the cell in FIG. 3 across the cell showing the programming element.



FIG. 5. Cross section along the diffusions of a MMT-2 cell, a four bit programmable cell with optimized select/program elements and storage element with buried diffusion contacts



FIG. 6. Cross section across the cell in FIG. 5 across the cell showing the programming element.



FIG. 7. Cross section along the diffusions of a MMT-3 cell, a four bit programmable cell with optimized select/program elements and storage element with buried diffusion contacts with MIM Erase capability



FIG. 8. Cross section across the cell in FIG. 8 across the cell showing the programming element.



FIG. 9. Cross section along the diffusions of a MMT-4 cell, a four bit programmable cell with high current programming for two of the bits and low current programming for the other two-smaller cell size.



FIG. 10. Cross section across the cell in FIG. 9 across the cell showing the programming element.



FIG. 11. Cross section along the diffusions of a MMT-5 cell, a four bit programmable cell with high current programming for two of the bits and low current programming for the other two, with MIM erase capability.



FIG. 12. Cross section across the cell in FIG. 11 across the cell showing the programming element.



FIG. 13. Cross section along the diffusions of a MMT-6 cell having “m” data bit storage capability using the low current programming.



FIG. 14. Cross section along the diffusions of a MMT-6 cell having “m” data bit storage capability using the low current programming, with single Oxide Nitride-Oxide gate dielectric for storage elements and select/program elements.



FIG. 15. Cross section along the diffusions of a MMT-6 cell having “m” data bit storage capability using the low current programming, with MIM erase capability.





EXPLANATION OF NUMBERING AND LETTERING IN THE FIGURES FOR TYPICAL IMPLEMENTATION OF THE TECHNOLOGY

Prior Art Mirror Bit Cell (FIG. 1, and FIG. 2)

    • 1. Diffusion 1 (S/D)
    • 1a. Diffusion 2 (S/D)
    • 3. Channel
    • 4. Oxide (SiO2)
    • 5. Well diffusion in Silicon
    • 6. Nitride layer or Silicon-nodule layer
    • 7. Oxide
      • Note: Layer 4,6 and 7 together form an ONO layer or in the alternate case the OsnO layer.
    • 8. Isolation
    • 9. Poly Silicon layer Control gate
    • 10. Location of storage of Bit 1
    • 11. Location of Storage of Bit 2


Disclosed Multi-bit Memory Technology Cells

MMT-1 Cell, (FIG. 3, and FIG. 4) MMT-2 Cell, (FIG. 5 and FIG. 6), MMT-3, (FIG. 7 and FIG. 8), MMT-4 Cell, (FIG. 9 and FIG. 10) MMT-5, (FIG. 11 and FIG. 12), MMT-6, (FIG. 13) and MMT-8, (FIG. 15)

    • Note.1: In the case of MIM erase cell MMT-3, the Control gate is replaced by the MIM stack comprising of Collection Grid electrode, Barrier layer and the Injector Electrode.
    • Note.2: Each number with letter combination denotes an element REGION in the cell.
    • 1. Well in Silicon Substrate
    • 2. 2x. Diffusions
    • 3. 3x. Isolation Oxide
    • 4. 4a, 4b, 4c, 4d. 4m. 4n. Integrated channel under each element
    • 5. 5b, 5d. 5n Gate oxide
    • 5a. 5c. 5m. Silicon Dioxide on silicon
      • (2nd oxide of the ONO or OsnO storage element)
    • 6a. 6c. 6m Silicon Nitride Storage layer or alternately silicon-nodule layer
      • (Nitride storage layer of ONO storage element)
    • 7a. 7c. 7m. Silicon Dioxide
      • (1st oxide of the ONO or OsnO storage element)
    • 8a. 8c. 8m. Control element (control gate layer)
    • 9. 9b. 9d. 9n Select/Program element (select/program gate layer)
    • 10a. 1st bit storage location
    • 11a. 2nd bit storage location
    • 10c. '3rd bit storage location
    • 11c. 4th bit storage location
    • 10m. mth bit storage location.
    • 11m. (m+1)th bit storage location.
    • 18a. 18c. 18m. Collection Grid electrode of MIM
      • (bottom layer of MIM stack)
    • 19a. 19c. 19m. Barrier (middle layer of MIM stack)
    • 20a. 20c. 20m. Injector electrode (top layer of MIM stack)


MMT-7 Cell, FIG. 14

    • 1. Well in Silicon Substrate
    • 2. 2x. Diffusion
    • 3. 3x. Isolation Oxide
    • 4. 4a, 4b, 4c, 4d. 4m. 4n. Integrated channel under each element
    • 5. Silicon Dioxide on silicon
      • (2nd oxide of the ONO storage element)
    • 6. Silicon Nitride Storage layer
      • (Nitride storage layer of the ONO storage element)
    • 7. Silicon Dioxide (Nitride Oxide)
      • (1st oxide of the ONO storage element)
    • 8a. 8c. 8m. Control element (control gate layer)
    • 9. 9b. 9d. 9n Select/Program element (select/program gate layer)
    • 10a. 1st bit storage location
    • 11a. 2nd bit storage location
    • 11c. 3rd bit storage location
    • 11c. 4th bit storage location
    • 10m. mth bit storage location.
    • 11m. (m+1)th bit storage location.


DESCRIPTION OF INVENTION

Multi-bit cells with storage in trap locations in Nitride and in potential wells in isolated (discrete) silicon nodules are disclosed. The cells are all capable of being programmed by hot electron programming (Channel Hot Electron or CHE), the preferred being a modified low current hot electron programming method, and erased by one of the two methods, FN tunneling from the storage sites due to applied potential or a lower voltage alternate disclosed method of erase that is by use of MIM (Metal-Insulator-Metal) for generating carriers of the opposite type from those used for program, and collection of part of the carriers so generated by the storage locations to erase the cells. This method used for energetic carrier generation is called the Tunnel-Gun or TG method. It should be noted that the TG method is capable with the right voltage application and choice of electrodes of generating either the positive or negative charge carriers. The application described is a typical one where the cell described is a n-channel cell where the erase is by generating energetic holes for collection in the storage layer for erase of the cell. Multiple cells have been disclosed using these methods of program and erase, that are capable of storing two bits to a larger number of bits in a cell.



FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 13 and FIG. 14 form a first group of cells that are erased by Fouler-Nordheim Tunneling (FN Tunneling) and have low current programming by Channel Hot Electrons (CHE).



FIG. 7, FIG. 8, and FIG. 15 form a second group of cells that are erased by use of MIM (Metal-Insulator-Metal) method and programming by the low current CHE. The MIM method of erasure is used to generate carriers having the opposing type of charge, typically holes with positve charge, as the carriers used during programming, typically negatively charged carriers or electrons, with the CHE programming method.



FIG. 9, FIG. 10, FIG. 11 and FIG. 12 form a third group that are examples of multi-bit cells that use a combination of the High current CHE programming of the prior art at the junctions and low current CHE programming disclosed in the current application and hence are not optimum cells for low power applications. These cells will form a smaller size cells but with more complex peripheral programming circuitry. Once the disclosed low current method for the cells have been understood it will be possible for any individual technologist to implement these cells combining the prior art with the disclosed method. FIG. 9 and 10 are for cells which are erased using FN-Tunneling FIG. 11 and 12 are cells which are erased with MIM method of erase. These are provided as an example of combining the prior art technology with the proposed technology and no detailed explanation of the cell operation is provided.


In order to simplify the description of the technology and the cells, the 4 bit cell shown in FIG. 5 and FIG. 6 (Group 1 cells) in the case of FN Tunneling erase cell and FIG. 7 and FIG. 8 (Group 2 cells) in the case of MIM method of erase are chosen. The explanation in these cases are easily extendable to each of the group of cells, to which these cells belong.



FIG. 5 and FIG. 6 show a 4 bit memory cell having three select/program gates and two storage gates, deposed in an alternating fashion over and integrated channel comprising the channel regions (4,4a,4b,4c, and 4d) under the gates, between two diffusion regions (2, 2x) forming the Source/Drain diffusions. The select/program gates separate the storage gates from each other and also keep them away from the diffusions. The storage gate in these memory cells consist of an ONO storage element, or alternately an OsnO storage element over which is a conductive, typically poly-silicon, control element or control gate layer is deposed.


The ONO storage element is made up of a stack comprising a silicon dioxide layer on silicon (5a or 5c), a Nitride layer (6a, or 6c) and a second Oxide layer (7a or 7c). The Nitride layer forms the storage layer and the charge carriers during programming are stored gets trapped in the trap sites that exist in the Nitride layer. Since the Nitride layer is non conductive the stored charge remains localized and does not spread throughout the storage layer. The two oxide layers form barrier layers on top and bottom, to prevent unwanted charge loss or accumulation in the Nitride.


In the alternate silicon-nodule storage, the OsnO storage element replaces the ONO storage element in the storage gates of the cells in the group, except for the cell in FIG. 14. The OsnO layer is also made up of a stack comprising an oxide layer on silicon (5a or 5c), a silicon-nodule layer (6a or 6c) having a few layers of discrete silicon nodules separated by thin barrier oxide, and a second oxide layer (7a or 7c). The silicon-nodule layer forms the storage layer where the charge carriers are stored in the isolated potential wells that exist in each nodule. The inter nodule barrier keeps the charge localized by preventing distributed by conduction. The top and bottom oxides form barrier layers to prevent unwanted charge loss or accumulation in the silicon-nodule storage layer.


In the typical implementation shown the storage gates have the storage element as the gate dielectric under a poly silicon conducting control gate layer while the select/control gates have an oxide dielectric under a poly-silicon conducting select/program gate layer.


As indicated earlier one implementation where the ONO layer cannot be replaced completely by the silicon-nodule layer is the implementation shown in FIG. 14 or similar implementations. Here a single ONO layer is used as the gate dielectric for the whole integrated channel. This use of the ONO allows the design to be implemented easily with reduced complexity in process. The disadvantages are the need for thicker than minimum gate dielectric for the select/control gates and possible residual charge in the nitride under the select/program gates affecting the performance as the number of write erase cycles are increased.


In all the cells shown there are two storage locations or storage nodes (10a to 10m and 11a to 11m) per storage element in a storage gate that can be programmed. It is also possible to only program one location per storage gate, rather than two for simplicity of operation.


Per example of the four bit cell in FIG. 5 and FIG. 6, there are four storage nodes (10a, 11a, 10c, 11c) in the two storage elements, storage element a comprising the stacked layers (5a,6a and 7a) over the channel (4a) and storage element c comprising the stacked layers (5c, 6c, and 7c) over the channel 4c, associated with the two storage gates a first storage gate (storage gate-a) and a second storage gate (storage gate-c) that comprise the respective storage elements underlying the respective conductive control gate layer or control gate element (8a and 8c). The first storage element (storage element-a) has the storage nodes (10a and 11a) and the second storage element (storage element-c) has the storage nodes (10c and 11c).


The storage gates are separated from the diffusions (source/drain diffusions) (2 and 2x) and each other by the three select/program gates, a first select/program gate (select/program gate 0) adjacent to the diffusion (2) on one side and the first storage gate on the other side, a second select/program gate (select program gate-b) separating the two storage gates (storage gate-a and storage gate-c) and a third select control gate (select control gate-d) adjacent to the diffusion (2x) and the second storage gate (storage gate-c)


The first select/program gate-0 comprise the gate oxide layer (5) over lying the channel (4) over which is deposed the conductive select/program element or select/program gate layer (9). Similarly the second select/program gate-b comprise the gate oxide layer (5b) over lying the channel (4b) over which is deposed the conductive select/program element or select/program gate layer (9b) and the third select/program gate-d comprise the gate oxide layer (5d) over lying the channel (4d) over which is deposed the conductive select/program element or select/program gate layer (9d).


The channel in silicon between the diffusions is an integrated channel that lies in the silicon beneath the gate dielectrics of the set of gates, in order, select/program gate-0, storage gate-a, select/program gate-b, storage gate-c and select/program gate-d.


The second group of cells, represented by FIG. 7 and FIG. 8 are similar to the FIG. 5 and FIG. 6 except in that, in the storage gate, the conductive control gate layer is replaced by a stack making up the electrodes of an MIM structure for generating energetic carriers or the TG. The TG stack comprise a conductive grid electrode (18a, 18c), typically doped poly-silicon, a barrier layer (19a, 19c), typically silicon dioxide, and an injector layer (20a,20c). The TG stack comprising 18a, 19a, and 20a, replace the control gate element 9a in the storage gate-a and the MIM stack comprising 18c, 19c, and 20c, replace the control gate element 9c in storage gate-c of the FIG. 5. In normal operation except during erase the TG stack as a whole act similarly to the control gate layer for the storage gates.


Operation:


Programming:


The operation of the MMT cells are also explained using the four bit cells of FIG. 5 and FIG. 7.


Taking the FIG. 5, the cell has four storage nodes that can be programmed. They are the 10a, and 11a that are part of the storage gate-a and 10c and 11c that belong to the storage gate-c. If the cell uses the traps in a Nitride storage layer in an ONO storage element, potential wells in silicon-nodules in an OsnO storage layer, in order to program the storage node 10a the selected storage gate is storage gate-a and the selected select/program gate is the select/program gate-0. The following steps are necessary:


a. The diffusion 2x is made the drain diffusion and diffusion 2 is made the source diffusion. A reasonably high voltage of sufficient magnitude, typically 3 to 7 V is applied to the drain diffusion closer to opposing end of the storage element where the storage node being programmed reside, that is for programming node 10a the drain voltage is applied to drain 2x.


b. The unselected storage gate (storage gate-c) has high voltages applied to it through the control gate layer (8c) such that this gates has voltage sufficient to fully turn on the channel (4c) under the gate irrespective of whether the storage nodes (10c and 11c) in the nitride storage layer (6c) of the storage gate have been previously programmed or left un-programmed, typically in the range of 3 to 5 V.


c. The unslected select/program gates (select/program gate-b and d) have enough voltage applied to them through the control gate layer (9b and 9d) to turn them, namely the channel regions (4b and 4d) controlled by them fully on, typically again in the 3 to 5V range.


d. A high collection voltage is applied to the control gate layer (8a) of the selected storage element where in the storage node (10a) reside, turning on the channel under the storage element. The typical voltages are in the 3 to 8V range.


e. Apply a voltage, on the selected select/program gate, adjacent the storage node (10a), through the selected control gate layer (9), such that the channel (4) of the select/program gate is just turned on, typically in the 0.3 to 1V range.


The channel of the selected select/program gate will hence operate in a pinched off condition allowing limited current flow. Electrons from the source (2) will flow to the drain limited by the gate potential on the selected select/program gate layer (9) This will allow the carriers, typically electrons, in the channel to achieve saturation velocity or close to it. When they encounter the high field at depletion region at the selected node due to the drain voltage passed through by the fully turned on unselected storage and select/program gates, the carriers will achieve the hot carrier status in the high field and enable CHE programming at the node due to the existing high collection voltage on the gate. The carriers that overcome the barrier will be trapped in the discrete trap sites that exist in the Nitride layer (6a) or alternately the discrete potential wells that exist in the silicon-nodule layer (6a) at the selected storage node and be stored.


If the next bit has to be programmed on the same storage element, at the storage node 11a, the procedure is similar. The diffusion 2 which is on the opposing end of the storage element where the storage node 11a is is made the drain diffusion and the diffusion 2x is now the source diffusion. The selected storage gate is still storage gate-0 while the selected select/program gate is select/program gate-b. The unselected gates are biased with high voltages to provide a low resistance path for the current and minimum voltage drops in the channel under the gates. The selected storage gate is biased with high voltage on the control gate layer, to enable collection of the hot-carriers generated adjacent the storage node in depletion region of the channel under the influence of the drain voltage. The hot carriers are generated due to the velocity saturated carriers produced by the pinched off channel of the turned on select program gate which is in a low current saturation condition due to the low turn on voltage applied the select/program gate layer of the select/program gate-b and the depletion field due to the drain voltage. Part of these carriers with the correct velocity component will be accelerated towards the barrier oxide by the collection voltage applied to the control gate layer of the storage gate and will overcome the barrier to get collected in the storage element at the selected storage node.


Erasing:


The erase uses two methods. One is the standard Fouler-Nordheim (FN) tunneling method as applied to FIG. 5, that applies a high voltage across the storage element, that is of sufficient magnitude and is in a direction that allows the charge to be extracted from the traps in the Nitride or alternately the potential wells in the silicon-nodule layer and be removed by tunneling through the barrier, there by erasing the data. This is done, typically by applying a negative high voltage to the control gate layer (8a and 8c), to generate the necessary high voltage gradient across the storage layer (6a and 6c) to erase the cell. In a typical implementation the select gates are held in the off state.


The FN tunneling is a well known phenomena but it has been found that this is not the best way to erase the Nitride or the silicon-nitride based cells. This is due to the fact that FN tunneling requires very high voltage gradients to extract the charge especially from the traps and cause them to tunnel out through the barrier oxide. A better erase method is by generating carriers of the opposite charge which can the be allowed to neutralize the charge in the traps and the potential wells. The prior art described uses the Band to Band tunneling in a high doped junction to create holes which are then attracted to the traps to do the erase.


The second method of erase is by use of Metal-Insulator-Metal diode method or TG method of generating the required type of carriers, which are then used to erase the data at the storage nodes that is explained by use of FIG. 7. The carriers used for erase have a charge with the opposing polarity, (typically holes in the cells shown), as the carriers used for program, (typically electrons). The TG stack or TG comprise of a thin conductive grid collector, Grid electrode, or Grid layer (18a, 18c), typically a high work function metal or a P-doped poly-silicon (for erase by holes), that has a thickness much less than the mean free path of the carriers being injected, typically in the 100 to 350A range, deposed over the storage element. A thin tunnel barrier layer (19a, 19c), typically an oxide layer of 20 to 60A, is deposed on top of the conductive Grid layer. A thicker conductive Injector Electrode or Injector layer (20a. 20c), typically P-doped Poly-silicon (for a hole injector), is deposed on top of the barrier oxide to complete the TG stack. When a voltage gradient is applied across the barrier layer, by applying a voltage, typically in the 4 to 8 V range, to the injector poly-silicon with application of a lower voltage 1 to 3V to the grid layer or grid electrode, the positive carriers from the injector electrode are able to overcome the barrier and get injected into the grid electrode. The carriers that enter the grid electrode have high energy and move through the grid electrodeake place, where carriers collide with atoms and loose energy and get collected. Since the grid electrode layer is a thin layer that has a thickness much less than the mean free path of the carriers, a portion of the carriers that enter the grid layer pass through the layer without collisions and loss of energy, such that they have enough energy to over come the oxide barrier protecting the storage layer. If a small voltage gradient exist across the storage element, these carriers that enter the storage element will drift across the barrier and get collected by the traps of the nitride storage layer or the potential wells of the silicon nodule layer, there by neutralizing the charge that exist in the storage nodes and hence erasing the data in the storage element.


In most cases the positive charge will accumulate in the storage element at all locations including the storage node during an erase. This will leave the storage gate in a depletion mode. The existence of the select gates are essential, under the depletion conditions of the storage gates, to make sure that the unselected memory cells do not conduct (provide leakage current) and create false reads during the read of a selected node of a selected cell.


Even though a hole injection based erase of an N-channel memory cell which programs using electrons is described, the TG structure is capable of generating electrons for program or erase of a memory cell. The doping of the poly-silicon and the applied voltage gradient need to be altered for this purpose as will be known to any practitioners of the art.


Reading the Cell:


Typical way to read the stored data from the cell is explained in the following description. Other ways of reading data are possible with application of different voltages to the cell gates as will become evident to those who are conversant with the memory cell and work with it.


The cell is read out by choosing a specific storage node for the read operation. In both the implementations shown, FIG. 5 and FIG. 7 the read out is accomplished in a similar fashion. In FIG. 7 the conductive layers of the TG or TG stack are used as a single layer by having the two layers (18a,20a and 18c and 20c for the two storage gates) at the same potential, that is the TG in FIG. 7 acts as the control gate layer for these cells similar to the control gate layer of the FIG. 5.


Assuming that the storage node 10a on storage layer 6a is being read out, the diffusion 2x is made the drain by applying a read voltage to it and diffusion 2 is made the source. All the select/program gates are turned on hard by applying sufficient voltage to the select/program gate layers (9,9b and 9d) to have the gates in full conduction with the channel (4, 4b and 4d) associated with the gates in the on condition, that is conducting. All the storage gates except the selected storage gates where the node (10a) exist are turned on with fully, with conducting channels (4c) in full conduction by application of a sufficiently high voltage to the control gate layer (8c) or TG stack layers (18c and 20c) of the unselected storage gate to ensure the channel is fully on even under the condition where the storage nodes (10c and 11c) are programmed. A voltage sufficient to turn on the channel (4a) of the selected storage gate is applied tom the control gate layer (8a) or the TG stack layers (18a an 20a) such that the cell is in conduction if the storage nodes (10a and 11a) are with 0 charge or in the neutral condition.


Due to the application of the drain voltage at diffusion 2x, with all gates to the selected gate in the fully on condition the voltage applied is transmitted to the edge of the selected gat with minimum resistive drop due the channel resistance. A depletion region will exist at the edge of the selected cell which will tend to mask out and reduce the effect of the state of storage node 11a and allow the read current to be mainly dependant on the node 10a. Thus allowing the 10 a node status (programmed or erased) to be read out.


Now if node 11a has to be read a similar procedure is done but diffusion 2 is made the drain diffusion while diffusion 2x is made the source diffusion. This allows the influence of node 10a to be masked by the depletion region from the voltage applied to drain 2 transmitted over to the selected storage gate edge allowing the status of node 11a to be the major influence on the read current, allowing it to be determined. Other storage nodes of the cells 10c and 11c can also be read out in a similar fashion as the nodes 10a and 11a.

Claims
  • 1. A multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data, by program and erase at storage nodes, in storage elements of the storage gates, each bit being programmed by a low current hot electron programming method.
  • 2. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions in claim 1, where in, the select/program gates and storage gates are deposed in an alternating fashion over the channel.
  • 3. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions in claim 1, where in, the select/program gates and storage gates are deposed in an alternating fashion over the channel such that the storage gates are spaced away from diffusions by having select/program gates placed adjacent to the diffusions.
  • 4. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes in storage elements of the storage gates in claim 1, where in the storage gate comprise a control gate poly-silicon over laying the ONO storage element that over lays a portion of an integrated channel region on silicon.
  • 5. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes in storage elements of the storage gates in claim 1, where in the storage gate comprise a control gate, in the form of a MIM stack made up of a grid collector and an Injector separated by a barrier layer, over laying the ONO storage element that overlays a portion of an integrated channel region on silicon.
  • 6. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes, in storage elements of the storage gates in claim 1, where in the storage gate comprise a control gate poly-silicon over laying the OsnO storage element that over lays a portion of an integrated channel region on silicon.
  • 7. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes, in storage elements of the storage gates in claim 1, where in the storage gate comprise a control gate in the form of a MIM stack made up of a grid collector and an Injector separated by a barrier layer, over laying the OsnO storage element that over lays a portion of an integrated channel region on silicon.
  • 8. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes, in storage elements of the storage gates, in claim 1, where in the storage element is ONO and comprise, a first Oxide layer, a Nitride storage layer and a second Oxide layer, where charge is stored in traps that exist in the Nitride layer.
  • 9. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data at storage nodes in storage elements of the storage gates, in claim 1, where in the storage element is OsnO comprising, a first Oxide layer, a silicon-nodule storage layer and a second Oxide layer, where charge is stored in potential wells of discrete barrier isolated silicon-nodules that exist in the silicon-nodule layer.
  • 10. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data, by program and erase at storage nodes, in storage elements of the storage gates in claim 1, where in, the programming of any bit is accomplished by a. applying a high voltage to a diffusion closer to opposing end of the storage element where the storage node being programmed reside;b. applying a high voltage to control gate over laying the storage element of all unselected storage elements, sufficient to fully turn on the channels under all the programmed and un-programmed storage gates, other than the channel underlying the selected storage element;c. applying a high collection voltage to the control gate of the selected storage element where in the storage node reside, turning on the channel under the storage element;d. applying a high voltage sufficient to turn on all the select/program gates fully except the select/program gate adjacent the storage node being programmed; ande. applying a voltage just sufficient to turn on the select/program gate adjacent the storage node.
  • 11. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data, by program and erase at storage nodes in storage layers of storage elements of the storage gates in claim 1, where in, the programming is by hot electrons generated by impact ionization due to velocity saturated carriers from a pinched off channel region of the selected select/program gate at a depletion region due to drain voltage, adjacent the selected storage node, where a few of the carriers achieve enough energy to overcome the oxide barrier and get stored in the storage layer at the storage node under the influence of a high voltage applied to the selected control gate.
  • 12. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data, by program and erase, at storage nodes in storage layers of storage elements of the storage gates in claim 1, where in, the erase is by Fouler Nordheim tunneling.
  • 13. The multi-bit non-volatile memory cell, capable of being programmed and erased, having select/program gates and storage gates, and having an integrated channel in silicon under-lying the gates, between two diffusion regions, where the cell is capable of storing multiple bits of data, by program and erase, at storage nodes in storage layers of storage elements of the storage gates in claim 1, where in, the erase is by generating carriers having the opposite charge, as the carriers stored during programming, using MIM method for collection by and storage in the storage element.
  • 14. A method of programming a multi-bit memory cell having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, such that the storage gates are separated from the diffusions by interposing a select/program gate, where the combination of control gates and select gates enable lower current programming of a storage node in a storage element in the storage gate by hot carrier programming.
  • 15. The method of programming a multi-bit memory cell having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, that allow lower current programming of a storage node in the storage element in the storage gate in claim 14, where in, the storage gate comprise an ONO storage element on silicon under laying a conductive control gate, where the programming is by storage of charge in traps existing in a Nitride storage layer forming part of the ONO storage element.
  • 16. The method of programming a multi-bit memory cell having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, that allow lower current programming of a storage node in the storage element in the storage gate in claim 14, where in, the storage gate comprise an OsnO storage element on silicon under laying a conductive control gate, where the programming is by storage of charge in potential wells existing in discrete and barrier isolated silicon-nodules existing in a silicon-nodule storage layer forming part of the OsnO storage element.
  • 17. The method of programming a multi-bit memory cell having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, that allow lower current programming of a storage node in the storage element in the storage gate in claim 14, where in, by using a high applied drain voltage and velocity saturated carriers in the channel of a selected select/program gate, that is in a pinch off condition, adjacent a selected storage gate having a selected storage node in a selected storage element, hot carriers are generated in the channel depletion region adjacent to the storage node by impact ionization, wherein a portion of such carriers have the right velocity component and are accelerated towards the storage element by the voltage applied to the control gate, to overcome the Oxide barrier and be stored in the storage node of the storage element.
  • 18. A method for erasing a multi-bit memory cell, having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, capable of being programmed and erased, where the erase is by TG using MIM diode based carrier generation method.
  • 19. The method for erasing a multi-bit memory cell, having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, capable of being programmed and erased, in claim 18, where in, the TG comprise a grid electrode, a barrier layer and an injector electrode, where the barrier layer separate the grid electrode from the injector electrode.
  • 20. The method for erasing a multi-bit memory cell, having select/program gates and storage gates deposed in an alternating fashion over an integrated channel between two diffusion regions, capable of being programmed and erased, in claim 18, where in, the TG used for erase act as the control gate during program and read.