Multi-chip solid-state image sensing device

Abstract

The solid-state image sensing device comprises N-piece photodiodes (2.sub.i) for converting optical signals to electric signals; N-piece buffers (3.sub.i) for detecting the converted electric signals, respectively; a shift register having a plurality of series-connected transfer stages (8.sub.i) for generating a read pulse (9.sub.i) on the basis of a control pulse (8.sub.i) at a predetermined timing and transmitting another control pulse (8.sub.i+) to the succeeding stage at another predetermined timing, respectively; a dummy transfer stage (6.sub.0) of the same structure as the shift register transfer stages, for transmitting a control pulse (8.sub.1) to the first shift register transfer stage in response to an external control pulse (8.sub.0) at another predetermined timing; a common output line (10); and N-piece select gates (5.sub.i) for outputting a detection signal of the buffer (3.sub.i) to the common output line on the basis of the read pulse (9.sub.i), respectively. Since control pulses (8.sub.i) applied to the respective transfer stages (6.sub.i) of the shift register can be generated internally from the dummy transfer stage and the preceding transfer stages of the shift register of the same structure, the waveforms of the control pulses can be equalized, thus improving the S/N ratio of the detected image signals.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a solid-state image sensing device, and more particularly to an image sensor provided with an amplification or impedance conversion function for each pixel (picture element).

Conventionally, an image sensor provided with an amplification or impedance conversion function for each pixel has existed as a contact image sensor. This is because the manufacturing process thereof is relatively simple and additionally to output integrating method is simple when integrated as a multichip, when compared with image sensors having other structures (e.g. OCD sensor).

In the conventional image sensors as described above, a plurality of (N.gtoreq.2) of photodiodes are formed on a single chip, for instance, and there are arranged thereon source follower buffer circuits, reset gates, select gates, a shift register composed of (N+1)-piece transfer stages of roughly the same structure, and a common output line.

In the above-mentioned conventional image sensor, the respective transfer stages (i=1, 2, . . . N+1) of the shift register are driven in response to two different-phase drive pulses .phi..sub.1 and .phi..sub.2. However, since a control pulse inputted to the first transfer stage of the shift register is supplied externally and control pulses inputted to the second and after transfer stages of the shift register are formed internally on the basis of the drive pulses .phi..sub.1 and .phi..sub.2, the control pulse applied to the first stage does not necessarily match the waveform of the control pulses applied to the second and after stages of the shift register, in general.

In the case where both the control pulses do not match the waveform of each other, a read pulse generated by the first transfer stage of the shift register is slightly different in waveform from those generated by the second and after transfer stages (i=2, . . . N+1) thereof, with the result that the output waveform (e.g. pulse rise time and fall time) of the first pixel is different from the output waveforms of the second and after pixels under the influence of these read pulses, in spite of the fact that output signals of the same waveform must be generated properly. Therefore, when data are sampled at a constant timing, the output waveform from the first pixel differs in waveform from those from the other pixels without generating uniform waveform output, thus resulting in a problem in that the S/N ratio of the image sensor is deteriorated.

SUMMARY OF THE INVENTION

Therefore, the object of the present invention is to provide a solid-state image sensing device which can improve the S/N ratio of the solid image device.

According to the first aspect of the invention, there is provided a solid-state image sensing device integrated on a semiconductor substrate, comprising: N-piece photoelectric sensing elements for converting optical signals to electric signals; N-piece signal detecting means for detecting an electric signal from the i-th (i=1, . . . N) photoelectric sensing element, respectively; a shift register having N-piece (N.gtoreq.2) series-connected transfer stages, for generating a read pulse on the basis of a control pulse at a predetermined timing and transmitting a control pulse to the succeeding transfer stage at another predetermined timing, respectively; dummy transfer means having at least one (m.gtoreq.1) transfer stage of the same structure as that of the respective transfer stages of the shift register, for transmitting a control pulse to the first transfer stage of the shift register in response to an externally applied control pulse at another predetermined timing; a common output line; and N-piece switching means for outputting a detection output of the i-th signal detecting means to the common output line, respectively on the basis of a read pulse transmitted from the i-th transfer stage of the shift register.

According to the first aspect of the solid-state image device of the present invention, the control pulses transmitted to the respective transfer stages of the shift register are formed internally by a dummy transfer stage of the same structure or the preceding transfer stages, respectively. Therefore, the read pulses outputted from the respective transfer stages are roughly the same in waveform, so that it is possible to prevent the S/N ratio of the image sensor from being deteriorated.

According to the second aspect of the invention, there is provided a multichip solid-state image sensing device, wherein L (.gtoreq.2)-piece solid image devices as described above are arranged in series and which comprises applying means for applying a pulse in phase with a control pulse transmitted from an (N-m)th transfer stage of the shift register of the i-th (i=1, . . . L-1) solid image device to the first stage of the dummy transfer stage of the (i+1)th solid image device as a control input; and an integrated output line for integratedly outputting signals outputted from the respective solid image devices via the common output lines.

According to the second aspect of the solid image device of the present invention, a pulse in phase with the control pulse transmitted from the (N-m)th transfer stage of the shift register of the i-th solid image device is applied to the first stage of the dummy transfer stage of the (i+1)th solid image device as the input control pulse. Accordingly, since the read pulses outputted from the respective transfer stages of the solid image device are roughly the same in waveform, thus enabling the prevention of deterioration of the S/N ratio of the solid image device.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram showing a first embodiment of the solid image device according to the present invention;

FIG. 2 is a timing chart for assistance in explaining the operation of the device shown in FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the solid image device according to the present invention; and

FIG. 4 is a timing chart for assistance in explaining the operation of the device shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of the solid image device according to the present invention will be described hereinbelow with reference to FIG. 1.

The image sensor of this embodiment formed on a single chip 1 is provided with a plurality (N.gtoreq.2) of photodiodes 2.sub.1 . . . 2.sub.N, buffer circuits (e.g. source follower) 3.sub.1 . . . 3.sub.N, reset gates 4.sub.1 . . . 4.sub.N, select gates 5.sub.1 . . . 5.sub.N, a shift register formed with (N+1) transfer stages 6.sub.1 . . . 6.sub.N+ 1 of the same structure, and a common output line 10. In addition, the shift register is provided with a dummy transfer stage 6.sub.0 of the same structure as that of the respective transfer stages 6.sub.i (i=1, . . . N+1) in front of the transfer stage 6.sub.1.

The operation of the image sensor shown in FIG. 1 will be described hereinbelow with reference to FIG. 2. The respective transfer stages 6i (i=1, . . . N+1) of the shift register are driven by two different-phase drive pulses .phi..sub.1 and .phi..sub.2. The first transfer stage 6.sub.1 transmits a read pulse 9.sub.1 synchronized with the drive pulse .phi..sub.1 to the select gate 5.sub.1 on the basis of a control pulse 8.sub.1 at a constant period, and further transmits a control pulse 8.sub.2 synchronized with the drive pulse .phi..sub.2 to the second transfer stage 6.sub.2. Further, the transfer stage 6.sub.i (i=2, . . . N) transmits a read pulse 9.sub.i synchronized with the drive pulse .phi..sub.1 to the select gate 5.sub.i and a reset gate 4.sub.i-1 on the basis of the control pulse 8.sub.i transmitted from the preceding transfer stage 6.sub.i-1, and further transmits a control pulse 8.sub.i+1 synchronized With the drive pulse .phi..sub.2 to the succeeding transfer stage 6.sub.i+1. In addition, the final transfer stage 6.sub.N+1 transmits a read pulse 9.sub.N+1 synchronized with the drive pulse .phi..sub.1 to the reset gate 4.sub.N on the basis of the control pulse 8.sub.N+1 transmitted by the transfer stage 6.sub.N. The control pulse output terminal of this transfer stage 6.sub.N+1 is kept opened. The dummy transfer stage 6.sub.0 is driven by the drive pulse .phi..sub.1 and .phi..sub.2 in the same way as the respective transfer stages 6.sub.i (i=1, . . . N+1), and transmits a control pulse 8.sub.1 synchronized with the drive pulse .phi..sub.2 to the transfer stage 6.sub.1 on the basis of the control pulse 8.sub.0 transmitted from the external circuit.

While the read pulse 9.sub.i+1 is kept at ON level, the output terminal potential of the photodiode 2.sub.i (i=1, . . . N) is initialized by a reset drain voltage applied from a voltage supply 20 to the reset gate 4.sub.i, and then drops according to the intensity of incident light. This voltage drop is detected by the buffer 3.sub.i. After an integral duration which corresponds to the ON-level duration of the control pulse 8.sub.i has elapsed, the voltage detected by the buffer 3.sub.i is generated at the common output line 10 as long as the read pulse 9.sub.i is at ON level. Thereafter, a control pulse 8.sub.i+1 is transmitted to the transfer stage 6.sub.i+1, and a read pulse 9.sub.i+1 is generated from this transfer stage 6.sub.i+1, so that the output terminal of the photodiode 2.sub.i is initialized again. The above operation is repeated so that the signal from the photodiode 2.sub.i is outputted to the common output line 10 when the read pulse 9.sub. i (i=1, . . . N+1) is kept generated, and the signal from the photodiode 2.sub.i+1 is outputted to the common output line 10 when the read pulse 9.sub.i+1 is kept generated. Therefore, signals are generated from the photodiodes 2.sub.1 . . . 2.sub.N to the common output line in time series fashion. Here, the one which includes the photodiode 2.sub.i, the buffer 3.sub.i, the reset gate 4.sub.i and the select gate 5.sub.i is referred to as a pixel, hereinafter.

As described above, since the waveforms of the control pulses 8.sub.i inputted into the respective transfer stages 6.sub.i (i=1, . . . N+1) are allowed to be roughly the same, it is possible to prevent the S/N ratio from being deteriorated. Further, in the above description, it is not necessarily required that the dummy transfer stage 6.sub.0 generate a read pulse synchronized with the drive pulse .phi..sub.1. Further, in the above embodiment, only the single dummy transfer stage has been explained by way of example. However, the similar effect can be obtained when a plurality of dummy transfer stages are arranged.

The second embodiment of the solid image device according to the present invention will be described with reference to FIG. 3.

This embodiment relates to a so-called multichip image sensor such that a plurality of solid image devices as shown in FIG. 1 are arranged in series with each other. In FIG. 3, a single chip is designated by a numeral 100 or 200. On the chip 100, there are formed pixels 101.sub.i (i=1, . . . N), a dummy transfer stage 106.sub.0, a shift register including transfer stages 106, 106.sub.N+1, and an output buffer 115 for transmitting a control pulse. On the chip 200, similarly there are arranged pixels 201.sub.i (i=1, N), a dummy transfer stage 206.sub.0, a shift register including transfer stages 206, . . . 206.sub.N+1, and an output buffer (not shown) for transmitting a control pulse. Each of the pixels 101.sub.i and 201.sub.i comprises the photodiode 2.sub.i, the buffer 3.sub.i, the reset gate 4.sub.i and the select gate 5.sub.i as shown in FIG. 1. The dummy transfer stages 106.sub.0 and 206.sub.0 and the transfer stages 106.sub.i and 206.sub. i (i=1, . . . N+1) are driven by two different-phase drive pulses .phi..sub.1 and .phi..sub.2, respectively. The dummy transfer stage 106.sub.0 transmits a control pulse 108.sub.1 synchronized with the drive pulse .phi..sub.2 to the transfer stage 106.sub.1 on the basis of the control pulse 108.sub.0 applied from the external circuit. The transfer stage 106.sub.i (i=1, . . . N) transmits read pulse 1091 synchronized with the drive pulse .phi..sub.1 to a select gate of the pixel 101.sub.1 on the basis of the control pulse 108.sub.1 transmitted from the dummy transfer stage 106.sub.0. Further, the transfer stage 106.sub.i (i=2, . . . N) transmits the read pulse 109.sub.i synchronized with the drive pulse .phi..sub.1 to the reset gate of the pixel 101.sub.i-1 and the select gate of the pixel 101.sub.i on the basis of the control pulse 108i transmitted by the preceding transfer stage 106.sub.i-1, and transmits a control pulse 108.sub.i+1 synchronized with the drive pulse .phi..sub.2 to the succeeding transfer stage 106.sub.i+1. The final transfer stage 106.sub.N+1 transmits a read pulse 109.sub.N+1 synchronized with the drive pulse .phi..sub.1 to the reset gate of the pixel 101.sub.N on the basis of the control pulse 108.sub.N+1. The pulse transmitting output buffer 115 is of high input impedance and low impedance characteristics, and transmits the control pulse 108.sub.N transmitted from the transfer stage 106.sub.N to the dummy transfer stage 206.sub.0 formed on the chip 200. The composing elements (e.g. transfer stages 106.sub.i (i=1, . . . N+1), pixels 101.sub.i (i=1, . . . N), etc.) other than the dummy transfer stage 206.sub.0 formed on the chip 200 are provided with functions the same as those of the corresponding composing elements (e.g. transfer stages 206.sub.i (i=1, . . . N+1), pixels 201.sub.i (i=1, . . . N), etc.) arranged on the chip 100.

The operation of this second embodiment will be described thereinbelow with reference to FIG. 4. When the control pulse 108.sub.0 transmitted from the external circuit is inputted to the dummy transfer stage 160.sub.0, the control pulse 1081 synchronized with the drive pulse .phi..sub.2 is transmitted from this dummy transfer stage 106.sub.0 to the transfer stage 106.sub.1. Therefore, since the read pulse 109.sub.1 synchronized with the drive pulse .phi..sub.1 is transmitted from the transfer stage 106.sub.1 to the select gate of the pixel 101.sub.1, an image signal is generated at the output line 110 of the chip 100 from the pixel 101.sub.1 according to the intensity of light incident upon the pixel 101.sub.1. Thereafter, the control pulse 108.sub.2 synchronized with the drive pulse .phi..sub.2 is transmitted from the transfer stage 106.sub.1 to the transfer stage 106.sub.2. On the basis of this control pulse 108.sub.2, the read pulse 109.sub.2 is transmitted from the transfer stage 106.sub.2 to the reset gate of the pixel 101.sub.1 and the select gate of the pixel 102.sub.i, so that a signal is generated from the pixel 101.sub.2 to the output line 110. The above-mentioned operation is repeated, so that signals are generated from the pixels 101.sub.i (i=1, . . . N) to the output line 110 in time series fashion, i-n the same way as with the case of the first embodiment. On the other hand, in the above-mentioned operation, when the control pulse 108.sub.N is generated from the transfer stage 106.sub.N= 1 this control pulse 108.sub.N is transmitted to both the transfer stage 106.sub.N and the buffer 115. Therefore, the control pulse 208.sub.0 is transmitted from the buffer 115 to the dummy transfer stage 206.sub.0 on the chip 200, with the result that the chip 200 operates in the same way as the chip 100 (see FIG. 5). At this moment, the timing at which the control pulse 208.sub.1 is generated from the dummy transfer stage 206.sub.0 matches the timing at which the control pulse 108.sub.N+1 is generated from the transfer stage 106.sub.N to the transfer stage 106.sub.N+1 on the chip 100.

After time serial signals are generated from the pixels 101.sub.1 . . . 101.sub.N to an integrated output line 999 via the output line 110 in accordance with the above-mentioned operation, time serial signals are generated from the pixels 201.sub.1 . . . 201.sub.N to the integrated output line 999 via the output line 210 of the chip 200. Owing to the above-mentioned operation, the signal processing can be simplified in spite of the multichip structure. Further, in this second embodiment, the same effect as with the case of the first embodiment shown in FIG. 1 can be of course obtained.

In the embodiment shown in FIG. 3, an image device composed of 2 chips has been explained by way of example. Without being limited thereto, it is of course possible to realize an image device of three or more chips. Further, in FIG. 3, the image device including a single dummy transfer stage has been explained. However, it is of course possible to incorporate a plurality of dummy transfer stages therein by adjusting the input branch positions to the pulse transmitting output buffer. In more detail, assuming that the number of the dummy transfer stages on one chip is m and the number of transfer stages of the shift register except the dummy transfer stages on the other chip in front of the one chip is n, the control pulse outputted from the (n-m)th transfer stage of the shift register is inputted to the input terminal of the pulse transmitting output buffer.

As described above, in the solid image device according to the present invention, it is possible to prevent the deterioration of the S/N ratio of the image signals.

Claims

1. A multi-chip solid-state image sensing device, comprising:

an integrated output line; and

a plurality of (L(.gtoreq.2)) of solid-state image sensing chips arranged in series, an i-th (i=1, 2, . . . L) solid-state image sensing chip comprising

N(.gtoreq.2) photoelectric sensing elements for converting optical signals to electric signals;

N signal detecting means for detecting an electric signal from the corresponding photoelectric sensing elements, respectively;

transfer means having a shift register with (N+1) series-connected transfer stages, for generating a read pulse on the basis of a control pulse and for transferring the control pulse to a succeeding transfer stage, respectively;

dummy transfer means having m (m.gtoreq.1) transfer stages and having the same structure as that of the transfer stages of said shift register, for transmitting the control pulse received from a previous (i-1) the solid-state image sensing chip to a first transfer stage of the i-th solid-state image sensing chip in response to the control pulse;

N switching means for outputting a detection output of an i-th signal detecting means to a common output line, respectively on the basis of the read pulse transmitted from an i-th transfer stage of said shift register; and

applying means for applying a pulse in phase with the control pulse transmitted from a (N-m)th transfer stage of the shift register of the i-th (i=1, . . . L-1) solid-state image sensing chip to a first stage of the transfer means of an (i+1)the solid-state image sensing chip as a control input,

wherein said integrated output line integratedly outputs signals outputted from the respective common output line of the solid-state image sensing chips.