Multi-chip touch architecture for scalability

Description

FIELD OF THE DISCLOSURE

This relates generally to touch-sensitive devices, and more particularly, to multiprocessor touch controller architectures.

BACKGROUND OF THE DISCLOSURE

Many types of input devices are presently available for performing operations in a computing system, such as buttons or keys, mice, trackballs, trackpads, joysticks, touch sensor panels, touch screens and the like. Touch screens, in particular, are becoming increasingly popular because of their ease and versatility of operation as well as their declining price. Touch screens can include a touch sensor panel, which can be a clear panel with a touch-sensitive surface, and a display device such as a liquid crystal display (LCD) that can be positioned partially or fully behind the panel so that the touch-sensitive surface can cover at least a portion of the viewable area of the display device. Touch screens can allow a user to perform various functions by touching the touch sensor panel using a finger, stylus or other object at a location often dictated by a user interface (UI) being displayed by the display device. In general, touch screens can recognize a touch and the position of the touch on the touch sensor panel, and the computing system can then interpret the touch in accordance with the display appearing at the time of the touch, and thereafter can perform one or more actions based on the touch. In the case of some touch sensing systems, a physical touch on the display is not needed to detect a touch. For example, in some capacitive-type touch sensing systems, fringing electrical fields used to detect touch can extend beyond the surface of the display, and objects approaching near the surface may be detected near the surface without actually touching the surface. As the sizes of touch screens vary in size and across device platforms, existing touch controller architectures can be unsuitable for scalability.

SUMMARY

This relates to multi-chip touch architecture for scalability. A touch-sensitive device can include a touch sensor panel, one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits (e.g., ASICs) coupled between the one or more touch controller ASICs and the touch sensor panel. Each touch controller ASIC can be coupled to one or more switching circuits. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel.

The touch controller ASICs can include an interface including one or more ports to communicate with one another and transfer touch data between the touch controller ASICs. The touch controller ASICs can be coupled together in a daisy chain configuration, and in some examples, in a ring configuration. The touch data can be transferred between the touch controller ASICs to allow each touch controller ASIC to store touch data representative of an image of touch for the touch sensor panel. The touch controller ASIC can use information including a chip identifier, a scan step, a scan type and a receive channel number to properly generate an image of touch from the touch data from the one or more touch controller ASICs. Storing touch data representative of the image of touch for the touch sensor panel can allow for parallel processing of the touch image by more than one touch controller ASIC.

A touch controller ASIC can include a receive section including a one or more receive channels, a transmit section and a panel scan engine. The touch controller ASIC can also include a memory configured to store touch data from the receive section and one or more processing circuits. The memory can include one or more access ports. The one or more processing circuits can directly access the memory and process the touch data stored in memory to enhance processing speeds. The touch controller ASIC can also include circuitry to dynamically adjust the coupling between portions (e.g., banks) of memory and inputs of the one or more processing circuits to minimize data transfer and improve processing speeds.

The one or more processing circuits can include one or more hardware accelerators to further enhance processing speeds. Hardware accelerators can process two dimensional touch data representing an image of touch to identify one or more touch events and perform centroid calculations. The touch processing information can be used to update coupling between the touch controller ASIC and the touch sensor panel. Hardware accelerators can be used to perform various algorithms necessary for touch processing.

The touch controller ASIC can also include a scan sequencer. The scan sequencer can decode and/or process synchronization signals received from a host processor to sequence the proper performance of scanning operations. The synchronization signals can be used to identify periods of time with minimal interference to perform scanning operations (e.g., intra-frame pauses). The scan sequencer can generate signals to reprogram or adjust the coupling of one or more switching circuits. The scan sequencer can also abort execution of one or more planned scans based on touch processing results.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D illustrate example systems that can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure.

FIG. 2 illustrates an example computing system that can include multiple touch controller circuits to implement touch sensing operations according to examples of the disclosure.

FIG. 3 illustrates an example touch screen including a touch sensor panel configured with drive and sense lines according to examples of the disclosure.

FIG. 4 illustrates an example touch screen including a touch sensor panel configured with self-capacitance electrodes according to examples of the disclosure.

FIG. 5 illustrates an example block diagram for a multiprocessor touch controller circuit architecture according to examples of the disclosure.

FIG. 6 illustrates an example configuration of memory and a plurality of processors according to examples of the disclosure.

FIG. 7 illustrates an example block diagram for improving touch data processing speeds according to examples of the disclosure.

FIG. 8 illustrates another example block diagram for improving touch detection and processing according to examples of the disclosure.

FIG. 9 illustrates an example block diagram for coupling memory to one or more hardware accelerators according to examples of the disclosure.

FIG. 10 illustrates an example block diagram for a hardware accelerator implementing an image scaling and baseline subtraction algorithm according to examples of the disclosure.

FIG. 11 illustrates an example block diagram for a hardware accelerator implementing a thresholding and marking algorithm according to examples of the disclosure.

FIG. 12 illustrates an example block diagram for a hardware accelerator implementing an image diffusion algorithm according to examples of the disclosure.

FIG. 14 illustrates an example touch sensing system including two touch controller circuits according to examples of the disclosure.

FIG. 15 illustrates an example touch sensing system including three touch controller circuits according to examples of the disclosure.

FIG. 16 illustrates an example touch sensing system including four touch controller circuits according to examples of the disclosure.

FIG. 17 illustrates an example computing system for sequencing scanning operations according to the examples of the disclosure.

FIG. 18 illustrates an example timing diagram for intra-frame pauses in a display frame and synchronization signals according to examples of the disclosure.

FIG. 19 illustrates an example of scanning operations during a display period that can be controlled by a scan sequencer according to examples of the disclosure.

FIG. 20 illustrates an exemplary representation of mapping between physical touch sensor panel electrodes and memory locations according to examples of the disclosure.

FIGS. 21A-21E illustrate an example mapping operation for a mutual capacitance scan according to examples of the disclosure.

FIGS. 22A-22E illustrate an example mapping operation for a self-capacitance scan according to examples of the disclosure.

DETAILED DESCRIPTION

In the following description of examples, reference is made to the accompanying drawings which form a part hereof, and in which it is shown by way of illustration specific examples that can be practiced. It is to be understood that other examples can be used and structural changes can be made without departing from the scope of the disclosed examples.

This relates to multi-chip touch architecture for scalability. A touch-sensitive device can include a touch sensor panel, one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits coupled between the one or more touch controller ASICs and the touch sensor panel. Each touch controller ASIC can be coupled to one or more switching circuits. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel.

FIGS. 1A-1D illustrate example systems that can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure. FIG. 1A illustrates an example mobile telephone 136 that includes a touch screen 124 and can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure. FIG. 1B illustrates an example digital media player 140 that includes a touch screen 126 and can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure. FIG. 1C illustrates an example personal computer 144 that includes a touch screen 128 and can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure. Additionally, the multiprocessor touch controller architectures can implement touch sensing operations for other touch interfaces without a display, such as for trackpad 146 in FIG. 1C. FIG. 1D illustrates an example tablet computing device 148 that includes a touch screen 130 and can include multiprocessor touch controller architectures to implement touch sensing operations according to examples of the disclosure. The touch screen and multiprocessor touch controller architectures can be implemented in other devices including wearable devices. Additionally or alternatively, the multiprocessor touch controller architecture can include multiple touch controller chips for scalability depending on the size of the touch screen or touch sensitive surface of a device.

Touch screens 124, 126, 128 and 130 can be based on, for example, self-capacitance or mutual capacitance sensing technology, or another touch sensing technology. For example, in a self-capacitance based touch system, an individual electrode with a self-capacitance to ground can be used to form a touch pixel (touch node) for detecting touch. As an object approaches the touch pixel, an additional capacitance to ground can be formed between the object and the touch pixel. The additional capacitance to ground can result in a net increase in the self-capacitance seen by the touch pixel. This increase in self-capacitance can be detected and measured by a touch sensing system to determine the positions of multiple objects when they touch the touch screen. A mutual capacitance based touch system can include, for example, drive regions and sense regions, such as drive lines and sense lines. For example, drive lines can be formed in rows while sense lines can be formed in columns (i.e., orthogonal). Touch pixels (touch nodes) can be formed at the intersections or adjacencies (in single layer configurations) of the rows and columns. During operation, the rows can be stimulated with an AC waveform and a mutual capacitance can be formed between the row and the column of the touch pixel. As an object approaches the touch pixel, some of the charge being coupled between the row and column of the touch pixel can instead be coupled onto the object. This reduction in charge coupling across the touch pixel can result in a net decrease in the mutual capacitance between the row and the column and a reduction in the AC waveform being coupled across the touch pixel. This reduction in the charge-coupled AC waveform can be detected and measured by the touch sensing system to determine the positions of multiple objects when they touch the touch screen. In some examples, a touch screen can be multi-touch, single touch, projection scan, full-imaging multi-touch, or any capacitive touch.

FIG. 2 illustrates an example computing system that can include multiple touch controller circuits (e.g., multiple chips) to implement touch sensing operations according to examples of the disclosure. Computing system 200 can be included in, for example, a mobile phone, tablet, touchpad, portable or desktop computer, portable media player, wearable device or any mobile or non-mobile computing device that includes a touch screen or touch sensor panel. Computing system 200 can include two touch controller circuits 250A and 250B, though in other examples the computing system can include only one touch controller circuit or more than two touch controller circuits depending on the size of the touch screen or touch sensitive surfaces (e.g., each with circuitry such as the circuitry illustrated in touch controller circuit 250A). As illustrated in FIG. 2, touch controller 206A, touch processor 202A and peripherals 204A can be integrated into a single application specific integrated circuit (ASIC) (i.e., single chip). Likewise, touch controller 206B, touch processor 202B and peripherals 204B can be integrated into a single ASIC. Touch controller circuits 250A and 250B can include the same or substantially similar components. Although illustrated in FIG. 2 as a single ASIC, the touch controller circuit 250A including one or more touch processors 202A, peripherals 204A, and touch controller 206A, the various components can be implemented with multiple chips, circuits and/or discrete components.

For simplicity the discussion of subsystems and components of touch controller circuits focuses on touch controller circuit 250A, but it is understood that the function of similar subsystems and components in touch controller circuit 250B can have the same or substantially similar functionality. Peripherals 204A can include, but are not limited to, random access memory (RAM) or other types of memory or storage, watchdog timers and the like. Touch controller 206A can include, but is not limited to, one or more sense channels in receive section 208A, panel scan engine 210A (which can include channel scan logic) and transmit section 214A (which can include driver logic). Panel scan engine 210A can access RAM 212A (which can include scan plan information and can be used to store touch data generated by scanning operations), autonomously read data from the sense channels and provide control for the sense channels. In addition, panel scan engine 210A can provide control for transmit section 214A to generate stimulation signals at various frequencies and/or phases that can be selectively applied to drive regions of the touch sensing circuitry of touch sensor panel 220. In some implementations, the touch sensor panel 220 can be integrated with a display to form a touch screen, though in other implementations the touch sensor panel 220 can be independent of the display and/or substantially cover the area of the display.

Computing system 200 can also include switching unit 240 (peripheral switching unit). In some examples switching unit can include a plurality of switches to couple the receive section (208A and/or 208B) and/or the transmit section (214A and/or 214B) to the proper electrodes and/or drive/sense lines of touch sensor panel 220. In some examples, the switching unit 240 can include one or more multiplexers (MUXs) to perform the switching functions. Additionally, some of the coupling between receive and/or transmit sections can be hardwired (via the switching unit 240 or bypassing switching unit 240). Although, illustrated as a single block, in some examples, the switching unit 240 can include a plurality of ASIC chips and/or discrete components to perform switching functions. For example, for the computing system illustrated in FIG. 2, the switching unit can include two ASICs, each ASIC implementing switching function for one of the two touch controller circuits 250A and 250B. In other examples, the switching unit can include a plurality of ASICs for each of the touch controller circuits (e.g., two switching ASICs per touch controller circuit). Additionally, in some examples, the switching units can be coupled to more than one touch controller circuit to permit connection between some or all electrodes and/or drive/sense lines of the touch sensor panel 220 and the receive sections and/or transmit sections of the one or more touch controller circuits. In other examples, the interconnection between the touch sensor panel and channels of the plurality of touch controller circuits can be limited based on routing and scanning complexity concerns. In some examples, when the electrodes of a panel can be divided among a plurality of touch controller circuits (e.g., half of the electrodes allocated to one touch controller circuit and half the electrodes allocated to a second touch controller circuit), the electrodes at the boundary between portions of the touch sensor panel can be prioritized to allow for coupling between the electrodes proximate to the boundary and either of the touch controller circuits scanning on either side of the boundary.

It should be understood that the architecture shown in FIG. 2 is only one example architecture of computing system 200, and that the system could have more or fewer components than shown, or a different configuration of components. The various components shown in FIG. 2 can be implemented in hardware, software, firmware or any combination thereof, including one or more signal processing and/or application specific integrated circuits.

Touch controller circuits 250A and 250B can operate together to perform touch sensing or other scanning operations. As illustrated in FIG. 2, touch controller circuit 250A can operate as a master touch controller and touch controller circuit 250B can operate as a slave touch controller. In some examples, the touch sensing or other scanning operations can be divided between the master and slave touch controller circuits by having each touch controller circuit scan half of the touch sensor panel. Each touch controller circuit can store the touch data produced by the scans in their respective memory. The master and slave touch controllers can communicate via a master-slave interface 230A and 230B to allow the processors subsystems 202A and 202B and/or touch controllers 206A and 206B to exchange information. Additionally, the slave touch controller circuit can transfer its touch data to the master touch controller circuit at various times (e.g., in response to an interrupt or synchronization signal), and the master touch controller circuit can process the combined touch data (forming a complete “image of touch”) for the touch sensor panel.

Computing system 200 can include a host processor 228 for receiving outputs from touch controller circuits 250A and 205B (e.g., via touch processors 202A and 202B) and performing actions based on the outputs. For example, host processor 228 can be connected to program storage 232 and a display or display controller, such as a Liquid-Crystal Display (LCD) driver 234. It is understood that although the examples of the disclosure are described with reference to LCD displays, the scope of the disclosure is not so limited and can extend to other types of displays, such as Light-Emitting Diode (LED) displays, including Active-Matrix Organic LED (AMOLED) and Passive-Matrix Organic LED (PMOLED) displays.

Host processor 228 can use LCD driver 234 to generate and display an image on a display (e.g., on the touch screen formed by the touch sensor panel and LCD display), such as an image of a user interface (UI), and can use touch controller circuits 250A and 250B (including touch processors 202A and 202B and touch controllers 206A and 206B) to detect a touch on or near touch sensor panel 220, such as a touch input to the displayed UI of the touch screen formed by touch sensor panel 220 and the LCD display. The touch input can be used by computer programs stored in program storage 232 to perform actions that can include, but are not limited to, moving an object such as a cursor or pointer, scrolling or panning, adjusting control settings, opening a file or document, viewing a menu, making a selection, executing instructions, operating a peripheral device connected to the host device, answering a telephone call, placing a telephone call, terminating a telephone call, changing the volume or audio settings, storing information related to telephone communications such as addresses, frequently dialed numbers, received calls, missed calls, logging onto a computer or a computer network, permitting authorized individuals access to restricted areas of the computer or computer network, loading a user profile associated with a user's preferred arrangement of the computer desktop, permitting access to web content, launching a particular program, encrypting or decoding a message, and/or the like. Host processor 228 can also perform additional functions that may not be related to touch processing.

In some examples, RAM 212A, RAM 212B, program storage 232, or one or more of the above storage, can be non-transitory computer readable storage media. One or more of RAM 212A, RAM 212B, and program storage 232 can have stored therein instructions, which when executed by touch processor 202A, touch processor 202B, or host processor 228 or both, can cause the device including computing system 200 to perform one or more functions and methods of one or more examples of this disclosure.

Note that one or more of the functions described herein, including the configuration of switches, can be performed by firmware stored in memory (e.g., one of the peripherals 204A and 204B in FIG. 2) and executed by touch processors 202A and 202B, or stored in program storage 232 and executed by host processor 228. The firmware can also be stored and/or transported within any non-transitory computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “non-transitory computer-readable storage medium” can be any medium (excluding signals) that can contain or store the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, a portable computer diskette (magnetic), a random access memory (RAM) (magnetic), a read-only memory (ROM) (magnetic), an erasable programmable read-only memory (EPROM) (magnetic), a portable optical disc such a CD, CD-R, CD-RW, DVD, DVD-R, or DVD-RW, or flash memory such as compact flash cards, secured digital cards, Universal Serial Bus (USB) memory devices, memory sticks, and the like.

The firmware can also be propagated within any transport medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “transport medium” can be any medium that can communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The transport medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic or infrared wired or wireless propagation medium.

As discussed above, the touch sensor panel 220 can be coupled to and/or integrated with a display to form a touch screen. FIG. 3 illustrates an example touch screen including a touch sensor panel configured with drive and sense lines according to examples of the disclosure. Touch screen 320 can include touch sensing circuitry that can include a capacitive sensing medium having a plurality of drive lines 322 and a plurality of sense lines 323. It should be noted that the term “lines” is sometimes used herein to mean simply conductive pathways, as one skilled in the art will readily understand, and is not limited to elements that are strictly linear, but includes pathways that change direction, and includes pathways of different size, shape, materials, etc. Additionally, the drive lines 322 and sense lines 323 can be formed from smaller electrodes coupled together to form drive lines and sense lines. Drive lines 322 can be driven by stimulation signals from the transmit section 214A and/or 214B through a drive interface 324, and resulting sense signals generated in sense lines 323 can be transmitted through a sense interface 325 to sense channels in receive section 208A and/or 208B (also referred to as an event detection and demodulation circuit) in touch controllers 206A and/or 206B. In this way, drive lines and sense lines can be part of the touch sensing circuitry that can interact to form capacitive sensing nodes, which can be thought of as touch picture elements (touch pixels), such as touch pixels 326 and 327. This way of understanding can be particularly useful when touch screen 320 is viewed as capturing an “image” of touch. In other words, after touch controllers 206A and/or 206B have determined whether a touch has been detected at each touch pixel in the touch screen, the pattern of touch pixels in the touch screen at which a touch occurred can be thought of as an “image” of touch (e.g., a pattern of fingers or other objects touching the touch screen).

Additionally or alternatively the touch screen can include self-capacitance touch sensing circuitry including an array of self-capacitance electrodes. FIG. 4 illustrates an example touch screen including a touch sensor panel configured with self-capacitance electrodes according to examples of the disclosure. Touch screen 420 can include touch sensing circuitry that can include a capacitive sensing medium having a plurality of electrically isolated touch pixel electrodes 422 (e.g., a pixelated self-capacitance touch screen). Touch pixel electrodes 422 can be coupled to sense channels in receive section 208A and/or 208B in touch controllers 206A and/or 206B, can be driven by stimulation signals from the sense channels (or transmit section 214A and/or 214B) through drive/sense interface 425, and can be sensed by the sense channels through the drive/sense interface as well, as described above. Labeling the conductive plates used to detect touch (i.e., touch pixel electrodes 422) as “touch pixel” electrodes can be particularly useful when touch screen 420 is viewed as capturing an “image” of touch. In other words, after touch controllers 206A and/or 206B have determined an amount of touch detected at each touch pixel electrode 422 in touch screen 420, the pattern of touch pixel electrodes in the touch screen at which a touch occurred can be thought of as an “image” of touch (e.g., a pattern of fingers or other objects touching the touch screen).

As discussed above, the touch sensor panel and display areas can partially or fully overlap. In some examples, the touch sensor panel and display can be discrete components that can be coupled together (e.g., adhering the touch sensor on top of the display). In other examples, the touch sensor panel can be integrated with the display stack-up, and may share some electrical components between sensing and display functions. In some examples, portions of the touch sensor panel can be integrated within the display stack-up (e.g., on-cell) and in other examples, the touch sensor panel can be fully integrated within the display stack-up (e.g., in-cell).

The touch sensor panel/touch screen can detect touch or proximity events from one or more objects including one or more fingers and/or styli. They styli can include a passive stylus and/or an active stylus (e.g., a stylus that can generate a stimulus signal to inject into the touch sensor panel).

In other examples, the architecture of the touch controller circuit can include one or more processors performing micro-sequences or firmware operations and/or one or more hardware acceleration units to replace or supplement micro-sequences or firmware operations. FIG. 5 illustrates an example block diagram for a multiprocessor touch controller circuit architecture according to examples of the disclosure. Touch controller circuit 500 can be an ASIC, or alternatively include multiple circuits including different chips, modules, and/or discrete components. As illustrated in FIG. 5, touch controller circuit 500 can include one or more processors 502, including one or more central processing units (CPUs), microcontrollers, or digital signal processors (DSP). Additionally or alternatively, touch controller circuit 500 can include one or more hardware accelerators 504. Hardware accelerators 504 can accelerate execution of certain operations—such as processing touch data—as will be discussed below in more detail.

Touch controller circuitry 500 can also include one or more memory circuits 506, including RAM and ROM. The RAM can be arranged to include a plurality of banks, for example. In order to enable one or more processors 502 and/or multiple hardware accelerators 504 to perform operations on data stored within memory circuits 506, the memory circuits can be designed to include multiple ports (e.g., direct memory access (DMA) ports). Sharing the memory between different processing components can increase processing performance for multi-processor architectures, instead of having to access data via an indirect route which can create processing bottlenecks and reduce or negate the benefits of multiple processors operating in parallel. The number of memory ports can be limited by routing constraints and memory access complexity constraints among other constraints.

Touch controller circuitry 500 can also include a high speed bus 508 to permit communication and data transfer between various blocks in touch controller circuitry 500. Although other connections and coupling between the blocks of touch controller circuitry 500 can be possible (e.g., dedicated lines for direct memory access between the memory and the one or more processors and/or one or more hardware accelerators).

Touch controller circuitry 500 can also include circuitry for performing touch sensing and other scanning operations. For example, touch controller can include, but is not limited to, one or more sense channels in receive section 510, panel scan engine 514 and transmit section 512.

A sense channel in receive section 510 can include, for example, a trans-impedance amplifier circuit (TIA), a band pass filter, an analog-to-digital converter (ADC) and one or more demodulation circuits (e.g., implemented with one or more digital signal processor (DSP) channels). In some examples, the demodulation circuits can be implemented as part of the panel scan engine 514 instead of in the receive section 510. The one or more DSP channels can perform simultaneous processing of the signals output from the ADC for the channel. For example, a first DSP channel can perform spectral analysis at a first frequency, a second DSP channel can perform spectral analysis at a second frequency, a third DSP channel can demodulate stylus/pen scan results at a third frequency and a fourth DSP channel can demodulate the stylus/pen scan results at a fourth frequency. The number of DSP channels for each channel can be different, and the number of DSP channels processing in parallel can depend on the type of touch sensing or other scanning operation performed and the desired demodulation and processing results.

The transmit section 512 can include one or more oscillators, a transmit digital-to-analog converter (TX DAC), and switching circuitry (e.g., MUXs) to select between various drive signals (e.g., DC voltages, AC voltages with different frequencies and/or phase).

Panel scan engine 514, which can include a scan sequencer (not shown), can execute a scan plan based on synchronization signals from the host processor, can access memory to read scan plan information and can store touch data generated by scanning operations in the memory. Panel scan engine 514 can also configure the receive section 510 and/or transmit section 512 according to the scan plan. Configuring the receive section 510 and/or transmit section 512 can include generating signals to properly couple sense channels and/or drive channels to the appropriate touch sensor electrodes, drive lines and/or sense lines. The coupling can be performed by the switching unit 240 (which can receive the generated signals from the touch controller circuit) including one or more switching unit circuits. The switching unit 240 can interpret and/or use the generated signals to perform the coupling. Panel scan engine can 514 also autonomously read data from the sense channels and provide control for the sense channels. In addition, panel scan engine 514 can provide control for transmit section to generate stimulation signals at various frequencies and/or phases that can be selectively applied to drive regions of the touch sensing circuitry of touch sensor panel 220.

In some examples, two processors of touch controller circuit 500 can be configured to perform touch sensing or other scanning operations on the touch sensor panel. One processor for example can operate as a master processor and another processor can operate as a slave processor. The receive section 510, transmit section 512, and panel scan engine 514 can be implemented to be shared for touch sensing and other scanning operations by the master and slave. Alternatively, each of the master and the slave processor can have a separate receive section, transmit section and panel scan engine for executing touch sensing and other scanning operations. The master and slave operations can be performed in a similar way as discussed with respect to the architecture of FIG. 2, though touch data need not be transferred between two different touch controller circuits as in FIG. 2.

Additionally, touch controller circuit 500 can include a touch controller circuit high speed interface 520. The high speed interface can include one or more interface ports to permit communication between multiple touch controller circuits as will be discussed below in more detail. Using multiple touch controller circuits (chips) like the touch controller circuit of FIG. 5 can allow for scaling the size of a touch screen or touch sensitive surface without designing a new touch controller chip architecture. The touch controller circuit of FIG. 5 can replace one or more of the touch controller circuits in FIG. 2. The touch controller circuit of FIG. 5 can be coupled to one or more peripheral switching units to appropriately couple the touch controller circuit to some or all of the electrodes of the touch sensor panel/touch screen.

It should be apparent that the architecture shown in FIG. 5 is only one example architecture of a touch controller circuit, and that the touch controller circuit could have more or fewer components than shown, or a different configuration of components. The various components shown in FIG. 5 can be implemented in hardware, software, firmware or any combination thereof, including one or more signal processing and/or application specific integrated circuits.

In order to take advantage of the one or more processors and/or the one or more hardware accelerators, the touch controller circuit can be designed to minimize data movement. Moving data between the memory and the one or more processors can become a bottleneck that prevents the one or more processors and/or the one or more hardware accelerators from increasing the operating speed of the touch controller circuit. FIG. 6 illustrates an example configuration of memory and a plurality of processors according to examples of the disclosure. FIG. 6 illustrates a plurality of processors, including master CPU 602, slave CPUs 604 and 606, and memory organized into a plurality of memory banks, including memory banks 610, 612 and 616. Master CPU 602 can be coupled to each of N memory banks for direct memory access, although in some examples, the master CPU 602 can be coupled to fewer than all N memory banks. Slave CPU 604 can be coupled to one or more memory banks, and as illustrated in FIG. 6 can be coupled to memory bank 610. Likewise, slave CPU 606 can be coupled to one or more memory banks, and as illustrated in FIG. 6 can be coupled to memory bank 612. The number of memory banks the slave CPUs can be coupled to can depend on the number of memory banks necessary to perform the operations associated with the one or more slave processors.

Although one master processor and two slave processors are illustrated in FIG. 6, the touch controller circuit can include a smaller or larger number of processors, configured in a master slave configuration or in a different configuration. Additionally, the number of memory banks for the system can vary depending on the memory needs of the touch controller circuit. Additionally, although the figure illustrates slave processors, one or more of the slave processors can be replaced with one or more hardware accelerators in other examples.

One or more processors and/or one or more hardware accelerators can be useful to reduce processing time for various algorithms. For example, processing touch data (which can be viewed as an “image of touch”) can require a number of algorithms that can be executed faster by distributed parallel processing across multiple processors and/or hardware accelerators. FIG. 7 illustrates an example block diagram for improving touch data processing speeds according to examples of the disclosure. As illustrated in FIG. 7, signals generated from touch sensing or scanning operation (e.g., a coarse self-capacitance scan) can be transmitted via switching unit 702 (peripheral switching unit) to receive channels 704 (sense channels). For simplicity, FIG. 7 illustrates one channel of receive channels 704. The one illustrated channel can include an analog front end (AFE) 706 (e.g., including a TIA and a band pass filter) and an ADC/demodulation section 708 including one or more DSP channels to process signals output form the ADC. The touch data processed from the one or more DSP channels can be stored in memory, such as RAM 710. As discussed above with regard to FIG. 6, the RAM can be accessible by multiple processors, such as master CPU 712 and slave CPU/micro-sequencer 714. In order to improve processing of the touch data stored in RAM 710, slave CPU/micro-sequencer 714 can run firmware to process the touch data stored in RAM (e.g., as a two dimensional image of touch) to detect one or more touch events and determine the centroid of one or more touch events (when touch events are detected). The micro-sequencer can generate output information about whether a touch event is detected and the centroid of one or more touch events which can be transmitted to an output buffer 716. Output buffer 716 can transmit signals to the switching unit 702 to control the coupling functions of switching unit 702 for future scan events that can be based upon the detection of one or more touch events and the location of the centroid of the one or more touch events. In some examples, the updated switching by switching unit 702 can allow the touch controller circuit to perform a targeted scan (e.g., scanning specific coordinates of the touch sensor panel where touch events were detected during the coarse scan).

In some examples, the information transmitted by output buffer 716 can be transmitted to switching unit 702 via an inter-integrated circuit (I2C) interface or a serial peripheral interface (SPI). The output from the output buffer can also be adjusted based on an address offset from the master CPU 712 or override signals from the master CPU 712. Additionally, the processed touch data can be mapped from the centroid information to information understandable by the switching unit 702. For example, a logic circuit or micro-sequence can be used to map centroid information generated by the slave CPU/micro-sequencer 714 to the switching functions necessary for subsequent scans of the touch sensor panel. Alternatively, switching unit 702 can include intelligence to map centroid information to properly switch the coupling between the touch controller circuit and the touch sensor panel.

FIG. 8 illustrates another example block diagram for improving touch detection and processing according to examples of the disclosure. FIG. 8 also illustrates switching unit 802 (peripheral switching unit), receive channels 804 (including AFE 806 and ADC/demodulation circuit 808), memory 810, master CPU 812, and output buffer 816. The functionality of these components can be the same or substantially similar to the functionality of the corresponding components in FIG. 7 and will be omitted here for simplicity. Instead of improving processing with a micro-sequencer 714 running firmware, the block diagram includes one or more hardware accelerators 814, which can include one or more hardware accelerator circuits. The one or more hardware accelerators 814 can implement some of the same algorithms performed by micro-sequencer 714, but with hardware rather than firmware to improve processing speed. The output of touch data processing by the one or more hardware accelerators can also be mapped to appropriate switching functionality by centroid-to-panel mapping engine 818.

In order to improve the touch data processing performance, the coupling between the one or more hardware accelerators and the memory can be dynamically reconfigured to reduce the data movement which can act as a bottleneck. FIG. 9 illustrates an example block diagram for coupling memory to one or more hardware accelerators according to examples of the disclosure. The block diagram of FIG. 9 can include RAM 902 (including one or more memory devices), one or more hardware accelerators 904 and a hardware acceleration switching unit 906. In some examples, the hardware acceleration switching unit 906 can couple any memory bank of RAM 902 to any input or output of the one or more hardware accelerator circuits. In other examples, the hardware accelerators can be configurable to couple to fewer than all memory banks of RAM 902. The switching functionality of hardware acceleration switching unit 906 can include a plurality of switches or MUXs or other switching circuitry to couple memory banks or locations to inputs and outputs of the hardware accelerator so as to reduce touch data transfer. Control signals to control the hardware acceleration switching unit can be generated by one or more of the hardware accelerator 904, a master processor (not shown), and a host processor (not shown).

As discussed above, touch data processing algorithms can be performed by hardware accelerator circuits to improve processing speeds. FIGS. 10-13 illustrate example block diagrams for implementing some touch data processing algorithms with hardware accelerators with minimal data movement. Additionally or alternatively, these algorithms can also be performed by slave processors running firmware with minimal data movement. The algorithms implemented by processors or hardware accelerators can include one or more of baseline subtraction and offset correction, thresholding, image diffusion, sorting a thresholded image, watershedding (i.e., a watershed algorithm), and centroid calculation, although other algorithms can be implemented in hardware accelerators as well.

FIG. 10 illustrates an example block diagram for a hardware accelerator implementing an image scaling and baseline subtraction algorithm according to examples of the disclosure. A hardware accelerator 1000 implementing an image scaling and baseline subtraction algorithm can include as inputs an alpha gain parameter and a scaler parameter from alpha register 1002 and scaler register 1004, respectively. The algorithm can accept touch information from three different memory locations—register bank A 1006, register bank B 1008 and register bank C 1010, for example—which can map to one or more physical memory banks of the system. The signals necessary to access these memory locations (e.g., address signals, data signals, handshake signals, etc.) can be routed via hardware accelerator switching unit 906 to couple these memory locations as inputs for the hardware accelerator 1000 implementing an image scaling and baseline subtraction algorithm. Likewise, the output of the algorithm can be output to memory locations represented by register bank D 1012. The dynamic switching can allow the hardware algorithm to perform processing operations while reducing the amount of data movement. The hardware accelerator switching unit 906 can use a small enough transistor process that switching circuitry can add minimal capacitive loading with a small silicon area cost to reduce data movement. For each pixel in the two dimensional touch image, the hardware accelerator can use the inputs from register banks 1006, 1008 and 1010 to generate an output stored in register bank 1012. The output, D(i), can be generated based on the following equation: D(i)=(alpha/scaler)×(A(i)−B(i))+C(i), where alpha and scaler are the constants stored in the alpha register 1002 and scaler register 1004, respectively, A(i), B(i), C(i) and D(i) refer to the data read from or written to the memory for the algorithm for each pixel i.

FIG. 11 illustrates an example block diagram for a hardware accelerator implementing a thresholding and marking algorithm according to examples of the disclosure. A hardware accelerator 1100 implementing a thresholding and marking algorithm can include as inputs one or more constants (e.g., for thresholding and marking) stored for example in a register block 1102. The algorithm can include as inputs touch information from two different memory locations—register bank A 1104 and register bank B 1106, for example—which can map to one or more physical memory banks of the system. The signals lines necessary to access these memory locations (e.g., address signals, data signals, handshake signals, etc.) can be routed via hardware accelerator switching unit 906 to couple these memory locations as inputs for the hardware accelerator 1100 implementing the thresholding and marking algorithm. Likewise, the outputs of the algorithm can be output to memory locations represented by register bank C 1108 and register bank D 1110. The dynamic switching can allow the hardware algorithm to perform operations while reducing the amount of data movement. The hardware accelerator can use the inputs from the register banks 1104 and 1106 to generate the outputs stored in register banks 1108 and 1110. The thresholding and marking algorithm outputs can include a thresholded map (marking) and a thresholded image (subtracted). The output D(i) (i.e., thresholded image) can be generated for each pixel of the two dimensional image based on the following equation:

$D (i) = {\begin{matrix} A (i) - constant 1; & if ((A (i) - constant 1) - constant 2) > 0 \\ 0; & else \end{matrix}}$

where constants 1 and 2 can be stored in register block 1102 and A(i) and D(i) refer to the data read from or written to the memory for the algorithm. The output C(i) (i.e., thresholded map (marking)) can be generated by the logical expression:

C(i)=D(i)==0) or (B(i)<constant3)

Where constant 3 can be stored in register block 1102 and B(i), C(i) and D(i) can refer to the data read from or written to the memory for the algorithm.

FIG. 12 illustrates an example block diagram for a hardware accelerator implementing an image diffusion algorithm according to examples of the disclosure. A hardware accelerator 1200 implementing an image diffusion algorithm can include as inputs a weighting function and scaling factor stored in registers 1202 and 1204, respectively, for example. The algorithm can include touch information from one memory location—register bank A 1206, for example—which can map to one or more physical memory banks of the system. The signals lines necessary to access these memory locations (e.g., address signals, data signals, handshake signals, etc.) can be routed via hardware accelerator switching unit 906 to couple these memory locations as inputs for the hardware accelerator 1200 implementing an image diffusion algorithm. Likewise, the output of the algorithm can be output to memory location represented by register bank B 1208. The switching can allow the hardware algorithm to perform operations while reducing the amount of data movement. For each pixel in the two dimensional touch image, the hardware accelerator can use the inputs from the register bank 1206 to generate an output stored in register bank 1208. The output, B(i), can be generated based on the following equation:

$B (i) = \frac{a_{11} w_{11} + a_{12} w_{12} + \dots + a_{22} w_{22}}{scaling factor}$

where w_jkcan correspond to weighting coefficients from register 1202, the scaling factor can correspond to the scaling factor from register 1204, a_jkcan correspond to the touch data value at A(i) and adjacent pixels, such that a₂₂(center pixel) can corresponds with A(i), and B(i) can refer to the data written to the memory for the algorithm.

FIG. 13 illustrates an example block diagram for a hardware accelerator implementing an algorithm for conversion between magnitude and phase representation and in-phase and quadrature representation according to examples of the disclosure. A hardware accelerator 1300 implementing an algorithm for conversion between a magnitude and phase (“Mag/Phase”) representation and an in-phase (I) and quadrature (Q) (“I/Q”) representation can include a selection input 1302 indicating the direction of conversion (from I/Q to Mag/Phase or from Mag/Phase to I/Q). The algorithm can include touch information from two different memory locations—register bank A 1304 and register bank B 1306, for example—which can map to one or more physical memory banks of the system. The signals lines necessary to access these memory locations (e.g., address signals, data signals, handshake signals, etc.) can be routed via hardware accelerator switching unit 906 to couple these memory locations as inputs for the hardware accelerator 1300 implementing the conversion algorithm. Likewise, the outputs of the algorithm can be output to memory locations represented by register bank C 1308 and register bank D 1310. The dynamic switching can allow the hardware algorithm to perform operations while reducing the amount of data movement. The hardware accelerator can use the inputs from the register banks 1304 and 1306 to generate the outputs stored in register banks 1308 and 1310. The conversion algorithm outputs can include either I/Q representations or Mag/Phase representations depending on the direction of conversion. In some examples, depending on the direction of conversion, the input and outputs can be reversed (such that register banks 1308 and 1310 can be inputs and register banks 1304 and 1306 can be outputs. The outputs C(i) and D(i) when converting from I/Q to Mag/Phase can be generated based on the following equations:

C(i)=A(i)cos(B(i))
D(i)=A(i)sin(B(i))

where A(i), B(i), C(i) and D(i) refer to the data read from or written to the memory for the algorithm. The outputs C(i) and D(i) when converting from Mag/Phase to I/Q can be generated based on the following equations:

C(i)=√{square root over (A(i)²+B(i)²)}
D(i)=arctan(A(i),B(i))

where A(i), B(i), C(i) and D(i) refer to the data read from or written to the memory for the algorithm.

The algorithms presented above can be representative, and more or fewer algorithms can be implemented with hardware accelerators. Additionally, although the register banks are labeled A through D, these representations are abstractions and simply refer to memory locations, not necessarily physical banks. The mapping between register banks A through D can be dynamically remapped to physical memory locations to minimize data transfers required to process touch data (e.g., via a hardware accelerator switching unit). In some examples, more than four register banks can be used to allow for hardware acceleration implementation of algorithms requiring more input and output register banks. Additionally, increasing the number of register banks can make it possible operate more than one hardware accelerator at a time.

In some examples, a touch controller circuit can include only one hardware accelerator of each algorithm type (e.g., one image distribution hardware accelerator per touch controller circuit). In other examples, a touch controller circuit can include one or more hardware accelerator of each algorithm type.

In some examples, the hardware accelerators can be sequenced by one of the one or more processors of the touch controller circuit. In other examples, the touch controller circuit including hardware accelerators can include a dedicated processor to sequence the hardware accelerator operations. For example, an on-chip sequencer (e.g., a state machine or programmable logic) can sequence the performance of processing operations by the one or more hardware accelerators. Sequencing the hardware accelerator processing can include specifying the inputs and outputs for the one or more hardware accelerators, providing timing (e.g., start and stop) for the processing operation, etc. This sequencing processor can include access to a dedicated local memory and the one or more of the memory banks of the RAM for the touch controller circuit. Sequencing the one or more hardware accelerators can include pipelining the input and output data using one or more buffers (e.g., and input and/or output buffer between the hardware accelerators and the memory. Additionally, in configurations using more than one touch controller circuit, the sequencer for each touch controller circuit can be synchronized through a dedicated set of synchronization signals that can be included in the touch controller circuit interface (discussed below in more detail). The sequencing function described herein can be part of the scan sequencer described in more detail below.

As discussed above, some touch sensitive devices can include one or more touch controller circuits (e.g., ASICs or chips) to perform sensing operations. In some examples, when the touch sensitive device includes more than one touch controller circuit, one of the touch controller circuits can act a master touch controller circuit and the remaining touch controller circuits can act as slave touch controller circuits. In order to coordinate and facilitate the sensing operations and processing performed by multiple touch controller circuits, a communication link and interface can be used to communicate between the multiple touch controller circuits.

The number of touch controller circuits used for a touch sensitive device can depend upon the size of the touch sensor panel (e.g., the number of individual pixel electrodes) and the number of receiving channels in each of the multiple touch controller circuits. In other words, the touch controller circuit can be designed with enough receiving channels for a small touch sensor panel, and as the size of the touch sensor panel increases, the number of touch controller circuits used can scale up according to the size of a touch sensor panel. As the number of touch controller circuits increases, each touch controller circuit can perform sensing or scanning operations on a portion of the touch sensor panel. Similarly, in some examples, the number of peripheral switching unit circuits/ASICs can scale with the number of touch controller circuits.

In touch sensitive devices including multiple touch controller circuits, processing of touch data generated from scanning operations from the multiple touch controller circuits can occur at a subset of the multiple touch controller circuits, for example at a master touch controller circuit, or alternatively, the processing can be distributed among the multiple touch controller circuits. In order to process the data at a master touch controller circuit, each of the slave touch controller circuits can transfer touch data generated from scanning operations to the master touch controller circuit and the master touch controller circuit can thereby store in memory touch data representative of the entire touch sensor panel (i.e., the entire image of touch) for processing. The master touch controller circuit can also transfer information after processing back to the slave touch controller circuits. In order to distribute the processing capability between the multiple touch controller circuits, each touch controller circuit can receive touch data from each of the remaining touch controller circuits (e.g., after each scanning step). Thus, each touch controller circuit can store in memory touch data representative of the entire touch sensor panel (i.e., the entire image of touch) and can process the touch data in parallel.

In some examples the data can be transferred between multiple touch controller circuits at the end of each scanning step. For example, if in a scanning step each touch controller circuit measures self-capacitance touch data for each receive channel of the touch controller circuit, at the conclusion of the scanning step, the touch data for each receive channel can be transferred to the remaining touch controller circuits (and each touch controller circuit can receive the corresponding touch data for the scanning step from the remaining touch controller circuits).

In some examples, each touch controller circuit can have two high speed ports (although in other examples, fewer or more high speed ports are possible). The ports can be used to couple together touch controller circuits. Because multiple ports can result in two memory access operations of the same location in memory of the touch controller circuit (e.g., two write operations to the same memory location), the touch controller circuit can include hardware, firmware or software to perform conflict resolution to prevent errors in transferring information on the two ports simultaneously.

Additionally, in order to properly map the touch data from the multiple touch controller circuits, information about the touch controller circuit can be transferred along with the touch data. For example, the information about the touch controller circuit can include a chip identifier (ID), which can be used to identify a touch controller circuit. For example, in a system having up to four touch controller circuits, the chip ID can be hardwired through two dedicated configuration pins. Each of the up to four touch controller circuits can be represented as “00”, “01”, “10” and “11”. For systems including up to eight touch controller circuits, the chip ID can require an extra signal, pin or bit to properly distinguish between the up to eight touch controller circuits. The size of the chip ID can vary as the number of touch controller circuits increases.

FIG. 14 illustrates an example touch sensing system including two touch controller circuits according to examples of the disclosure. Touch sensing system 1400 can include a first touch controller circuit 1402 and second touch controller circuit 1404. First touch controller circuit 1402 can act as the master touch controller circuit, and can include two high speed ports 1410 and 1412. Second touch controller circuit 1404 can act as the slave touch controller circuit, and can include two high speed ports 1414 and 1416. High speed port 1410 of the first touch controller circuit 1402 can be coupled to high speed port 1416 of the second touch controller circuit 1404 via communication link 1432. High speed port 1412 of the first touch controller circuit 1402 can be coupled to high speed port 1414 of the second touch controller circuit 1404 via communication link 1430. Each port can be capable of accepting or transmitting any necessary input/output signals, clock signals, control signals, synchronization signals and/or strobe signals for the interface between touch controller circuits. In the above configuration with two communication links between the two touch controller circuits, one communication link can be used for communications between the processors (or other processing circuitry) of different touch controller circuits, e.g., to transfer information between one or more processors in the first touch controller circuit 1402 and one or more processors of the second touch controller circuit 1404. The second communication link can be used as a high speed communication channel for the transfer of touch data from scanning operations between the first and second touch controller circuits.

In a configuration with two touch controller circuits, the touch sensing system can have a dedicated communication link for inter-circuit communication between processors and a dedicated communication link for transferring touch data between the two touch controller circuits. In other examples, each of the two communication links can be used to communicate touch data and/or other information between processors between the two touch controller circuits. In either case, the transfer of touch data can be accomplished in one step (e.g., touch data from the first touch controller circuit can be transferred to the second touch controller circuit, and touch data from the second touch controller circuit can be transferred to the first touch controller circuit).

FIG. 15 illustrates an example touch sensing system including three touch controller circuits according to examples of the disclosure. Touch sensing system 1500 can include a first touch controller circuit 1502, a second touch controller circuit 1504, and a third touch controller circuit 1506. First touch controller circuit 1502 and third touch controller circuit 1506 can act as slave touch controller circuits, and can each include two high speed ports 1510 and 1512 and 1518 and 1520, respectively. Second touch controller circuit 1504 can act as a master touch controller circuit, and can include two high speed ports 1514 and 1516. High speed port 1512 of the first touch controller circuit 1502 can be coupled to high speed port 1514 of the second touch controller circuit 1504 via communication link 1530. High speed port 1516 of the second touch controller circuit 1504 can be coupled to high speed port 1518 of the third touch controller circuit 1506 via communication link 1534. Communication links 1530 and 1534 can be shared for touch data transfer or processor communication between the three touch controller circuits. When no touch data is being transferred, the communication link can operate at maximum speed. When touch data is being transferred between touch controller circuits, the communication link between the processors can operate at a reduced speed (compared with the maximum speed) to allow for parallel simultaneous communications of touch data and inter-processor information.

In the example of FIG. 15, transfer of touch data can be accomplished in two steps. During a first data transfer step, the second touch controller circuit (master) can receive touch data from the first touch controller circuit and touch data from the third touch controller circuit, and the first and third touch controller circuits can receive touch data from the second touch controller circuit. During a second data transfer step, the third touch controller circuit can receive touch data from the first touch controller circuit (having been previously transferred to the intermediate second touch controller circuit) and likewise, the first touch controller circuit can receive touch data from the third touch controller circuit (having been previously transferred to the intermediate second touch controller circuit). Thus, for a configuration with three touch controller circuits as shown in FIG. 15 two steps can be performed to transfer the touch data to each touch controller circuit.

FIG. 16 illustrates an example touch sensing system including four touch controller circuits according to examples of the disclosure. Touch sensing system 1600 can include a first touch controller circuit 1602, a second touch controller circuit 1604, a third touch controller circuit 1606, and a fourth touch controller circuit 1608. First touch controller circuit 1602, third touch controller circuit 1606, and fourth touch controller circuit 1608 can act as slave touch controller circuits, and can each include two high speed ports 1610 and 1612, 1618 and 1620, and 1622 and 1624, respectively. Second touch controller circuit 1604 can act as a master touch controller circuit, and can include two high speed ports 1614 and 1616. High speed port 1612 of the first touch controller circuit 1602 can be coupled to high speed port 1614 of the second touch controller circuit 1604 via communication link 1630. High speed port 1616 of the second touch controller circuit 1604 can be coupled to high speed port 1618 of the third touch controller circuit 1606 via communication link 1634. High speed port 1620 of the third touch controller circuit 1606 can be coupled to high speed port 1622 of the fourth touch controller circuit 1608 via communication link 1636. Communication links 1630, 1634, and 1636 can be shared for touch data transfer or processor communication between the three touch controller circuits (the details of which are not repeated here for simplicity).

In the example of FIG. 16, transfer of touch data can be accomplished in three steps. During a first data transfer step, the second touch controller circuit (master) can receive touch data from the first touch controller circuit and touch data from the third touch controller circuit. Likewise, during the first data transfer step, the third touch controller circuit can receive touch data from the second and fourth touch controller circuits. The first and fourth touch controller circuits can receive touch data from the second and third touch controller circuits, respectively, during the first data transfer step. During a second data transfer step, the third touch controller circuit can receive touch data from the first touch controller circuit (having been previously transferred to the intermediate second touch controller circuit), the first touch controller circuit can receive touch data from the third touch controller circuit (having been previously transferred to the intermediate second touch controller circuit), the second touch controller circuit can receive touch data from the fourth touch controller circuit (having been previously transferred to the intermediate third touch controller circuit), and the fourth touch controller circuit can receive touch data from the second touch controller circuit (having been previously transferred to the intermediate third touch controller circuit). Thus, for a configuration with four touch controller circuits as shown in FIG. 16, three steps can be performed to transfer the touch data to each touch controller circuit.

In other configurations, the number of data transfer steps can be changed. For example, a ring configuration can be used to reduce the number of data transfer steps. As illustrated in FIG. 16, high speed port 1610 can be coupled to high speed port 1624 via communication link 1638. Communication link 1638 can be shared for touch data transfer or processor communication between the first and fourth touch controller circuits. In the example of FIG. 16, transfer of touch data can be accomplished in two steps instead of three steps. During a first data transfer step, the second touch controller circuit (master) and third touch controller circuit can receive the same touch data described above. Additionally, during the first data transfer step the first touch controller circuit can receive touch data from the second and fourth touch controller circuits, and the fourth touch controller circuit can receive touch data from the first and third touch controller circuits respectively. During a second data transfer step, each of the touch controller circuits can receive the remaining data from the non-adjacent touch controller circuit (e.g., via an intermediate data transfer between touch controller circuits in the first step). For example, the first touch controller circuit can receive touch data from the third touch controller circuit, the second touch controller circuit can receive touch data from the fourth touch controller circuit, the third touch controller circuit can receive touch data from the first touch controller circuit, and the fourth touch controller circuit can receive touch data from the second touch controller circuit. Thus, for a configuration with four touch controller circuits in a ring configuration, the number of data transfer steps can be reduced from three steps to two steps to transfer the touch data to each touch controller circuit for parallel processing.

Similarly, referring back to FIG. 15, communication link 1540 between high speed port 1510 and high speed port 1520 (i.e., ring configuration) can be used to reduce the number of data transfer steps for a touch sensing system having three touch controller circuits. Each touch controller circuit can receive touch information from the adjacent touch controller circuit so the number of data transfer steps can be reduced from two to one.

As discussed above, each touch controller circuit can store in memory touch data representative of the entire touch sensor panel (i.e., the entire image of touch) and can process the touch data in parallel using one or more processors and/or one or more hardware accelerators. The touch data can be received on a per-pixel basis (e.g., from scans by one or more touch controller circuits). For example, the sensed signals for each receive channel for each touch controller circuit (corresponding to specific pixels) can be received (for various scans and/or scan steps), processed (e.g., via one or more DSP channels) and the touch data can be stored in memory for subsequent processing (e.g., centroid calculation, etc.). The touch controller circuit can receive the per-pixel information and use a mapping function to keep track of the touch data accumulated from different touch controller circuits in order to properly recreate or reconstruct an image of touch for local processing. Additionally, or alternatively, this mapping can be accomplished by a look-up table (LUT). In order to map the memory locations to physical touch sensor panel electrodes, the touch data can include identifying information that can be used by the touch controller circuit to properly process and store the data. For example, the identifying information can include one or more of the following parameters: (1) touch controller chip ID, (2) channel number, (3) scan type, and (4) scan step number (or time). The above information can be used to identify a specific the physical pixel location within the touch sensor panel. With this information, the touch data collected from the plurality of touch controller circuits and copied to the other touch controller circuits can be used to create a complete image of touch for the touch sensor panel at each touch controller circuit. In the case that only one touch controller circuit is used, some of than the above information can be unnecessary for the mapping function (and the mapping function may be entirely unnecessary). The above described mapping capability can be performed by one or more processors in the touch controller circuit. Additionally or alternatively, the mapping can be done using a predefined map (e.g., as an equation or function of the parameters discussed above).

As discussed above, in some examples, the touch controller chip ID can be hardwired. In other examples, the chip ID can be set on at boot-up or reset, or dynamically adjusted during operation. Some or all of the remaining identifying information (e.g., scan type, scan step/time, etc.) can come from the scan sequencer, for example. In some examples, some or all of the identifying information (e.g., correspondence between the physical touch node and Rx channel) can come from the switching unit (e.g., switching unit 240) coupled between the touch controller chip and a touch sensor panel. This information can also come from the scan sequencer in some examples. The scan sequencer can be a part of the touch controller circuit (or can separate from the touch controller in other examples), and in some cases can be implemented as part of the panel scan engine.

FIG. 20 illustrates an exemplary representation of mapping between physical touch sensor panel electrodes and memory locations according to examples of the disclosure. In the example of FIG. 20, example touch sensor panel 2000 can include 16 touch nodes numbered 1 through 16, though the number of electrodes can be different for other examples. The number associated with each electrode can correspond to a physical location of the touch node in the touch sensor panel configuration. FIG. 20 also illustrates two example touch controller chips—Touch Controller Chip A 2002A and Touch Controller Chip B 2002B—that can correspond to the touch controller chips described above with reference to FIG. 2, for example. For ease of description, only RAM 2008AB and receive (Rx) channels 2004AB and 2006AB are illustrated. Each Rx channel can be coupled (e.g., by switching unit 240) to one or more electrodes during scanning operations to sense touch data. The mapping function performed by mapping units 2010A-B can respectively map the touch data from the Rx channels 2004A-B and 2006A-B to locations in memory 2008A-B to store the touch data. The mapping function performed by mapping units 2010A-B can be implemented using hardware, firmware, or software (e.g., programmable logic blocks, LUT, processor executing instructions for mapping that can be stored, for example, on a non-transitory computer readable storage medium, etc.). In some examples, the mapping unit can be implemented as part of the panel scan engine illustrated in FIG. 2.

The memory locations are illustrated in FIG. 20 by memory arrays 2012A-B including memory locations, such as memory location 2020, which are numbered 1 through 16 for illustration purposes corresponding to the physical location of touch nodes. Although illustrated in FIG. 20 as arranged in a specific pattern, the memory locations do not have to be stored in dedicated memory addresses or in a particular order, though they can be stored in continuous memory locations and/or in predetermined location and/or in a dedicated portion of the memory. In some examples, the memory locations allocated for touch nodes and scans can be predetermined. In some examples, the memory locations allocation for touch nodes and scans can be adjustable and/or selected during operation. In some examples, results from different scans can be stored in different portions of the memory. The mapping units 2010A can be configured to map the touch data received at Rx channels to the memory locations based, for example, on the identifying information. In some examples, the mapping unit for each touch controller chip can use the same memory locations and/or mapping function to store touch data (e.g., with the same identifying information) in the same place, though in other examples, touch controller chips can have different mappings to memory.

FIGS. 21A-21E illustrate an example mapping operation for a mutual capacitance scan according to examples of the disclosure. The example scan configuration illustrated in FIGS. 21-21E can correspond to scanning an example touch sensor panel 2100, using two touch controller chips, each touch controller chip including two Rx channels (e.g., corresponding to the configuration illustrated in FIG. 20). For ease of illustration and description, each of the four steps of the illustrated example mutual capacitance scan of touch sensor panel 2100 is shown in a different figure. FIG. 21A illustrates a first mutual capacitance scan step. FIG. 21A illustrates touch nodes in drive (“D”), sense (“S”) and grounded/fixed voltage (“G”) configurations. For ease of description, reference can be made to legend 2101 that can be representative of groups of four touch nodes in the touch sensor panel 2100. Referring to legend 2101 and the configuration of FIG. 21A, touch nodes in position 1 can be configured as drive nodes (e.g., coupled to a transmit section that can generate stimulation signals), touch nodes in position 2 and 3 can have a fixed voltage (e.g., grounded) and touch nodes in position 4 can be sensed (e.g., coupled to Rx channels). During the first mutual capacitance scan step, the drive nodes can be stimulated and mutual capacitance changes (between the position 1 touch nodes and position 4 touch nodes) can be sensed at the sense nodes. Thus, the first scan step illustrated in FIG. 21A can generate touch data for physical touch nodes 6, 8, 14 and 16 according to the numbering scheme of FIG. 20. During the second, third and fourth mutual capacitance scan steps, the configuration of D, G and S touch nodes can be rotated 90 degrees according to legend 2101, for example. Thus, in the second mutual capacitance scan step in FIG. 21B, touch nodes in position 3 can be sensed, in the third mutual capacitance scan step in FIG. 21C, touch nodes in position 1 can be sensed, and in the fourth mutual capacitance scan steps in FIG. 21D, touch nodes in position 2 can be sensed.

The touch data sensed during each scan step can be mapped to the memory based on the identifying information corresponding to the touch data. FIG. 21E illustrates an example table representing the mapping of touch data to memory locations according to examples of the disclosure. The table maps touch data using identifying information that can include (1) touch controller chip ID, (2) channel number, (3) scan type, and (4) scan step number (or time). For example, the touch data sensed at the second Rx channel (Rx2) of touch controller chip A during the second step of a mutual capacitance scan can correspond to physical touch node 5 in the numbering scheme of FIG. 20. The touch data can be stored in memory in a location corresponding to the touch data for this physical touch node (and scan type). As another example, the touch data sensed at the first Rx channel (Rx1) of touch controller chip B during the third step of a mutual capacitance scan can correspond to physical touch node 11 in the numbering scheme of FIG. 20 and can be stored in memory in a location corresponding to the touch data for this physical touch node (and scan type).

FIGS. 22A-22E illustrate an example mapping operation for a self-capacitance scan according to examples of the disclosure. The example scan configuration illustrated in FIGS. 22-22E can correspond to scanning an example touch sensor panel 2200 using two touch controller chips, each touch controller chip including two Rx channels (e.g., corresponding to the configuration illustrated in FIG. 20). For ease of illustration, each of the four steps of the illustrated example self-capacitance scan of touch sensor panel 2200 is shown in a different figure. FIG. 22A illustrates a first self-capacitance scan step (e.g., a fully boot-strapped self-capacitance scan). FIG. 22A illustrates touch nodes in drive (“D”) and drive/sense (“D/S”) configurations. During the first step of the illustrated scan, the drive nodes can be stimulated and the drive/sense nodes can be driven and sensed. Thus, the first scan step can generate touch data for physical touch nodes 4, 7, 12 and 14 according to the numbering scheme of FIG. 20. During the second, third and fourth self-capacitance scan steps, other touch nodes can be sensed. Thus, in the second self-capacitance scan step in FIG. 22B, physical touch nodes 3, 8, 11 and 15 can be sensed, in the third self-capacitance scan step in FIG. 22C, physical touch nodes 1, 6, 10 and 13 can be sensed, and in the fourth self-capacitance scan steps in FIG. 22D, physical touch nodes 2, 5, 9 and 16 can be sensed.

The touch data sensed during each scan step can be mapped to the memory based on the identifying information corresponding to the touch data. FIG. 22E illustrates an example table representing the mapping of touch data to memory locations according to examples of the disclosure. The table maps touch data using identifying information that can include (1) touch controller chip ID, (2) channel number, (3) scan type, and (4) scan step number (or time). For example, the touch data sensed at the first Rx channel (Rx1) of touch controller chip A during the first step of a self-capacitance scan can correspond to physical touch node 4 in the numbering scheme of FIG. 20. The touch data can be stored in memory in a location corresponding to the touch data for this physical touch node (and scan type). As another example, the touch data sensed at the second Rx channel (Rx2) of touch controller chip B during the fourth step of a self-capacitance scan can correspond to physical touch node 16 in the numbering scheme of FIG. 20 and can be stored in memory in a location corresponding to the touch data for this physical touch node (and scan type).

It should be understood that the mutual capacitance and self-capacitance scans and mapping described in FIGS. 21-21E and 22A-22E are exemplary and other scan configurations and mappings are possible. For example, the scan steps can be performed in a different order and different touch nodes can be scanned during different steps than illustrated. Additionally, a different number of touch nodes, receive channels and/or touch controller chips can be used, which can change the scanning operations (configurations and number of steps) and mapping operations.

For the example mapping described with respect to FIGS. 20, 21A-21E and 22A22E, the image of touch can be reconstructed based on the touch data and corresponding physical location of the touch node. For example, the processing circuitry can access touch data stored at memory locations corresponding to the physical touch nodes and process the data accordingly. In other examples, rather than mapping the data to dedicated memory location, the touch data can be stored in memory along with some or all of the identifying information. In such examples, the mapping function can be performed during processing of the data stored in memory (e.g., rather than mapping before storing the data in memory).

As discussed herein, the touch controller chips can transfer touch data to other touch controller chips such that each touch controller chip can store touch data forming an image of touch. In some examples, the data transferred can include the identifying information (e.g., touch controller chip ID, channel number, scan type, and scan step number/time), which can be used by the memory mapping unit of the touch controller receiving the data to store the transferred touch data in the correct location. In other examples, different information can be transferred. For example, the touch data, chip ID and physical touch node location (e.g., without the scan type and scan step) can be transferred and a different mapping function (e.g., implemented by mapping unit 2010A-B or another mapping unit) can map the transferred touch data to memory.

FIG. 17 illustrates an example computing system for sequencing scanning operations according to the examples of the disclosure. FIG. 17 illustrates computing system 1700 which can include a host processor 1702, one or more touch controller circuits 1704, a peripheral switching unit 1706 (that can include one or more switching ASICs), and a touch sensor panel 1708 (or a touch screen). Scan sequencer 1710 can be implemented in each of the one or more touch controller circuits 1704. Host processor 1702 can generate synchronization signals that can be transmitted to the one or more touch controller circuits 1704. In other examples, the synchronization signals can also be transmitted to the one or more touch controller circuits 1704, via a display controller (not shown). Additionally, as discussed above, the scan sequencer of a touch controller circuit can also receive synchronization signals transmitted to or between more than one touch controller circuit. The scan sequencer 1710 can receive the synchronization signals and can decode or otherwise use the synchronization signals to determine the appropriate scanning functionality to be implemented at a given time (i.e., execution of a scan plan). In some examples, the synchronization signals can be decoded to identify whether and/or when a display can be performing a display refresh or an intra-frame pause (IFP). Performing some sensing and scanning operations during IFPs can improve performance because the interference from display refresh operations can be reduced during IFPs. Thus, the synchronization signals can be used by the scan sequencer 1710 to configure and/or execute one or more scanning operations including partial or complete sensing and scanning operations. Executing the one or more scans can include starting and stopping scans. Additionally, in some examples, the scan sequencer can also have access to additional information regarding the relative length and spacing of IFPs in a display frame in order to properly sequence the scans.

The scan sequencer can also perform the memory mapping discussed above to properly store touch data in the memory of the touch controller circuit based on information including chip ID, scan type, scan step and channel number.

FIG. 18 illustrates an example timing diagram for intra-frame pauses in a display frame and synchronization signals according to examples of the disclosure. Timing diagram 1800 shows a display frame, including one or more IFPs, at which time the display can be in a blanking period (vertical and/or horizontal blanking), for example. During the remaining portions of the display frame, the display can be performing an active display refresh which can cause interference with some scanning or sensing operations. As a result, the scan sequencer causes sensing or scanning operations to be performed in light of the state of the display operation (e.g., IFP or Display Refresh). The synchronization signals generated by the host processor can provide information to the scan sequencer about the operating mode of the display. For example, timing diagram 1810 includes three synchronization signals. When SYNC0 is high and SYNC1 and SYNC2 are low, the scan sequencer can identify IFP 1802. Likewise, when SYNC1 is high and SYNC0 and SYNC2 are low, the scan sequencer can identify IFP 1804. Similarly, when SYNC0 and SYNC2 are high and SYNC1 is low, the scan sequencer can identify IFP 1806. The meaning of the synchronization signals combinations illustrated in FIG. 18 is for purposes of example. Fewer or more synchronization signals can be used and the information encoded in the synchronization signals to indicate IFPs can be different than shown.

Returning to FIG. 17, scan sequencer 1710 can control the operation of switching unit 1706 (peripheral switching unit). The operation of switching unit 1706 can be based on the decoding of synchronization signals as well as on the scan plan (e.g., what scan or step of a scan is to be executed). In some examples, scan sequencer 1710 can cause a major reprogramming of the switching unit 1706. For example, when transitioning between scan types that require major reconfigurations of the coupling between the one or more touch controller circuits and the touch sensor panel (e.g., from a mutual capacitance row-to-column scan (i.e., driving rows and sensing columns) to a stylus/pen scan (i.e., sensing both rows and columns)), the scan sequencer can transmit (e.g., via an SPI or I2C channel) instructions to reconfigure the switching unit 1706 to configure the coupling for the upcoming sensing or scanning operation.

Additionally or alternatively, scan sequencer 1710 can transmit other information to cause the switch to make minor adjustments. For example, when walking through a plurality of steps of a scan, the scan sequencer can update which pixel is coupled to the receive channel without having to reconfigure the switching unit 1706 entirely. For example, when walking through the steps of a self-capacitance scan, each receive channel can be used to scan a plurality of electrodes, one electrode per step. As a result the signals from the scan sequencer can indicate a new step or a new pixel and the switching circuit can update the coupling to scan the appropriate pixel based on the information (e.g., the scan step). The minor adjustments to switching unit 1706 can also occur during steps of other sensing or scanning operations than self-capacitance scans.

The scans performed by a touch sensing system can include one or more of: a mutual capacitance row-to-column or column-to-row scan, a mutual capacitance row-to-row scan, a mutual capacitance column-to-column scan, a self-capacitance row scan, a self-capacitance column scan, a stylus scan (e.g., to sense an active stylus), a stylus spectral analysis scan, and a touch spectral analysis scan, although it is to be understood that other scan events can also be performed and that some scan events can be performed in a number of steps.

FIG. 19 illustrates an example of scanning operations during a display period that can be controlled by a scan sequencer according to examples of the disclosure. As discussed above, during periods of active display refresh, interference from the display can degrade scanning performance. Accordingly, during display refresh periods, the scan sequencer can idle (i.e., not perform a scan). During the first IFP, the scan sequencer can execute M scans, during a second IFP, the scan sequencer can execute L scans, and during an Nth IFP, the scan sequencer can execute K scans. The scans performed during each of the IFPs can correspond to part of or a complete one of the one or more scan discussed above. Additionally, depending on the number of DSP channels for a sense channel, the sensed signals can be processed in parallel to perform simultaneous scans. For example, there can be N DSP channels (illustrated by additional columns in FIG. 19) to perform concurrent or partially concurrent scans. For example, the scan sequencer can cause the touch controller circuit to execute a mutual capacitance scan and also perform a mutual capacitance spectral analysis of the received touch data. Additionally or alternatively, the scan sequencer can cause the touch controller circuit to execute a self-capacitance scan and also perform a stylus/pen spectral analysis scan of the received touch data.

In some examples, the sequence of scans in a scan plan for a first IFP in a display frame can include a coarse scan used to coarsely detect touch events. After the coarse scan, additional scans in the first IFP or in subsequent IFPs can be performed. In some examples, if after performing the coarse detection scans no touch events are detected (or some other conditions are detected), the touch controller circuit can generate an abort command and the scan sequencer can abort one or more scans from the first IFP and/or one or more scans from the remaining IFPs. Additionally, one or more of the IFPs can include a coarse scan, the results from which can be used to generate abort commands for one or more subsequent scans during one or more IFPs.

Therefore, according to the above, some examples of the disclosure are directed to an integrated circuit. The integrated circuit can comprise a receive section including a plurality of receive channels configured to receive signals from sensing operations, a memory configured to store data based on the signals from the receive section, and a plurality of processing circuits. At least two of the plurality of processing circuits can be configured to directly access the memory. One or more of the plurality of processing circuits can be configured to process the data stored in memory. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the integrated circuit can further comprise a switching unit coupled between the memory and at least one of the plurality of processing circuits. The switching unit can be configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the switching unit can be coupled between the memory and at least one hardware accelerator. The switching unit can be configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the at least one hardware accelerator circuit. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the memory can include a plurality of access ports for simultaneous direct access of the memory by one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the plurality of processing circuits can include one or more hardware accelerators configured to process the data stored in the memory. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one of the plurality of processing circuits is configured to sequence the processing of the data stored in memory by the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, sequencing the processing of the data stored in memory can include distributing the processing of one or more algorithms between the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the one or more hardware accelerators can include a first hardware accelerator to perform one or more of scaling the data stored in memory, subtracting a baseline amount from the data stored in memory, and adding or subtracting an offset to the data stored in memory. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the one or more hardware accelerators can include a first hardware accelerator to generate a mapping of pixel locations with signals above a threshold and below a threshold. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the one or more hardware accelerators can include a first hardware accelerator to perform an image diffusion algorithm. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the one or more hardware accelerators can include a first hardware accelerator configured to convert data represented by a magnitude component and a phase component into data represented by an in-phase component and a quadrature component, or to convert data represented by the in-phase component and the quadrature component a magnitude component into data represented by the magnitude component and the phase component. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the integrated circuit can further comprise an interface with one or more ports for transmitting first touch signals to, or receiving second touch signals from, another integrated circuit. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one processing circuit of the plurality of processing circuits can be configured to generate an image of touch from the signals received by receive section or data stored in memory based on one or more parameters associated with the signals or data. The parameters can include one or more of a chip identifier, a scan step, a scan type and a receive channel number. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one processing circuit of the plurality of processing circuits can be configured to map information associated with the signals or data stored in memory to physical pixel locations in order to generate the image of touch.

Some examples of the disclosure are directed to an apparatus (or a system). The apparatus can comprise a touch sensor panel, a plurality of touch controller integrated circuits, and a plurality of switching circuits coupled between the plurality of touch controller integrated circuits and the touch sensor panel. Additionally or alternatively to one or more of the examples disclosed above, in some examples, each touch controller integrated circuit can be coupled to a plurality of switching circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the one or more of the plurality of touch controller integrated circuits can include a receive section including a plurality of receive channels configured to receive signals from sensing operations, a memory configured to store data based on the signals from the receive section, and a plurality of processing circuits. At least two of the plurality of processing circuits can be configured to directly access the memory. One or more of the plurality of processing circuits can be configured to process the data stored in memory. Additionally or alternatively to one or more of the examples disclosed above, in some examples, one or more of the plurality of touch controller integrated circuits can further include a switching unit coupled between the memory and at least one of the plurality of processing circuits. The switching unit can be configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the switching unit can be coupled between the memory and at least one hardware accelerator. The switching unit can be configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the at least one hardware accelerator circuit. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the memory of one or more of the plurality of touch controller integrated circuits can include a plurality of access ports for simultaneous direct access of the memory by one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, one or more of the plurality of touch controller integrated circuits can further include one or more hardware accelerator configured to process the data stored in the memory. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one of the plurality of processing circuits of the one or more of the plurality of touch controller circuits can be configured to sequence the processing of the data stored in memory by the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, sequencing the processing of the data stored in memory can include distributing the processing of one or more algorithms between the one or more of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the plurality of touch controller integrated circuits can include an interface with one or more ports for transmitting signals to or receiving signals from another touch controller integrated circuit. Additionally or alternatively to one or more of the examples disclosed above, in some examples, each of the plurality of touch controller integrated circuits can be coupled to one or more of the other touch controller integrated circuits in a daisy chain configuration. Additionally or alternatively to one or more of the examples disclosed above, in some examples, each of the plurality of touch controller integrated circuits can be coupled to another two touch controller integrated circuits in a daisy chain with a ring configuration. Additionally or alternatively to one or more of the examples disclosed above, in some examples, each of the plurality of touch controller integrated circuits can perform one or more scan steps and the data stored in memory based on the received signals can be transferred to each of the plurality of touch controllers such that each touch controller can store in memory the data from the plurality of touch controllers. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one processing circuit of the plurality of processing circuits in each of the plurality of touch controller integrated circuits can be configured to generate an image of touch from data received from execution of one or more scans of the touch sensor panel based on one or more parameters associated with the signals. The parameters can include one or more of a chip identifier, a scan step, a scan type and a receive channel number. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the at least one processing circuit of the plurality of processing circuits can be configured to map information associated with the signals or data stored in memory to physical pixel locations of the touch sensor panel in order to generate the image of touch. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the sensing operations can include a stylus scan to sense stimulation signals generated by an active stylus.

Some examples of the disclosure are directed to a method for performing sensing scans for a touch-sensitive device. The method can comprise receiving synchronization signals, decoding the synchronization signals, and configuring a touch controller for performing the sensing scans based on the decoded synchronization signals. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the synchronization signals can be received from one or more of a host processor and a display controller. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise identifying a period of display operation corresponding to an intra-frame pause based on the decoded synchronization signal. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise generating signals for reprogramming a switching unit based on the decoded synchronization signals and a scan plan. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise generating signals for adjusting a coupling of a switching unit based on a sensing scan step. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise generating signals for reprogramming or adjusting a coupling of the switching unit based on the decoded synchronization signals and output from processing touch data of one or more scans. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise processing the data at each of the plurality of touch controller integrated circuits to generate an image of touch from the execution of one or more scans of the touch sensor panel. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise aborting one or more scans based on results from one or more scans performed by the touch controller. Some examples of the disclosure are directed to an electronic device with a touch-sensitive display that can be configured to perform the method of any of the examples disclosed above. Some examples of the disclosure are directed to a computer program having instructions which when executed by an electronic device with a touch-sensitive display can cause the electronic device to perform the method of any of the examples disclosed above. Some examples of the disclosure are directed to a computer readable medium having stored thereon a computer program according any of the examples disclosed above. Some examples of the disclosure are directed to a non-transitory computer readable storage medium. The computer readable medium can contain instructions that, when executed by a processor, can perform the method of any of the examples disclosed above.

Some examples of the disclosure are directed to an apparatus for sequencing sensing scans. The apparatus can comprise a receive section including one or more sense channels and logic configured to decode synchronization signals, configure the receive section to perform a scan based on the decoded synchronization signals, and perform the scan. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the apparatus can further comprise at least one of a host processor and a display controller. The synchronization signals can be received from the one or more of the host processor and the display controller. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the logic can be further configured to identify a period of display operation corresponding to an intra-frame pause based on the decoded synchronization signal. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the logic can further configured to generate signals for reprograming a switching unit based on the decoded synchronization signals and a scan plan. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the logic can be further configured to generate signals for adjusting a coupling of a switching unit based on a sensing scan step. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the logic can be further configured to generate signals for reprogramming or adjusting a coupling of the switching unit based on the decoded synchronization signals and output from processing touch data of one or more scans. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the logic can be further configured to abort one or more scans based on results from the performed scan.

Some examples of the disclosure are directed to an integrated circuit. The integrated circuit can comprise means for receiving signals from sensing operations, means for storing data based on the received signals; and a plurality of processing means. At least two of the plurality of processing means can be configured to directly access the storing means. At least one of the plurality of processing means can be configured to process the stored data. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the integrated circuit can further comprise switching means coupled between the storing means and at least one of the plurality of processing means. The switching means can be configured to dynamically couple one or more portions of the storing means to one or more inputs or one or more outputs of the at least one of the plurality of processing means. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the plurality of processing means can include one or more hardware accelerator means configured to process the data stored in the storing means. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the integrated circuit can further comprise communication means for interfacing with another integrated circuit. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the integrated circuit can further comprising means for generating an image of touch for touch sensing means based on one or more parameters associated with the stored data. The parameters can include one or more of a chip identifier, a scan step, a scan type and a receive channel number.

Some examples of the disclosure are directed to a method for processing data from sensing scans in an integrated circuit comprising a plurality of sense channels, a storage device, and a plurality of processing circuits. The method can comprise receiving signals at the plurality of sense channels from the sensing scans, storing first data based on the signals received at the plurality of sense channels in the storage device, and simultaneously processing the data in the storage device by the plurality of processing circuits, the data in the storage device including the first data. At least two of the plurality of processing circuits can simultaneously access the storage device. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise switching a coupling between data storage locations and one or more inputs or one or more outputs of at least one of the plurality of processing circuits. Additionally or alternatively to one or more of the examples disclosed above, in some examples, at least one of the plurality of processing circuits can be a hardware accelerator configured to process the data. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the hardware accelerator can perform operations including one or more of scaling the data, subtracting a baseline amount from the data, adding or subtracting an offset to the data, generating a mapping of pixel locations with signals above a first threshold or below a second threshold, diffusing an image, and converting between a magnitude and phase representation and an in-phase component and quadrature component representation. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise receiving second data from another integrated circuit and storing the second data in the storage device. The data in the storage device processed by the plurality of processing circuits can further include the second data. Additionally or alternatively to one or more of the examples disclosed above, in some examples, the method can further comprise generating an image of touch from the data in the storage device based on one or more parameters associated with the first data or the second data. The parameters can include one or more of a circuit identifier, a scan step, a scan type and a receive channel number. Some examples of the disclosure are directed to a non-transitory computer readable storage medium. The computer readable medium can contain instructions that, when executed by a processor, can perform the method of the examples disclosed above.

Although examples of this disclosure have been fully described with reference to the accompanying drawings, it is to be noted that various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of examples of this disclosure as defined by the appended claims.

Claims

1. An integrated circuit apparatus comprising: a touch sensor panel;a plurality of touch controller integrated circuits, one or more of the plurality of touch controller integrated circuits comprising:a plurality of receive channels configured to receive signals from sensing operations;a memory configured to store data based on the signals from the plurality of receive channels;a plurality of processing circuits, wherein at least two of the plurality of processing circuits are configured to access the memory using Direct Memory Access, and wherein the plurality of processing circuits includes one or more hardware accelerators configured to process data accessed from the memory; andswitching circuitry coupled between the memory and at least one of the plurality of processing circuits, wherein the switching circuitry is configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the one or more of the plurality of processing circuits; anda plurality of switching circuits coupled between the plurality of touch controller integrated circuits and the touch sensor panel.
2. The integrated circuit apparatus of claim 1, wherein the one or more hardware accelerators comprises a plurality of hardware accelerators, wherein at least one of the plurality of processing circuits of the one or more of the plurality of touch controller circuits is configured to sequence the processing of the data accessed from the memory by the plurality of hardware accelerators, wherein the one or more of the plurality of touch controller integrated circuits further comprise: switching circuitry coupled between the memory and the plurality of hardware accelerators, the switching circuitry is configured to dynamically couple one or more banks of the memory to one or more inputs or one or more outputs of the plurality of hardware accelerators according the sequencing of the processing.
3. The integrated circuit apparatus of claim 1, wherein the memory includes a plurality of access ports for simultaneous direct access of the memory by one or more of the plurality of processing circuits.
4. The integrated circuit apparatus of claim 1, wherein sequencing the processing of the data accessed from the memory of the one or more of the plurality of touch controller integrated circuits includes distributing processing of one or more algorithms between the one or more of the plurality of processing circuits.
5. The integrated circuit apparatus of claim 1, wherein the one or more hardware accelerators include a first hardware accelerator to perform one or more of scaling the data accessed from the memory, subtracting a baseline amount from the data accessed from the memory, and adding or subtracting an offset to the data accessed from the memory.
6. The integrated circuit apparatus of claim 1, wherein the one or more hardware accelerators include a first hardware accelerator to generate a mapping of touch node locations with signals above a first threshold and below a second threshold.
7. The integrated circuit apparatus of claim 1, wherein the one or more hardware accelerators include a first hardware accelerator to perform an image diffusion algorithm.
8. The integrated circuit apparatus of claim 1, wherein the one or more hardware accelerators include a first hardware accelerator configured to convert data represented by a magnitude component and a phase component into data represented by an in-phase component and a quadrature component, or to convert data represented by the in-phase component and the quadrature component into data represented by the magnitude component and the phase component.
9. The integrated circuit apparatus of claim 1, wherein the one or more of the plurality of touch controller integrated circuits further comprise: an interface with one or more ports for transmitting first touch signals to, or receiving second touch signals from, another of the plurality of touch controller integrated circuits.
10. The integrated circuit apparatus of claim 1, wherein at least one processing circuit of the plurality of processing circuits in each of the plurality of touch controller integrated circuits is configured to generate an image of touch from execution of one or more scans of the touch sensor panel based on one or more parameters associated with the signals or the data, the parameters including one or more of a chip identifier, a scan step, a scan type and a receive channel number.
11. The integrated circuit apparatus of claim 10, wherein the at least one processing circuit of the plurality of processing circuits is configured to map information associated with the signals or the data stored in the memory to physical touch node locations of the touch sensor panel in order to generate the image of touch.
12. The integrated circuit apparatus of claim 1, wherein each touch controller integrated circuit is coupled to two or more of the plurality of switching circuits.
13. The integrated circuit apparatus of claim 1, wherein each of the plurality of touch controller integrated circuits performs a plurality of scan steps and the data stored in the memory based on the received signals are transferred to each of the plurality of touch controller integrated circuits such that each touch controller stores in its respective memory the data from the plurality of touch controller integrated circuits.
14. A method for performing sensing scans and for processing data from the sensing scans for a touch-sensitive device including a plurality of touch controller integrated circuits and a plurality of switching circuits coupled between the plurality of touch controller integrated circuits and a touch sensor panel, one or more of the plurality of integrated circuits comprising a plurality of sense channels, a storage device, and a plurality of processing circuits, the method comprising: decoding synchronization signals;configuring the plurality of touch controller integrated circuits for performing the sensing scans based on the decoded synchronization signals;performing one or more scan steps at each of the plurality of touch controller integrated circuits, wherein performing the one or more scan steps comprises: receiving signals at the plurality of sense channels of each of the plurality of touch controller integrated circuits from the one or more steps of the sensing scans; andstoring data based on the signals received at the plurality of sense channels in the storage device of each of the plurality of touch controller integrated circuits;transferring the data based on signals received in response to the one or more scanning steps between the plurality of touch controller integrated circuits; andprocessing the data at the one or more of the plurality of touch controller integrated circuits to generate an image of touch from the execution of one or more scans of the touch sensor panel, wherein processing the data comprises simultaneously processing the data in the storage device of the one or more of the plurality of touch controller integrated circuits by the plurality of processing circuits, wherein: the plurality of processing circuits includes one or more hardware accelerators, andat least two of the plurality of processing circuits simultaneously access the storage device.
15. The method of claim 14, further comprising: switching a coupling between data storage locations and one or more inputs or one or more outputs of at least one of the plurality of processing circuits.
16. The method of claim 14, wherein the one or more hardware accelerators perform operations including one or more of scaling the data, subtracting a baseline amount from the data, adding or subtracting an offset to the data, generating a mapping of touch node locations with signals above a first threshold or below a second threshold, diffusing an image, and converting between a magnitude and phase representation and an in-phase component and quadrature component representation.
17. The method of claim 14, wherein generating the image of touch is based on parameters associated with the data from each of the plurality of touch controller integrated circuits, the parameters including a circuit identifier, a scan step, a scan type and a receive channel number.
18. The method of claim 14, further comprising: generating signals for reprogramming the plurality of switching circuits based on the decoded synchronization signals and a scan plan.
19. The method of claim 14, further comprising: generating signals for reprogramming or adjusting a coupling of one or more of the plurality of switching circuits based on the decoded synchronization signals and output from processing touch data of one or more scans.
20. The method of claim 14, wherein transferring the data based on signals received in response to the one or more scanning steps comprises: transferring a first portion of the data between a first touch controller integrated circuit and a second touch controller integrated circuit; andtransferring a second portion of the data between the first touch controller integrated circuit and the second touch controller integrated circuit, and simultaneously transferring the first portion of the data from the first scanning step between the second touch controller integrated circuit and a third touch controller integrated circuit.
21. A non-transitory computer readable storage medium having stored thereon instructions, which when executed by a processor, perform a method for performing sensing scans and for processing data from the sensing scans for a touch-sensitive device including a plurality of touch controller integrated circuits and a plurality of switching circuits coupled between the plurality of touch controller integrated circuits and a touch sensor panel, one or more of the plurality of integrated circuits comprising a plurality of sense channels, a storage device, and a plurality of processing circuits, the method comprising: decoding synchronization signals;configuring the plurality of touch controller integrated circuits for performing the sensing scans based on the decoded synchronization signals;performing one or more scan steps at each of the plurality of touch controller integrated circuits, wherein performing the one or more scan steps comprises: receiving signals at the plurality of sense channels of each of the plurality of touch controller integrated circuits from the one or more steps of the sensing scans; andstoring data based on the signals received at the plurality of sense channels in the storage device of each of the plurality of touch controller integrated circuits;transferring the data based on signals received in response to the one or more scanning steps between the plurality of touch controller integrated circuits; andprocessing the data at the one or more of the plurality of touch controller integrated circuits to generate an image of touch from the execution of one or more scans of the touch sensor panel, wherein processing the data comprises simultaneously processing the data in the storage device of the one or more of the plurality of touch controller integrated circuits by the plurality of processing circuits, wherein: the plurality of processing circuits includes one or more hardware accelerators, andat least two of the plurality of processing circuits simultaneously access the storage device.
22. The non-transitory computer readable storage medium of claim 21, further comprising: switching a coupling between data storage locations and one or more inputs or one or more outputs of at least one of the plurality of processing circuits.
23. The non-transitory computer readable storage medium of claim 21, wherein generating the image of touch is based on parameters associated with the first data or the second data, the parameters including a circuit identifier, a scan step, a scan type and a receive channel number.
24. The non-transitory computer readable storage medium of claim 21, wherein the one or more hardware accelerators perform operations including one or more of scaling the data, subtracting a baseline amount from the data, adding or subtracting an offset to the data, generating a mapping of touch node locations with signals above a first threshold or below a second threshold, diffusing an image, and converting between a magnitude and phase representation and an in-phase component and quadrature component representation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/131,242 filed on Mar. 10, 2015, the entire disclosure of which is herein incorporated by reference for all purposes.

US Referenced Citations (407)

Number	Name	Date	Kind
4087625	Dym et al.	May 1978	A
4090092	Serrano	May 1978	A
4304976	Gottbreht et al.	Dec 1981	A
4475235	Graham	Oct 1984	A
4550221	Mabusth	Oct 1985	A
4659874	Landmeier	Apr 1987	A
5194862	Edwards	Mar 1993	A
5317919	Awtrey	Jun 1994	A
5459463	Gruaz et al.	Oct 1995	A
5483261	Yasutake	Jan 1996	A
5488204	Mead et al.	Jan 1996	A
5543590	Gillespie et al.	Aug 1996	A
5631670	Tomiyoshi et al.	May 1997	A
5825352	Bisset et al.	Oct 1998	A
5835079	Shieh	Nov 1998	A
5841078	Miller et al.	Nov 1998	A
5844506	Binstead	Dec 1998	A
5880411	Gillespie et al.	Mar 1999	A
5914465	Allen et al.	Jun 1999	A
6057903	Colgan et al.	May 2000	A
6137427	Binstead	Oct 2000	A
6163313	Aroyan et al.	Dec 2000	A
6188391	Seely et al.	Feb 2001	B1
6239788	Nohno et al.	May 2001	B1
6310610	Beaton et al.	Oct 2001	B1
6323846	Westerman et al.	Nov 2001	B1
6452514	Philipp	Sep 2002	B1
6456952	Nathan	Sep 2002	B1
6690387	Zimmerman et al.	Feb 2004	B2
6730863	Gerpheide et al.	May 2004	B1
6970160	Mulligan et al.	Nov 2005	B2
7015894	Morohoshi	Mar 2006	B2
7030860	Hsu et al.	Apr 2006	B1
7129935	Mackey	Oct 2006	B2
7138686	Banerjee et al.	Nov 2006	B1
7180508	Kent et al.	Feb 2007	B2
7184064	Zimmerman et al.	Feb 2007	B2
7337085	Soss	Feb 2008	B2
7395717	DeAngelis et al.	Jul 2008	B2
7412586	Rajopadhye et al.	Aug 2008	B1
7504833	Sequine	Mar 2009	B1
7538760	Hotelling et al.	May 2009	B2
7548073	Mackey et al.	Jun 2009	B2
7639234	Orsley	Dec 2009	B2
7663607	Hotelling et al.	Feb 2010	B2
7719523	Hillis	May 2010	B2
7701539	Shih et al.	Aug 2010	B2
7907126	Yoon et al.	Mar 2011	B2
7932898	Philipp et al.	Apr 2011	B2
8026904	Westerman	Sep 2011	B2
8040321	Peng et al.	Oct 2011	B2
8040326	Hotelling et al.	Oct 2011	B2
8045783	Lee et al.	Oct 2011	B2
8058884	Betancourt	Nov 2011	B2
8068097	GuangHai	Nov 2011	B2
8120371	Day et al.	Feb 2012	B2
8125312	Orr	Feb 2012	B2
8169421	Wright et al.	May 2012	B2
8223133	Hristov	Jul 2012	B2
8258986	Makovetskyy	Sep 2012	B2
8259078	Hotelling et al.	Sep 2012	B2
8283935	Liu et al.	Oct 2012	B2
8319747	Hotelling et al.	Nov 2012	B2
8339286	Cordeiro	Dec 2012	B2
8441464	Lin et al.	May 2013	B1
8479122	Hotelling et al.	Jul 2013	B2
8484838	Badaye et al.	Jul 2013	B2
8487898	Hotelling	Jul 2013	B2
8507811	Hotelling et al.	Aug 2013	B2
8508495	Hotelling et al.	Aug 2013	B2
8537126	Yousefpor et al.	Sep 2013	B2
8542208	Krah et al.	Sep 2013	B2
8593410	Hong et al.	Nov 2013	B2
8593425	Hong et al.	Nov 2013	B2
8614688	Chang	Dec 2013	B2
8680877	Lee et al.	Mar 2014	B2
8760412	Hotelling et al.	Jun 2014	B2
8773146	Hills et al.	Jul 2014	B1
8810543	Kurikawa	Aug 2014	B1
8884917	Seo	Nov 2014	B2
8902172	Peng et al.	Dec 2014	B2
8922521	Hotelling et al.	Dec 2014	B2
8957874	Elias	Feb 2015	B2
8976133	Yao et al.	Mar 2015	B2
8982096	Hong et al.	Mar 2015	B2
8982097	Kuzo	Mar 2015	B1
9001082	Rosenberg et al.	Apr 2015	B1
9035895	Bussat et al.	May 2015	B2
9075463	Pyo et al.	Jul 2015	B2
9086774	Hotelling et al.	Jul 2015	B2
9189119	Liao	Nov 2015	B2
9261997	Chang et al.	Feb 2016	B2
9292137	Kogo	Mar 2016	B2
9329674	Lee et al.	May 2016	B2
9329723	Benbasat et al.	May 2016	B2
9372576	Westerman	Jun 2016	B2
9582131	Elias	Feb 2017	B2
9690397	Shepelev et al.	Jun 2017	B2
9785295	Yang	Oct 2017	B2
9804717	Schropp, Jr.	Oct 2017	B2
9874975	Benbasat et al.	Jan 2018	B2
9880655	O'Connor	Jan 2018	B2
9886141	Yousefpor	Feb 2018	B2
9904427	Co	Feb 2018	B1
9996175	Hotelling et al.	Jun 2018	B2
10001888	Hong	Jun 2018	B2
10061433	Imai	Aug 2018	B2
10289251	Shih et al.	May 2019	B2
20020152048	Hayes	Oct 2002	A1
20030076325	Thrasher	Apr 2003	A1
20030164820	Kent	Sep 2003	A1
20030210235	Roberts	Nov 2003	A1
20040017362	Mulligan et al.	Jan 2004	A1
20040061687	Kent et al.	Apr 2004	A1
20040090429	Geaghan et al.	May 2004	A1
20040188151	Gerpheide et al.	Sep 2004	A1
20040239650	Mackey	Dec 2004	A1
20050007353	Smith et al.	Jan 2005	A1
20050012724	Kent	Jan 2005	A1
20050069718	Voss-Kehl et al.	Mar 2005	A1
20050073507	Richter et al.	Apr 2005	A1
20050083307	Aufderheide et al.	Apr 2005	A1
20050126831	Richter et al.	Jun 2005	A1
20050146509	Geaghan et al.	Jul 2005	A1
20050239532	Inamura	Oct 2005	A1
20050270039	Mackey	Dec 2005	A1
20050270273	Marten	Dec 2005	A1
20050280639	Taylor et al.	Dec 2005	A1
20060001640	Lee	Jan 2006	A1
20060017710	Lee et al.	Jan 2006	A1
20060038791	Mackey	Feb 2006	A1
20060132463	Lee et al.	Jun 2006	A1
20060146484	Kim et al.	Jul 2006	A1
20060197753	Hotelling	Sep 2006	A1
20060202969	Hauck	Sep 2006	A1
20060238522	Westerman et al.	Oct 2006	A1
20060267953	Peterson et al.	Nov 2006	A1
20060278444	Binstead	Dec 2006	A1
20060279548	Geaghan	Dec 2006	A1
20060293864	Soss	Dec 2006	A1
20070008299	Hristov	Jan 2007	A1
20070012665	Nelson et al.	Jan 2007	A1
20070023523	Onishi	Feb 2007	A1
20070074914	Geaghan et al.	Apr 2007	A1
20070075982	Morrison et al.	Apr 2007	A1
20070216637	Ito	Sep 2007	A1
20070216657	Konicek	Sep 2007	A1
20070229468	Peng et al.	Oct 2007	A1
20070229470	Snyder et al.	Oct 2007	A1
20070247443	Philipp	Oct 2007	A1
20070262963	Xiao-Ping et al.	Nov 2007	A1
20070262969	Pak	Nov 2007	A1
20070268273	Westerman et al.	Nov 2007	A1
20070268275	Westerman et al.	Nov 2007	A1
20070279395	Philipp	Dec 2007	A1
20070283832	Hotelling	Dec 2007	A1
20070285365	Lee	Dec 2007	A1
20080006454	Hotelling	Jan 2008	A1
20080007533	Hotelling	Jan 2008	A1
20080018581	Park et al.	Jan 2008	A1
20080024456	Peng et al.	Jan 2008	A1
20080036742	Garmon	Feb 2008	A1
20080042986	Westerman et al.	Feb 2008	A1
20080042987	Westerman et al.	Feb 2008	A1
20080042992	Kim	Feb 2008	A1
20080047764	Lee et al.	Feb 2008	A1
20080062140	Hotelling et al.	Mar 2008	A1
20080062148	Hotelling et al.	Mar 2008	A1
20080062151	Kent	Mar 2008	A1
20080074398	Wright	Mar 2008	A1
20080136787	Yeh et al.	Jun 2008	A1
20080136792	Peng et al.	Jun 2008	A1
20080158145	Westerman	Jul 2008	A1
20080158146	Westerman	Jul 2008	A1
20080158167	Hotelling et al.	Jul 2008	A1
20080158172	Hotelling et al.	Jul 2008	A1
20080158174	Land et al.	Jul 2008	A1
20080158181	Hamblin et al.	Jul 2008	A1
20080158182	Westerman	Jul 2008	A1
20080158185	Westerman	Jul 2008	A1
20080162996	Krah et al.	Jul 2008	A1
20080188267	Sagong	Aug 2008	A1
20080224962	Kasai et al.	Sep 2008	A1
20080238871	Tam	Oct 2008	A1
20080264699	Chang et al.	Oct 2008	A1
20080277259	Chang	Nov 2008	A1
20080283175	Hagood et al.	Nov 2008	A1
20080303022	Tai et al.	Dec 2008	A1
20080303964	Lee et al.	Dec 2008	A1
20080309626	Westerman et al.	Dec 2008	A1
20080309627	Hotelling et al.	Dec 2008	A1
20080309629	Westerman et al.	Dec 2008	A1
20080309632	Westerman et al.	Dec 2008	A1
20080309633	Hotelling et al.	Dec 2008	A1
20080309635	Matsuo	Dec 2008	A1
20090002337	Chang	Jan 2009	A1
20090019344	Yoon et al.	Jan 2009	A1
20090020343	Rothkopf et al.	Jan 2009	A1
20090070681	Dawes	Mar 2009	A1
20090073138	Lee et al.	Mar 2009	A1
20090085894	Gandhi et al.	Apr 2009	A1
20090091551	Hotelling et al.	Apr 2009	A1
20090114456	Wisniewski	May 2009	A1
20090128516	Rimon et al.	May 2009	A1
20090135157	Harley	May 2009	A1
20090160787	Westerman et al.	Jun 2009	A1
20090174676	Westerman	Jul 2009	A1
20090174688	Westerman	Jul 2009	A1
20090182189	Lira	Jul 2009	A1
20090184937	Grivna	Jul 2009	A1
20090194344	Harley et al.	Aug 2009	A1
20090205879	Halsey, IV et al.	Aug 2009	A1
20090213090	Mamba et al.	Aug 2009	A1
20090236151	Yeh et al.	Sep 2009	A1
20090242283	Chiu	Oct 2009	A1
20090251427	Hung et al.	Oct 2009	A1
20090267902	Nambu et al.	Oct 2009	A1
20090267903	Cady et al.	Oct 2009	A1
20090273577	Chen et al.	Nov 2009	A1
20090303189	Grunthaner et al.	Dec 2009	A1
20090309850	Yang	Dec 2009	A1
20090315854	Matsuo	Dec 2009	A1
20090322702	Chien et al.	Dec 2009	A1
20100001973	Hotelling et al.	Jan 2010	A1
20100006350	Elias	Jan 2010	A1
20100007616	Jang	Jan 2010	A1
20100039396	Ho et al.	Feb 2010	A1
20100059294	Elias et al.	Mar 2010	A1
20100060608	Yousefpor	Mar 2010	A1
20100079384	Grivna	Apr 2010	A1
20100079401	Staton	Apr 2010	A1
20100102027	Liu et al.	Apr 2010	A1
20100110035	Selker	May 2010	A1
20100117985	Wadia	May 2010	A1
20100143848	Jain et al.	Jun 2010	A1
20100156810	Barbier et al.	Jun 2010	A1
20100156846	Long et al.	Jun 2010	A1
20100182278	Li et al.	Jul 2010	A1
20100194697	Hotelling et al.	Aug 2010	A1
20100194707	Hotelling et al.	Aug 2010	A1
20100245286	Parker	Sep 2010	A1
20100253638	Yousefpor et al.	Oct 2010	A1
20100328248	Mozdzyn	Dec 2010	A1
20100328263	Lin	Dec 2010	A1
20110007020	Hong	Jan 2011	A1
20110025623	Lin	Feb 2011	A1
20110025629	Grivna et al.	Feb 2011	A1
20110025635	Lee	Feb 2011	A1
20110096016	Yilmaz	Apr 2011	A1
20110134050	Harley	Jun 2011	A1
20110157068	Parker	Jun 2011	A1
20110199105	Otagaki et al.	Aug 2011	A1
20110227874	Faahraeus et al.	Sep 2011	A1
20110231139	Yokota	Sep 2011	A1
20110241907	Cordeiro	Oct 2011	A1
20110248949	Chang et al.	Oct 2011	A1
20110254795	Chen	Oct 2011	A1
20110261005	Joharapurkar et al.	Oct 2011	A1
20110261007	Joharapurkar et al.	Oct 2011	A1
20110282606	Ahed et al.	Nov 2011	A1
20110298727	Yousefpor et al.	Dec 2011	A1
20110310033	Liu et al.	Dec 2011	A1
20110310064	Keski-Jaskari et al.	Dec 2011	A1
20120026099	Harley	Feb 2012	A1
20120044199	Karpin et al.	Feb 2012	A1
20120050206	Welland	Mar 2012	A1
20120050214	Kremin	Mar 2012	A1
20120050216	Kremin et al.	Mar 2012	A1
20120054379	Leung	Mar 2012	A1
20120056662	Wilson et al.	Mar 2012	A1
20120056851	Chen et al.	Mar 2012	A1
20120075239	Azumi et al.	Mar 2012	A1
20120092288	Wadia	Apr 2012	A1
20120098776	Chen et al.	Apr 2012	A1
20120113047	Hanauer et al.	May 2012	A1
20120146726	Huang	Jun 2012	A1
20120146942	Kamoshida et al.	Jun 2012	A1
20120154324	Wright et al.	Jun 2012	A1
20120162133	Chen et al.	Jun 2012	A1
20120162134	Chen et al.	Jun 2012	A1
20120169652	Chang	Jul 2012	A1
20120169653	Chang	Jul 2012	A1
20120169655	Chang	Jul 2012	A1
20120169656	Chang	Jul 2012	A1
20120169664	Milne	Jul 2012	A1
20120182251	Krah	Jul 2012	A1
20120211264	Milne	Aug 2012	A1
20120262395	Chan	Oct 2012	A1
20120313881	Ge et al.	Dec 2012	A1
20120320385	Mu	Dec 2012	A1
20130015868	Peng	Jan 2013	A1
20130021291	Kremin et al.	Jan 2013	A1
20130027118	Ho et al.	Jan 2013	A1
20130027346	Yarosh et al.	Jan 2013	A1
20130038573	Chang	Feb 2013	A1
20130057511	Shepelev et al.	Mar 2013	A1
20130069911	You	Mar 2013	A1
20130076648	Krah et al.	Mar 2013	A1
20130100071	Wright	Apr 2013	A1
20130120303	Hong et al.	May 2013	A1
20130127739	Guard et al.	May 2013	A1
20130141383	Woolley	Jun 2013	A1
20130154996	Trend et al.	Jun 2013	A1
20130173211	Hoch et al.	Jul 2013	A1
20130176271	Sobel et al.	Jul 2013	A1
20130176273	Li et al.	Jul 2013	A1
20130215049	Lee	Aug 2013	A1
20130234964	Kim	Sep 2013	A1
20130257785	Brown et al.	Oct 2013	A1
20130257797	Wu et al.	Oct 2013	A1
20130265276	Obeidat et al.	Oct 2013	A1
20130271427	Benbasat	Oct 2013	A1
20130278447	Kremin	Oct 2013	A1
20130278498	Jung et al.	Oct 2013	A1
20130278525	Lim et al.	Oct 2013	A1
20130278543	Hsu	Oct 2013	A1
20130314342	Kim	Nov 2013	A1
20130320994	Brittain	Dec 2013	A1
20130321289	Dubery et al.	Dec 2013	A1
20130342479	Pyo et al.	Dec 2013	A1
20140002406	Cormier et al.	Jan 2014	A1
20140009438	Liu et al.	Jan 2014	A1
20140022201	Boychuk	Jan 2014	A1
20140043546	Yamazaki et al.	Feb 2014	A1
20140071084	Sugiura	Mar 2014	A1
20140078096	Tan et al.	Mar 2014	A1
20140104225	Davidson et al.	Apr 2014	A1
20140104228	Chen et al.	Apr 2014	A1
20140118270	Moses	May 2014	A1
20140125628	Yoshida et al.	May 2014	A1
20140132560	Huang et al.	May 2014	A1
20140145997	Tiruvuru	May 2014	A1
20140152615	Chang et al.	Jun 2014	A1
20140160058	Chen et al.	Jun 2014	A1
20140168540	Wang et al.	Jun 2014	A1
20140204058	Huang	Jul 2014	A1
20140240291	Nam	Aug 2014	A1
20140247245	Lee	Sep 2014	A1
20140253470	Havilio	Sep 2014	A1
20140267070	Shahparnia et al.	Sep 2014	A1
20140267146	Chang et al.	Sep 2014	A1
20140285469	Wright et al.	Sep 2014	A1
20140306924	Lin	Oct 2014	A1
20140347574	Tung et al.	Nov 2014	A1
20140362034	Mo et al.	Dec 2014	A1
20140368436	Abzarian et al.	Dec 2014	A1
20140368460	Mo et al.	Dec 2014	A1
20140375598	Shen et al.	Dec 2014	A1
20140375603	Hotelling et al.	Dec 2014	A1
20140375903	Westhues et al.	Dec 2014	A1
20150002176	Kwon et al.	Jan 2015	A1
20150002448	Brunet et al.	Jan 2015	A1
20150002464	Nishioka et al.	Jan 2015	A1
20150009421	Choi	Jan 2015	A1
20150015528	Vandermeijden	Jan 2015	A1
20150026398	Kim	Jan 2015	A1
20150042600	Lukanc et al.	Feb 2015	A1
20150042607	Takanohashi	Feb 2015	A1
20150049043	Yousefpor	Feb 2015	A1
20150049044	Yousefpor	Feb 2015	A1
20150077375	Hotelling et al.	Mar 2015	A1
20150091587	Shepelev et al.	Apr 2015	A1
20150091849	Ludden	Apr 2015	A1
20150103047	Hanauer et al.	Apr 2015	A1
20150116263	Kim	Apr 2015	A1
20150123939	Kim et al.	May 2015	A1
20150227240	Hong et al.	Aug 2015	A1
20150242028	Roberts et al.	Aug 2015	A1
20150248177	Maharyta	Sep 2015	A1
20150253907	Elias	Sep 2015	A1
20150268789	Liao	Sep 2015	A1
20150268795	Kurasawa et al.	Sep 2015	A1
20150309610	Rabii et al.	Oct 2015	A1
20150338937	Shepelev et al.	Nov 2015	A1
20150370387	Yamaguchi et al.	Dec 2015	A1
20150378465	Shih et al.	Dec 2015	A1
20160018348	Yau et al.	Jan 2016	A1
20160041629	Rao	Feb 2016	A1
20160048234	Chandran	Feb 2016	A1
20160062533	O'Connor	Mar 2016	A1
20160077667	Chiang	Mar 2016	A1
20160139728	Jeon et al.	May 2016	A1
20160154505	Chang et al.	Jun 2016	A1
20160154529	Westerman	Jun 2016	A1
20160224177	Krah	Aug 2016	A1
20160224189	Yousefpor et al.	Aug 2016	A1
20160246423	Fu	Aug 2016	A1
20160253041	Park	Sep 2016	A1
20160259448	Guarneri	Sep 2016	A1
20160266676	Wang et al.	Sep 2016	A1
20160282980	Chintalapoodi	Sep 2016	A1
20160283023	Shin et al.	Sep 2016	A1
20160299603	Tsujioka et al.	Oct 2016	A1
20160357344	Benbasat et al.	Dec 2016	A1
20170090619	Yousefpor	Mar 2017	A1
20170097703	Lee	Apr 2017	A1
20170139539	Yao et al.	May 2017	A1
20170168626	Konicek	Jun 2017	A1
20170229502	Liu	Aug 2017	A1
20170269729	Chintalapoodi	Sep 2017	A1
20170285804	Yingxuan et al.	Oct 2017	A1
20170357371	Kim	Dec 2017	A1
20180067584	Zhu et al.	Mar 2018	A1
20180275824	Li et al.	Sep 2018	A1
20180307374	Shah et al.	Oct 2018	A1
20180307375	Shah et al.	Oct 2018	A1
20190034032	Westerman	Jan 2019	A1

Foreign Referenced Citations (108)

Number	Date	Country
1246638	Mar 2000	CN
1527274	Sep 2004	CN
1672119	Sep 2005	CN
1689677	Nov 2005	CN
1711520	Dec 2005	CN
1782837	Jun 2006	CN
1818842	Aug 2006	CN
1864124	Nov 2006	CN
1945516	Apr 2007	CN
101046720	Oct 2007	CN
101071354	Nov 2007	CN
101419516	Apr 2009	CN
102023768	Apr 2011	CN
103049148	Apr 2013	CN
103221910	Jul 2013	CN
103294321	Sep 2013	CN
103365506	Oct 2013	CN
103809810	May 2014	CN
104020908	Sep 2014	CN
105474154	Apr 2016	CN
11 2008 001 245	Mar 2010	DE
0 853 230	Jul 1998	EP
1 192 585	Apr 2002	EP
1 192 585	Apr 2002	EP
1 573 706	Feb 2004	EP
1 573 706	Feb 2004	EP
1 455 264	Sep 2004	EP
1 455 264	Sep 2004	EP
1 644 918	Dec 2004	EP
1 717 677	Nov 2006	EP
1 717 677	Nov 2006	EP
1 986 084	Oct 2008	EP
2 077 489	Jul 2009	EP
2 256 606	Dec 2010	EP
1 546 317	May 1979	GB
2 144 146	Feb 1985	GB
2 428 306	Jan 2007	GB
2 437 827	Nov 2007	GB
2 450 207	Dec 2008	GB
2000-163031	Jun 2000	JP
2002-342033	Nov 2002	JP
2004-503835	Feb 2004	JP
2005-084128	Mar 2005	JP
2005-301373	Oct 2005	JP
2007-018515	Jan 2007	JP
2008-510251	Apr 2008	JP
2008-225415	Sep 2008	JP
10-20040091728	Oct 2004	KR
10-20070002327	Jan 2007	KR
10-2008-0019125	Mar 2008	KR
10-2013-0094495	Aug 2013	KR
10-2013-0117499	Oct 2013	KR
10-2014-0074454	Jun 2014	KR
10-1609992	Apr 2016	KR
200715015	Apr 2007	TW
200826032	Jun 2008	TW
2008-35294	Aug 2008	TW
M341273	Sep 2008	TW
M344522	Nov 2008	TW
M344544	Nov 2008	TW
201115442-1	May 2011	TW
201401129	Jan 2014	TW
201419071	May 2014	TW
WO-9935633	Jul 1999	WO
WO-9935633	Jul 1999	WO
WO-01097204	Dec 2001	WO
WO-2005114369	Dec 2005	WO
WO-2005114369	Dec 2005	WO
WO-2006020305	Feb 2006	WO
WO-2006020305	Feb 2006	WO
WO-2006023147	Mar 2006	WO
WO-2006023147	Mar 2006	WO
WO-2006104745	Oct 2006	WO
WO-2006104745	Oct 2006	WO
WO-2006130584	Dec 2006	WO
WO-2006130584	Dec 2006	WO
WO-2007012899	Feb 2007	WO
WO-2007034591	Mar 2007	WO
WO-2007066488	Jun 2007	WO
WO-2007089766	Aug 2007	WO
WO-2007089766	Aug 2007	WO
WO-2007115032	Oct 2007	WO
WO-2007146785	Dec 2007	WO
WO-2007146785	Dec 2007	WO
WO-2008007118	Jan 2008	WO
WO-2008007118	Jan 2008	WO
WO-2008047990	Apr 2008	WO
WO-2008076237	Jun 2008	WO
WO-2008108514	Sep 2008	WO
WO-2008135713	Nov 2008	WO
WO-2009046363	Apr 2009	WO
WO-2009103946	Aug 2009	WO
WO-2009132146	Oct 2009	WO
WO-2009132150	Oct 2009	WO
WO-2010088659	Aug 2010	WO
WO-2010117882	Oct 2010	WO
WO-2011137200	Nov 2011	WO
WO-2013158570	Oct 2013	WO
WO-201412771	Aug 2014	WO
WO-2015017196	Feb 2015	WO
WO-2015023410	Feb 2015	WO
WO-2015072722	May 2015	WO
WO-2015107969	Jul 2015	WO
WO-2015178920	Nov 2015	WO
WO-2016048269	Mar 2016	WO
WO-2016069642	May 2016	WO
WO-2016126525	Aug 2016	WO
WO-2017058415	Apr 2017	WO

Non-Patent Literature Citations (139)

Entry
Lee, S.K. et al. (Apr. 1985). “A Multi-Touch Three Dimensional Touch-Sensitive Tablet,” Proceedings of CHI: ACM Conference on Human Factors in Computing Systems, pp. 21-25.
Rubine, D.H. (Dec. 1991). “The Automatic Recognition of Gestures,” CMU-CS-91-202, Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Computer Science at Carnegie Mellon University, 285 pages.
Rubine, D.H. (May 1992). “Combining Gestures and Direct Manipulation,” CHI ' 92, pp. 659-660.
Westerman, W. (Spring 1999). “Hand Tracking, Finger Identification, and Chordic Manipulation on a Multi-Touch Surface,” A Dissertation Submitted to the Faculty of the University of Delaware in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical Engineering, 364 pages.
Final Office Action dated Apr. 8, 2016, for U.S. Appl. No. 13/899,391, filed May 21, 2013, ten pages.
Final Office Action dated May 9, 2016, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, ten pages.
Final Office Action dated May 27, 2016, for U.S. Appl. No. 14/645,120, filed Mar. 11, 2015, twelve pages.
Final Office Action dated Jun. 14, 2016, for U.S. Appl. No. 14/550,686, filed Nov. 21, 2014, ten pages.
International Search Report dated May 9, 2016, for PCT Application No. PCT/US2016/015479, filed Jan. 28, 2016, five pages.
International Search Report dated May 11, 2016, for PCT Application No. PCT/US2016/016011, filed Feb. 1, 2016, six pages.
Non-Final Office Action dated Apr. 14, 2016, for U.S. Appl. No. 14/558,529, filed Dec. 2, 2014, 20 pages.
Non-Final Office Action dated May 25, 2016, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, 23 pages.
Non-Final Office Action dated Jun. 1, 2016, for U.S. Appl. No. 14/615,186, filed Feb. 5, 2015, eight pages.
TW Search Report dated May 3, 2016, for TW Application No. 104115152, one page.
Final Office Action dated Sep. 29, 2016, for U.S. Appl. No. 14/558,529, filed Dec. 2, 2014, 22 pages.
Final Office Action dated Nov. 4, 2016, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, 18 pages.
Non-Final Office Action dated Dec. 14, 2016, for U.S. Appl. No. 14/550,686, filed Nov. 21, 2014, eight pages.
Notice of Allowance dated Dec. 2, 2016, for U.S. Appl. No. 14/615,186, filed Feb. 5, 2015, seven pages.
Non-Final Office Action dated Dec. 16, 2016, for U.S. Appl. No. 14/645,120, filed Mar. 11, 2015, ten pages.
Non-Final Office Action dated Dec. 19, 2016, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, eleven pages.
Non-Final Office Action dated Mar. 13, 2017, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, 20 pages.
Non-Final Office Action dated Apr. 7, 2017, for U.S. Appl. No. 15/144,706, filed May 2, 2016, eight pages.
European Search Report dated Jul. 27, 2017, for EP Application No. 14902458.0, four pages.
Final Office Action dated Jul. 26, 2017, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, 10 pages.
Final Office Action dated Aug. 10, 2017, for U.S. Appl. No. 14/645,120, filed Mar. 11, 2015, twelve pages.
Final Office Action dated Aug. 21, 2017, for U.S. Appl. No. 14/550,686, filed Nov. 21, 2014, 11 pages.
Non-Final Office Action dated Jun. 14, 2017, for U.S. Appl. No. 15/006,987, filed Jan. 26, 2016, 14 pages.
Non-Final Office Action dated Jun. 26, 2017, for U.S. Appl. No. 14/558,529, filed Dec. 2, 2014, six pages.
Non-Final Office Action dated Sep. 14, 2017 , for U.S. Appl. No. 15/017,463, filed Feb. 5, 2016, 22 pages.
Notice of Allowance dated Sep. 20, 2017, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, eight pages.
Notice of Allowance dated Sep. 20, 2017, for U.S. Appl. No. 15/144,706, filed May 2, 2016, nine pages.
Notice of Allowance dated Oct. 3, 2017, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, nine pages.
Notice of Allowance dated Oct. 13, 2017, for U.S. Appl. No. 14/558,529, filed Dec. 2, 2014, eight pages.
European Search Report dated Jan. 31, 2018, for EP Application No. 17183937.6, four pages.
Final Office Action dated Dec. 5, 2017, for U.S. Appl. No. 15/006,987, filed Jan. 26, 2016, 16 pages.
Final Office Action dated May 14, 2018, for U.S. Appl. No. 15/006,987, filed Jan. 26, 2016, 11 pages.
Final Office Action dated May 17, 2018, for U.S. Appl. No. 15/017,463, filed Feb. 5, 2016, 22 pages.
Non-Final Office Action dated Jan. 22, 2018 , for U.S. Appl. No. 15/097,179, filed Apr. 12, 2016, 11 pages.
Non-Final Office Action dated Apr. 3, 2018, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, twelve pages.
Notice of Allowance dated Feb. 9, 2018, for U.S. Appl. No. 14/550,686, filed Nov. 21, 2014, eleven pages.
Notice of Allowance dated Mar. 1, 2018, for U.S. Appl. No. 14/645,120, filed Mar. 11, 2015, five pages.
Non-Final Office Action dated Jun. 20, 2018, for U.S. Appl. No. 15/009,774, filed Jan. 28, 2016, seventeen pages.
Final Office Action mailed Jul. 27, 2018, for US Patent Application No. 15/097,179, filed Apr. 12, 2016, 11 pp.
Cassidy, R. (Feb. 23, 2007). “The Tissot T-Touch Watch—A Groundbreaking Timepiece,” located at <http://ezinearticles.com/?The-Tissot-T-Touch-Watch---A-Groundbreaking-Timepiece&id . . . >, last visited Jan. 23, 2009, two pages.
Chinese Search Report completed Dec. 14, 2011, for CN Patent Application No. ZL201020108330X, filed Feb. 2, 2010, with English Translation, 22 pages.
Chinese Search Report completed May 18, 2015, for CNPatent Application No. 201310042816.6, filed Feb. 2, 2010, two pages.
European Search Report dated Jul. 21, 2010, for EP Patent Application 10151969.2, six pages.
European Search Report dated Apr. 25, 2012, for EP Patent Application No. 08022505.5, 12 pages.
European Search Report dated Dec. 3, 2012, for EP Patent Application No. 12162177.5, seven pages.
European Search Report dated Feb. 13, 2013, for EP Patent Application No. 12192450.0, six pages.
European Search Report dated Aug. 31, 2015, for EP Application No. 15166813.4, eight pages.
Final Office Action dated Jan. 5, 2012, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 15 pages.
Final Office Action dated Jan. 3, 2013, for U.S. Appl. No. 11/818,498, filed Jun. 13, 2007, 17 pages.
Final Office Action dated Feb. 1, 2013, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, nine pages.
Final Office Action dated Feb. 5, 2013, for U.S. Appl. No. 12/500,911, filed Jul. 10, 2009, 15 pages.
Final Office Action dated Apr. 30, 2013, for U.S. Appl. No. 12/494,173, filed Jun. 29, 2009, 7 pages.
Final Office Action dated May 22, 2013, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 16 pages.
Final Office Action dated Jun. 21, 2013, for U.S. Appl. No. 12/545,754, filed Aug. 21, 2009, 6 pages.
Final Office Action dated Jul. 19, 2013, for U.S. Appl. No. 12,545/604, filed Aug. 21, 2009, 17 pages.
Final Office Action dated Aug. 12, 2013, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, 19 pages.
Final Office Action dated Aug. 13, 2013, for U.S. Appl. No. 12/238,342, filed Sep. 25, 2008, 14 pages.
Final Office Action dated Jan. 27, 2014, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 20 pages.
Final Office Action dated Apr. 23, 2014 for U.S. Appl. No. 12/847,987, filed Jul. 30, 2010, 16 pages.
Final Office Action dated May 9, 2014, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, 13 pages.
Final Office Action dated Jul. 16, 2014, for U.S. Appl. No. 12/545,604, filed Aug. 21, 2009, 18 pages.
Final Office Action dated Oct. 22, 2014, for U.S. Appl. No. 12/238,342, filed Sep. 25, 2008, 16 pages.
Final Office Action dated Oct. 22, 2014, for U.S. Appl. No. 13/448,182, filed Apr. 16, 2012, 11 pages.
Final Office Action dated Apr. 22, 2015, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, 23 pages.
Final Office Action dated Jun. 11, 2015, for U.S. Appl. No. 13/448,182, filed Apr. 16, 2012, 12 pages.
Final Office Action dated Nov. 12, 2015, for U.S. Appl. No. 14/082,074, filed Nov. 15, 2013, 22 pages.
Final Office Action dated Jan. 4, 2016, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, 25 pages.
Final Office Action dated Jan. 29, 2016, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, nine pages.
International Search Report dated Mar. 10, 2010, for PCT Application No. PCT/US2010/22868, filed Feb. 2, 2010, three pages.
International Search Report dated Jan. 14, 2011, for PCT Application No. PCT/US2010/029698, filed Apr. 1, 2010, 4 pages.
International Search Report dated May 2, 2011, for PCT Application No. PCT/US2010/058988, filed Dec. 3, 2010, five pages.
International Search Report dated Aug. 6, 2013, for PCT Application No. PCT/US2013/036662, filed Apr. 15, 2013, three pages.
International Search Report dated Sep. 24, 2014, for PCT Application No. PCT/US/2014/39245, three pages.
International Search Report dated Dec. 12, 2014, for PCT Application No. PCT/US2014/56795, two pages.
International Search Report dated Jan. 29, 2015, for PCT Application No. PCT/US2014/047888, filed Jul. 23, 2014, six pages.
International Search Report dated Jan. 8, 2016, for PCT Application No. PCT/US2015/057644, filed Oct. 27, 2015, four pages.
Malik, S. et al. (2004). “Visual Touchpad: A Two-Handed Gestural Input Device,” Proceedings of the 6th International Conference on Multimodal Interfaces, State College, PA, Oct. 13-15, 2004, ICMI '04, ACM pp. 289-296.
Non-Final Office Action dated Jun. 9, 2011, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 13 pages.
Non-Final Office Action dated Mar. 9, 2012, for U.S. Appl. No. 12/238,342, filed Sep. 25, 2008, 26 pgs.
Non-Final Office Action dated May 3, 2012, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, 22 pgs.
Non-Final Office Action dated May 25, 2012, for U.S. Appl. No. 11/818,498, filed Jun. 13, 2007, 16 pages.
Non-Final Office Action dated Jun. 7, 2012, for U.S. Appl. No. 12/500,911, filed Jul. 10, 2009, 16 pages.
Non-Final Office Action dated Aug. 28, 2012, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, nine pages.
Non-Final Office Action dated Sep. 26, 2012, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 14 pages.
Non-Final Office Action dated Oct. 5, 2012, for U.S. Appl. No. 12/545,754, filed Aug. 21, 2009, 10 pages.
Non-Final Office Action dated Nov. 23, 2012, for U.S. Appl. No. 12/545,557, filed Aug. 21, 2009, 11 pages.
Non-Final Office Action dated Nov. 28, 2012, for U.S. Appl. No. 12/494,173, filed Jun. 29, 2009, six pages.
Non-Final Office Action dated Jan. 7, 2013, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, 20 pgs.
Non-Final office Action dated Jan. 7, 2013, for U.S. Appl. No. 12/545,604, filed Aug. 21, 2009, 12 pages.
Non-Final Office Action dated Feb. 15, 2013, for U.S. Appl. No. 12/238,342, filed Sep. 25, 2008, 15 pages.
Non-Final Office Action dated Mar. 29, 2013 for U.S. Appl. No. 13/737,779, filed Jan. 9, 2013, nine pages.
Non-Final Office Action dated Sep. 6, 2013, for U.S. Appl. No. 12/847,987, filed Jul. 30, 2010, 15 pages.
Non-Final Office Action dated Sep. 10, 2013, for U.S. Appl. No. 12/545,754, filed Aug. 21, 2009, six pages.
Non-Final Office Action dated Sep. 30, 2013, for U.S. Appl. No. 12/206,680, filed Sep. 8, 2008, 18 pages.
Non-Final Office Action dated Nov. 8, 2013, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, 12 pages.
Non-Final Office Action dated Dec. 19, 2013, for U.S. Appl. No. 12/545,604, filed Aug. 21, 2009, 17 pages.
Non-Final Office Action dated Jan. 2, 2014, for U.S. Appl. No. 12/545,754, filed Aug. 21, 2009, 11 pages.
Non-Final Office Action dated Jan. 3, 2014 , for U.S. Appl. No. 12/545,557, filed Aug. 21, 2009, 9 pages.
Non-Final Office Action dated Jan. 31, 2014, for U.S. Appl. No. 13/448,182, filed Apr. 16, 2012, 18 pages.
Non-Final Office Action dated Mar. 12, 2014, for U.S. Appl. No. 12/238,342, filed Sep. 25, 2008, 15 pages.
Non-Final Office Action dated Apr. 10, 2014, for U.S. Appl. No. 14/055,717, filed Oct. 16, 2013, 10 pages.
Non-Final Office Action dated Sep. 18, 2014, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, 21 pages.
Non-Final Office Action dated Apr. 10, 2015, for U.S. Appl. No. 14/082,074, filed Nov. 15, 2013, 23 pages.
Non-Final Office Action dated May 4, 2015, for U.S. Appl. No. 12/642,466, filed Dec. 18, 2009, nine pages.
Non-Final Office Action dated May 8, 2015, for U.S. Appl. No. 14/082,003, filed Nov. 15, 2013, 25 pages.
Non-Final Office Action dated Aug. 20, 2015 , for U.S. Appl. No. 14/550,686, filed Nov. 21, 2014, ten pages.
Non-Final Office Action dated Oct. 5, 2015, for U.S. Appl. No. 13/899,391, filed May 21, 2013, ten pages.
Non-Final Office Action dated Oct. 6, 2015, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, seven pages.
Non-Final Office Action dated Oct. 27, 2015, for U.S. Appl. No. 14/645,120, filed Mar. 11, 2015, eight pages.
Notice of Allowance dated Jun. 10, 2013, for U.S. Appl. No. 12/545,557, filed Aug. 21, 2009, 9 pages.
Notice of Allowance dated Aug. 19, 2013, for U.S. Appl. No. 12/500,911, filed Jul. 10, 2009, six pages.
Notice of Allowance dated Sep. 3, 2013, for U.S. Appl. No. 13/737,779, filed Jan. 9, 2013, 10 pages.
Notice of Allowance dated Apr. 11, 2014, for U.S. Appl. No. 12/545,557, filed Aug. 21, 2009, 9 pages.
Notice of Allowance dated Aug. 21, 2014, for U.S. Appl. No. 12/545,754, filed Aug. 21, 2009, 8 pages.
Notice of Allowance dated Oct. 15, 2014, for U.S. Appl. No. 12/494,173, filed Jun. 29, 2009, eight pages.
Notice of Allowance dated Nov. 7, 2014, for U.S. Appl. No. 14/055,717, filed Oct. 16, 2013, six pages.
Notice of Allowance dated Mar. 16, 2015, for U.S. Appl. No. 14/312,489, filed Jun. 23, 2014, 10 pages.
Notice of Allowance dated Dec. 1, 2015, for U.S. Appl. No. 12/238,333, filed Sep. 25, 2008, nine pages.
Notice of Allowance dated Jan. 8, 2016, for U.S. Appl. No. 13/448,182, filed Apr. 16, 2012, nine pages.
Rekimoto, J. (2002). “SmartSkin: An Infrastructure for Freehand Manipulation on Interactive Surfaces,” CHI 2002, Apr. 20-25, 2002. [(Apr. 20, 2002). 4(1):113-1201.
Search Report dated Nov. 12, 2015, for ROC (Taiwan) Patent Application No. 103105965, with English translation, two pages.
Search Report dated Apr. 29, 2009, for NL Application No. 2001672, with English translation of Written Opinion, eight pages.
Search Report dated Oct. 14, 2015, for TW Application No. 103116003, one page.
Wilson, A.D. (Oct. 15, 2006). “Robust Computer Vision-Based Detection of Pinching for One and Two-Handed Gesture Input,” ACM, USIT '06, Montreux, Switzerland, Oct. 15-18, 2006, pp. 255-258.
Yang, J-H. et al. (Jul. 2013). “A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels,” IEEE Transactions on Circuits and Systems -1: Regular Papers 60(7):1800-1809.
First Action Interview Pilot Program Pre-Interview Communication, date Apr. 4, 2019, for U.S. Appl. No. 15/686,969, filed Aug. 25, 2017, three pages.
Notice of Allowance dated Apr. 3, 2019, for U.S. Appl. No. 15/687,078, filed Aug. 25, 2017, eight pages.
Non-Final Office Action dated May 15, 2019 for U.S. Appl. No. 15/017,463, filed Feb. 5, 2016, 19 pages.
Final Office Action dated Feb. 6, 2019, for U.S. Appl. No. 15/009,774, filed Jan. 28, 2016, fifteen pages.
Non-Final Office Action dated Dec. 21, 2018, for U.S. Appl. No. 15/313,549, filed Nov. 22, 2016, thirteen pages.
Non-Final Office Action dated Feb. 11, 2019 , for U.S. Appl. No. 15/507,722, filed Feb. 28, 2017, fifteen pages.
Non-Final Office Action dated Jan. 18, 2019 , for U.S. Appl. No. 15/087,956, filed Mar. 31, 2016, tweleve pages.
Non-Final Office Action dated Jan. 2, 2019, for U.S. Appl. No. 15/522,737, filed Apr. 27, 2017, thirteen pages.
Notice of Allowance dated Dec. 31, 2018, for U.S. Appl. No. 14/318,157, filed Jun. 27, 2014, eight pages.
Notice of Allowance dated Mar. 11, 2019, for U.S. Appl. No. 15/087,956, filed Mar. 31, 2016, ten pages.

Related Publications (1)

	Number	Date	Country
	20160266679 A1	Sep 2016	US

Provisional Applications (1)

	Number	Date	Country
	62131242	Mar 2015	US

Multi-chip touch architecture for scalability

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

Field of Search

CPC

International Classifications

Term Extension

Abstract