Patent Application
20060085573
This invention relates to information handling systems, and more particularly to hardware partitioning of such systems.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
As information handling systems become more complex, issues such as security and resource allocation become paramount. One area of concern is the separation of multiple workloads on a single machine. This problem is addressed with hardware partitioning, which provide distinct execution environments on a single machine.
Hardware partitioning can be of the CPU and/or memory, and optionally through to the I/O system. In today's computer systems, partitioning that extends through the I/O system (“through the edge of the system”) is more difficult to achieve than are CPU and memory partitioning.
One approach to I/O partitioning is to provide separate I/O devices for each hardware partition. However, this results in expensive hardware replication.
In accordance with teachings of the present disclosure, a system and method are described for “to the edge” hardware partitioning. That is, multiple partitions are created for I/O devices.
The information handling system is partitioned into a number of partitions, each partition having a CPU system, a memory system, and an I/O system. The I/O system is connected to the rest of the system by means of a PCI Express bus. Each I/O device has a hardware context, comprising a set of one or more registers for each partition. Partitioning of the I/O system is performed by using the transaction ID portion of a PCI Express packet header to map an I/O device to the context of a desired partition.
By using the transaction ID field of the PCI express packet header for partition selection, hardware partitioning can be accomplished to the edge of the computer system. This is accomplished using existing PCI Express protocol. Actual implementation may involve clarification or re-definition of existing fields, but the basic protocol is unchanged.
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
Preferred embodiments and their advantages are best understood by reference to
For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
For purposes of this description, CPU 101 can comprise a single partitioned processor or multiple processors. For example, a system 100 having multiple server CPU devices, can be partitioned in accordance with the system and method described herein.
As explained in the Background, the partitions provide distinct execution environments within system 100. However, in
In
To create isolation of the partitions of I/O system 201, each I/O device presents a private programming model for each partition from which a host attempts to use that device. “Programming model” means the control registers, etc., that make up the normal programming interface normally seen when using that device. The I/O device is required to manage the application of the correct information presented from each partition and used by the underlying functions.
The register sets that are owned exclusively by a host in a partition are referred to herein as “contexts”. By creating multiple contexts for I/O devices, each context corresponding to a unique operating system instance, I/O partitions can be created.
As stated above, it is assumed that the bus between the northbridge 101a is a PCI (Peripheral Component Interconnect) Express bus 303. Bus 303 is a local I/O bus, which connects various peripheral devices to the memory, chipset, and processor. Video cards, disk storage devices, and network interface cards are examples of peripheral devices that use this bus.
The PCI Express bus 303 is the current generation of the PCI bus family. This bus 303 is a high-bandwidth serial bus, which maintains software compatibility with existing PCI devices. Data is encapsulated into packets and sent as a serial stream on the link to/from an I/O device. The packets contain information such as the destination address, amount of data being sent or being read, CRC, and a command.
Referring in particular to
However, all packet headers 401 contain a transaction ID field 501. The transaction ID field 501 identifies the bus number, device number, and function number. In a requester packet, the transaction ID field 501 comprises bytes 8 and 9 of the packet header 401.
Referring again to
Although the disclosed embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the embodiments without departing from their spirit and scope.
