Patent Application
20160284909
Photovoltaic cells, commonly known as solar cells, are devices for direct conversion of solar radiation into electrical energy. Generally, solar cells are fabricated on a semiconductor wafer or substrate using semiconductor processing techniques to form a p-n junction near a surface of the substrate. Solar radiation impinging on the surface of, and entering into, the substrate creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage differential between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct an electrical current from the cell to an external circuit coupled thereto.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):
“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.
“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, for that unit/component.
“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” sub-cell does not necessarily imply that this sub-cell is the first sub-cell in a sequence; instead the term “first” is used to differentiate this sub-cell from another sub-cell (e.g., a “second” sub-cell).
“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.
“Inhibit”—As used herein, inhibit is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition it may completely prevent the result or outcome or future state completely. Additionally, “inhibit” can also refer to a reduction or lessening of the outcome, performance, and/or effect which might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.
In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “side”, “outboard”, and “inboard” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Solar cells having a plurality of sub-cells coupled by metallization structures, and singulation approaches to forming solar cells having a plurality of sub-cells coupled by metallization structures, are described herein. In the following description, numerous specific details are set forth, such as specific process flow operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques, such as solar cell emitter region fabrication techniques, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
The specification first describes an example multi-diode solar cell structure, followed by specific examples of multi-diode solar cells for concentrating photovoltaic (PV) receivers. The specification also describes an example method for forming the disclosed structures. Various examples are provided throughout.
To give context for a solar cell having a plurality of sub-cells, a single solar cell (e.g., 125 mm, 156 mm, 210 mm) can be subdivided into smaller cells to allow for flexibility in module current and voltage, as well as flexibility in the metallization (e.g., thickness can be reduced with reduced current). As an example, a single silicon P/N diode has an open circuit voltage (Voc) of 0.6 to 0.74 V. A maximum power voltage (Vmp) may be approximately 0.63V for a solar cell. Thus, single diode cells will have a voltage of 0.63V. If 10 sub-diodes are produced on a single full-area wafer, and connected in series, the voltage would be 6.3V for the entire cell (at roughly 1/10th the current, or about 0.5 A for a standard cell).
Having the ability to control the voltage conversely allows control over the current, which ultimately dictates the thickness of the metal required for a finished device, since power loss is associated with resistive losses in the metal. For example, for an interdigitated back contact (IBC) cell on a 5 inch wafer, the nominal finger length is 125 mm long, and requires approximately 30 microns of plated copper (Cu) to prevent grid losses. Moving to a 6 inch wafer extends the finger length to 156 millimeters, and since resistive losses go by the length squared, this may require a metal thickness of approximately 48 microns. The potential adds substantial cost to metallization, e.g., by having more direct material costs and by reducing the throughput of the tools. Thus, the ability to control the finger length and cell parametrics by moving to multiple diode solutions can allow for greater flexibility in the processing of solar cell metallization. In particular, for applications on larger cells, increasing the size of the cell also produces more current. Moreover, for a concentrating PV application, thicker metal is typically used to accommodate the higher current that is produced. By implementing a multi-diode approach for a concentrating PV, a lower current can be achieved thereby allowing thinner metal to be used, which can result in reduced cost and increased throughput.
Additionally, temperature of the devices in operation in the field is dependent on the current and generally should be minimized to avoid accelerated aging affects, and risks of higher temperatures should cells enter reverse bias. Furthermore, in general, lower current will improve the overall reliability of the PV receiver.
As described in greater detail below in association with the Figures, specific embodiments described herein can be implemented based on the understanding that metal or metallization structures having a thickness of greater than approximately 20 microns can be used to prevent power loss otherwise associated with silicon (Si)-cracking in a solar cell by using the metal to hold the cell together. Embodiments described herein provide a metal structure (e.g., by plating, or foil, or ribbon, etc.) that is bonded to a full-area wafer having sub-cells. In the multi-sub-cell approach, the metal can be patterned such that the sub-cell interconnects are formed in the same operation as the sub-cell metallization and are part of the metallization structure of the full solar cell having the multiple sub-cells. And in embodiments in which a half wafer form factor is used, the silicon and metal can be scribed and diced, respectively, to separate the full wafer into two separate half wafers, each with multiple sub-cells.
As an exemplary representation of the scribing concepts described herein,
Referring to
Referring again to
In the example of
Referring again to
In an embodiment, the metallization structure is fabricated from a foil (e.g., a conductive foil, such as an aluminum foil with or without an additional seed layer) or is fabricated by a plating process. The metallization structure may be fabricated by plating, printing, by use of a bonding procedure (e.g., in the case of a foil), or may be fabricated by a by a deposition, lithographic, and etch approach. In one such embodiment, in the case that a relatively thick (e.g., greater that approximately 25 microns) back metal is used, some tolerance for partial laser ablation into the metal may be accommodated. However, if a thin metallization structure is used (e.g., less than approximately 25 microns), ablation may need to be halted without any scribing of the metallization structure, so as to maintain the electrical and physical integrity of the metal required to survive reliability testing. Accordingly, in various embodiments, the disclosed techniques can provide a way to halt the scribing while inhibiting damage to the metallization structure.
In an embodiment, the metallization scheme is used to hold and provide mechanical integrity for the sub-cells together within the parent cell, such that additional handling complexity is not necessarily required when building the module, and the cells remain physically separated.
In one embodiment, the emitter is designed so that the scribe falls primarily or entirely within the N-doped region, which has a lower recombination rate when unpassivated than the unpassivated P-doped region, and therefore results in significantly less power loss. In another embodiment, the emitter and scribe are designed so that there is little or no intersection of the scribe with a P—N junction, since unpassivated junctions have significantly higher recombination resulting in more power loss.
In one embodiment, a buffer stop (e.g., a polymer such as polyimide) can be implemented in addition to the scribing depth control techniques, to provide a backup to inhibit damage to the metallization structure. The polymer can be globally deposited and then patterned or may be deposited only in desired, e.g., by printing. In other embodiments, such a buffer stop is composed of a dielectric material such as, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON). In one such embodiment, the dielectric material can be formed using a deposition technique such as, but not limited to, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD).
It is to be appreciated that one or more embodiments described herein involve implementation of metallization that is single-level ‘monolithic’ across all sub-cells. Thus, the resulting cell metallization can be identical to the interconnect metallization and fabricated in the same process, at the same time. In one such embodiment, use of a monolithic metallization structure leads to implementation of cell isolation as completed subsequent all diodes being metallized. This is distinguished from conventional approaches where metallization is a multi-step process. In more particular embodiments, a monolithic metallization approach is implemented in conjunction with a buffer or protective layer over which the monolithic metallization structure is formed. Such embodiments can allow for ablation stop on the buffer or protective layer without exposing the metal itself.
In some embodiments, an encapsulating material, e.g., ethylene vinyl alcohol (EVA), poly-olefin, can be disposed in the groove between adjacent ones of the singulated and physically separated semiconductor substrate portions. In one such embodiment, the encapsulant provides shunt resistance as well as wear resistance between adjacent sub-cell portions.
In accordance with an embodiment of the present disclosure, each sub-cell of a diced solar cell has approximately a same voltage characteristic and approximately a same current characteristic. In an embodiment, the plurality of sub-cells is a plurality of in-parallel diodes, in-series diodes, or a combination thereof. In an embodiment, the solar cell and, hence, the sub-cell portions, is a back-contact solar cell, and the metallization structure is disposed on the back surface, opposite a light-receiving surface, of each of the singulated and physically separated semiconductor substrate portions. In one such embodiment, the back surface of each of the sub-cells has approximately a same surface area. In a particular embodiment, the light-receiving surface of each of the sub-cells is a texturized surface, as is described in greater detail below.
In accordance with an embodiment of the present disclosure, the semiconductor substrate portions can be bulk monocrystalline silicon substrate portions, such as fabricated from an N-type monocrystalline substrate. In one such embodiment, each silicon portion includes one or more N+ regions (e.g., phosphorous or arsenic doped regions) and one or more P+ regions (e.g., boron doped regions) formed in substrate itself. In other embodiments, each silicon portion includes one or more polycrystalline silicon N+ regions and one or more polycrystalline silicon P+ regions formed above a silicon substrate.
It is to be appreciated that a variety of arrangements of numbers and electrically coupling of sub-cells within a singulated solar cell may be contemplated within the spirit and scope of embodiments described herein. In a first example,
As shown in
In one embodiment, the scribe cut can be performed on diffusion regions with the lowest recombination post isolation.
The receivers illustrated and described through, including the receiver of
As shown in
For each of the illustrated half wafers of
In one embodiment, the scribe cut can be performed on diffusion regions with the lowest recombination post isolation.
The arrows of
As was the case with
Turning now to
As shown, the metallization structures of half wafers 902a and 902b are coupled together with interconnect structures 912, 914, and 916, which can be offset in the z-direction in contrast to on-board interconnects used in other receivers. Although illustrated as three separate interconnect structures, the interconnect structure between half wafers in such an embodiment can be a single unitary interconnect structure (with one or more portions that physically connect to the half wafer), such as a dogbone-type interconnect or an interconnect structure with multiple distinct interconnect pieces. As shown, interconnect structures 910 and 918 can be used to couple the half wafers of receiver 900 to a load. Note that, in the embodiments illustrated and described herein, a concentrating PV receiver can include more than two half wafers. Accordingly, the interior interconnects connecting two half wafers can be repeated until reaching the end half wafer of the receiver at which point an end interconnect, such as interconnects 910 and 918 can be used. Moreover, in various embodiments, depending on the voltage, current, and power configuration based on the number of sub-cells per half wafer, different receiver lengths may be appropriate for different configurations.
As was the case with the receiver of
Referring now to
Moreover, additional benefits of the arrangement of
Some additional advantages of one or more of the receiver configurations described herein can include a lower I2R, more voltage per receiver (and therefore shorter tracker in embodiments in which the concentrating PV receiver is used in a PV tracker system), and fewer cell gaps.
It is to be appreciated that other arrangements for sub-cells may also be achieved using approaches described herein, such as, but not limited to, 1×4, 1×2, 3×3, 4×4, etc., type arrangements. Also, a combination of series and parallel configurations of sub-cells within an original cell is also accessible. Approaches may be beneficial for both back contact and front contact based cells as well as other semiconductor devices.
One limitation of a perpendicular-to-the-flux-beam finger pattern, for example, as shown in
For concentrating PV applications, the use of parallel-to-the-flux-beam finger patterns can result in solder pads being located in light receiving regions of the PV receiver, which can result in efficiency loss. In some embodiments, an additional metal layer can be used to enable longer fingers to be used thereby inhibiting pad loss.
As one specific example of an additional metal layer embodiment, a dielectric region (e.g., polyimide) 1401 can be formed on one polarity (e.g., positive) of fingers 1411 and 1413 of the metallization structure at one end of the cell, as shown in the top representation of
Referring to pathway (a) of
Turning now to
As shown at 1602, a metallization structure can be formed on a first surface of a semiconductor substrate. In an embodiment, forming the metallization structure on the first surface of the semiconductor substrate can include forming and patterning (e.g., in a finger pattern, such as a parallel-to-the-flux-beam pattern, perpendicular-to-the-flux-beam pattern, or otherwise) a metal foil. In other embodiments, however, the metallization structure is formed by printing a metal, plating a metal or stack of metals, or by a metal deposition and etch process. In one embodiment, the metallization structure can be formed to have mechanical properties sufficient to bridge at least two sub-cells together through all reliability testing performed in the fabrication and test procedure.
In one embodiment, the metallization structure that is formed at 1602 can be a metallization structure that bridges together multiple sub-cells of a parent solar cell.
As described herein, in some embodiments, a double metal layer can be implemented. For example, in one embodiment, a parallel-to-the-flux-beam finger pattern can be used for the metallization structure and respective dielectric regions can be formed at the ends of the metallization structure with one dielectric region applied to one polarity of the metallization structure and the other dielectric region applied to the other polarity of the metallization structure. An additional metal layer can then be formed (e.g., printed, plated, foil) on the dielectric regions and on the exposed fingers of the polarity not covered by the dielectric regions to effectively form a pad area for interconnection yet enable finger length to the edge of the cell or closer to it.
At 1604, the substrate can be scribed from a second, opposite resulting in exposed portions of the metallization structure from the second surface. Scribing can result in forming a plurality of sub-cells, each of the sub-cells comprising a singulated and physically separated portion of the substrate having a groove between adjacent ones of the singulated and physically separated substrate portions with the metallization structure coupling ones of the sub-cells.
In an embodiment, the scribing is performed with a scribing instrument, such as a laser, of a tooling apparatus. Furthermore, in an embodiment, with the understanding that certain laser parameters may result in side-wall damage, melting, and disruption of the insulating dielectric stack on the rear side, the laser parameters can be selected so as to minimize such damage, melting, and disruption. Typically, this drives a laser selection to shorter pulse-lengths (e.g., less than approximately 10 nanoseconds), and processes that stop short of disrupting the rear dielectric (e.g., groove followed by mechanical separation).
It is to be appreciated that a mechanical scribing process, such as with a saw, milling machine, or etchant may be implemented instead of or in conjunction with a laser scribing process.
In some embodiments, a partial scribe is performed, followed by breaking or sawing the substrate to complete isolation of portions of the substrate. In one embodiment bending the substrate can be performed during scribing, for example, by placing the substrate on a curved (e.g., concave, convex) chuck or surface for the scribing operation. In another embodiment, bending the substrate can be performed after scribing to complete the isolation of the substrate to the metallization structure. Manual breaking can help mitigate the risk of shunting through the base, e.g., by not totally isolating the Si, or having the isolated Si regions touch each other during cycling. In some embodiments, an encapsulant or dielectric can be applied in the gap to further mitigate the shunt risk.
In an embodiment, the method of cell fabrication further involves texturizing the second surface (light-receiving surface) of the semiconductor substrate prior to scribing the semiconductor substrate. Texturizing of the light-receiving surface of the solar cell can, in one embodiment, involve texturizing using a hydroxide-based etch process. It is to be appreciated that a texturized surface may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off of the light-receiving surface of the solar cell. Accordingly, scribing the substrate at block 1602 can include scribing a textured and non-uniform surface. Note also that other materials (e.g., the metallization structure) may also have variation in thickness.
At 1606, the substrate and the metallization structure can be diced at a particular location to completely separate a first set of sub-cells of the solar cell from a second set of sub-cells. For example, in one embodiment, the location can be along a midpoint of one axis of the solar cell to form two half wafer forms, each with a plurality of sub-cells resulting from the scribing at 1604. In various embodiments, the dicing axis can be perpendicular (e.g., example of
Dicing can be performed in a similar manner as the scribing described at 1604. For example, a laser or mechanical tool can be used to perform the dicing. In one embodiment, dicing at 1606 and scribing at 1604 can be performed with the same tool.
In some embodiments, such as in the example of
One or more benefits or advantages of embodiments described herein include the reduction of the amount of interconnect material for a PV receiver thereby reducing cost of the device, and the reduction of busbar pad loss and/or gap loss from cell-cell spacing, each of which can result in increased efficiency. In addition, because the disclosed structures and techniques can result in lower current, thinner metal can be used, thermal management demands, which can be significant for concentrating PV, can be reduced, and reverse-bias/hot-spot risk can reduced, which can result in another cost savings in the form of bypass diode elimination.
Overall, although certain materials are described specifically above, some materials may be readily substituted with others with other such embodiments remaining within the spirit and scope of embodiments of the present disclosure. For example, in an embodiment, a different material substrate, such as a group III-V material substrate, can be used instead of a silicon substrate. In another embodiment, a polycrystalline or multi-crystalline silicon substrate is used. Furthermore, it is to be understood that, where N+ and P+ type regions are described specifically, other embodiments contemplated include a switched conductivity type, e.g., P+ and N+ type regions, respectively.
Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
