Multi-frame-history pixel drive compensation

Abstract

Image data for a current image frame may be compensated for transient response variations due to changes to pixel values from one frame to another over time by performing pixel drive compensation. The pixel drive compensation may be performed using a current pixel value and a historical pixel value. The historical pixel value may be the same as a pixel value in the directly previous frame in some conditions, while in other conditions the historical pixel value may be modified from a previous image frame in light of a prior pixel value occurring before the previous image frame. In this way, drive compensation corresponding to image data of a subsequent image frame may be determined based at least in part on a multi-frame history. Even so, the memory bandwidth and/or power consumed to use a multi-frame history to determine a drive compensation may be reduced.

Description

BACKGROUND

The present disclosure relates generally to electronic displays and, more particularly, to pixel drive compensation, which may selectively be determined based at least in part on a multi-frame history.

This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Numerous electronic devices—computers, mobile phones, portable media devices, tablets, televisions, virtual-reality headsets, and vehicle dashboards, among many others—often use an electronic display to present visual representations of information such as text, still images, or video. To display an image, an electronic display may control light emission of its display pixels based on corresponding image data. In general, the amount of light emitted by each display pixel depends on an analog electrical signal based on the image data that is programmed into the pixel each frame. In some cases, however, transitioning between different target luminance levels may could cause visible artifacts, such as edge-ghosting (e.g., edge shadow), spatial stretching and/or compression, color fringing, color shift, and/or the like to appear on the display panel.

SUMMARY

A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.

The present disclosure generally relates to applying pixel drive compensation that is selectively determined based at least in part on a multi-frame history to image data. More specifically, the present disclosure relates to techniques for selectively modifying image data and/or selectively using modified image to provide a multi-frame history such that the pixel drive compensation may be determined. In particular, to facilitate improving perceived image quality, an electronic device may include a display pipeline (e.g., image data processing circuitry) that processes image data before an electronic display uses the image data to display a corresponding image (e.g., image frame). Moreover, to reduce transient response variations, which may produce perceivable visual artifacts in the pixels of a display, the display pipeline may be implemented to process image data corresponding to a current image based at least in part on image data corresponding to one or more previous images (e.g., image frames) displayed prior to the current image. To that end, the display pipeline may be implemented to determine drive compensation for the image data corresponding to the current image based at least in part on a multi-frame history.

Accordingly, in some embodiments, the display pipeline may be implemented to store and/or retrieve image data related to the previous images in memory (e.g., system memory). Further, the display pipeline may be implemented to retrieve the stored image data from the memory to provide drive compensation for current image data based at least in part on the stored image data. However, the total memory bandwidth, which may refer to the rate at which data stored in memory may be fetched (e.g., read) or stored (e.g., written) by a system using a memory bus per direct memory access (DMA) cycle, may be fixed for accessing (e.g., fetching from and/or storing to) memory. Moreover, portions of the memory bandwidth may be used to access memory to store and/or retrieve additional data, such as burn-in statistics, configuration data, and/or the like. As such, storing and/or retrieving respective data for each of multiple previous images may reduce the memory bandwidth available for other operations, which may reduce the operational efficiency of the electronic display.

Thus, in some embodiments, image data for a current image frame may be modified (e.g., processed) before storage based at least in part on image data for an image frame directly previous to the current image frame (e.g., a previous image frame) to effectively produce a multi-frame history. For example, in some embodiments, the multi-frame history may be produced based at least in part on an interpolation of a lookup table value, image data for the current image frame, and/or image data for the previous image frame. Moreover, the drive compensation of a subsequent image frame (e.g., an image frame directly following the current image frame) may be determined based at least in part on the multi-frame history. Accordingly, the memory bandwidth and/or power consumed to use a multi-frame history to determine a drive compensation may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a block diagram of an electronic device, in accordance with an embodiment;

FIG. 2 is an example of the electronic device of FIG. 1, in accordance with an embodiment;

FIG. 3 is another example of the electronic device of FIG. 1, in accordance with an embodiment;

FIG. 4 is another example of the electronic device of FIG. 1, in accordance with an embodiment;

FIG. 5 is another example of the electronic device of FIG. 1, in accordance with an embodiment;

FIG. 6 is a block diagram of a portion of the electronic device of FIG. 1 including a display pipeline with pixel drive compensation circuitry, in accordance with an embodiment;

FIG. 7 is an example of the pixel drive compensation circuitry of FIG. 6, in accordance with an embodiment; and

FIG. 8 is a flow diagram of a process for providing drive compensation to a current input pixel value based at least in part on a multi-frame history, in accordance with an embodiment.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

As mentioned above, numerous electronic devices—computers, mobile phones, portable media devices, tablets, televisions, virtual-reality headsets, and vehicle dashboards, among many others—often use an electronic display to present visual representations of information such as text, still images, or video. To display an image, an electronic display may control light emission of its display pixels based on corresponding image data. In general, the amount of light emitted by each display pixel depends on an analog electrical signal based on the image data that is programmed into the pixel each frame. To that end, when image data indicates a first non-zero target luminance (e.g., gray level), a first analog electrical signal may be supplied to the display pixel, and when the image data indicates a second non-zero target higher (e.g., brighter) than the first non-zero target, a second analog electrical signal with a greater magnitude than the magnitude of the first analog electrical signal may be supplied to the display pixel. Moreover, to achieve zero target luminance (e.g., black), the display pixel may be maintained in an off state and/or a block state.

Further, the display pixel may include a storage element (e.g., a capacitor). Thus, the magnitude of current flowing through the display pixel and, subsequently, the luminance of the display pixel, may also depend at least in part on an electrical energy stored in the storage element. Moreover, changes in electrical energy stored in the storage element of the display pixel may occur non-instantaneously. Accordingly, the resulting magnitude of electrical energy stored in the storage element responsive to an analog electrical signal may being supplied to the display pixel for a fixed duration may depend at least in part on the magnitude of electrical energy stored in the storage element before the analog electrical signal was supplied. Thus, the display pixel response to an analog electrical signal may vary based at least in part on the magnitude of the analog electrical signal and the magnitude of the electrical energy previously stored in the storage element, which may depend on previous analog electrical signals supplied to the display pixel. As such, the transition of the display pixel between different target luminance levels may vary, which may result in the transient response variations (e.g., transient response deficiencies). This could cause visible artifacts, such as edge-ghosting (e.g., edge shadow), spatial stretching and/or compression, color fringing, color shift, and/or the like to appear on the display panel.

With the foregoing in mind, an electronic device 10, which may utilize an electronic display 12 to display images with reduced or eliminated artifacts due to transient response variations, is shown in FIG. 1. As will be described in more detail below, the electronic device 10 may be any suitable computing device, such as a handheld computing device, a tablet computing device, a notebook computer, and/or the like. Thus, it should be noted that FIG. 1 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in the electronic device 10.

In the depicted embodiment, the electronic device 10 includes the electronic display 12, one or more input devices 14, one or more input/output (I/O) ports 16, a processor core complex 18 having one or more processor(s) or processor cores, memory 20 that may be local to the electronic device 10, a main memory storage device 22, a network interface 24, a power source 26, and image processing circuitry 27. The various components described in FIG. 1 may include hardware elements (e.g., circuitry), software elements (e.g., a tangible, non-transitory computer-readable medium storing instructions), or a combination of both hardware and software elements. It should be noted that the various depicted components may be combined into fewer components or separated into additional components. For example, the memory 20 and the main memory storage device 22 may be included in a single component. Additionally, the image processing circuitry 27 (e.g., a graphics processing unit (GPU)) may be included in the processor core complex 18.

As depicted, the processor core complex 18 is operably coupled with memory 20 and the main memory storage device 22. In some embodiments, the memory 20 and/or the main memory storage device 22 may be tangible, non-transitory, computer-readable media that stores instructions executable by the processor core complex 18 and/or data to be processed by the processor core complex 18. For example, the memory 20 may include random access memory (RAM) and the main memory storage device 22 may include read only memory (ROM), rewritable non-volatile memory such as flash memory, hard drives, optical discs, and/or the like.

In some embodiments, the processor core complex 18 may execute instructions stored in memory 20 and/or the main memory storage device 22 to perform operations, such as allocating total memory bandwidth to the image processing circuitry 27 and/or determining a multi-frame history. As such, the processor core complex 18 may include one or more general purpose microprocessors, one or more application specific processors (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof.

Additionally, as depicted, the processor core complex 18 is operably coupled with the network interface 24. Using the network interface 24, the electronic device 10 may communicatively couple to a communication network and/or other electronic devices. For example, the network interface 24 may connect the electronic device 10 to a personal area network (PAN), such as a Bluetooth network, a local area network (LAN), such as an 802.11x Wi-Fi network, and/or a wide area network (WAN), such as a 4G or LTE cellular network. In this manner, the network interface 24 may enable the electronic device 10 to transmit image data to a network and/or receive image data from the network for display on the electronic display 12.

Furthermore, as depicted, the processor core complex 18 is operably coupled with I/O ports 16, which may enable the electronic device 10 to interface with various other electronic devices. For example, a portable storage device may be connected to an I/O port 16, thereby enabling the processor core complex 18 to communicate data with a portable storage device. In this manner, the I/O ports 16 may enable the electronic device 10 to output image data to the portable storage device and/or receive image data from the portable storage device.

As depicted, the processor core complex 18 is also operably coupled to the power source 26, which may provide power to the various components in the electronic device 10. The power source 26 may include any suitable source of energy, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter. Furthermore, as depicted, the processor core complex 18 is operably coupled with input devices 14, which may enable a user to interact with the electronic device 10. In some embodiments, the inputs devices 14 may include buttons, keyboards, mice, trackpads, and the like. Additionally or alternatively, the electronic display 12 may include touch components that enable user inputs to the electronic device 10 by detecting occurrence and/or position of an object touching its screen (e.g., outer surface of the electronic display 12).

The electronic display 12 may use, for example, organic light-emitting diode (OLED) or liquid-crystal display (LCD) technology to present visual representations of information by display images, such as on a graphical user interface (GUI) of an operating system, an application interface, a still image, or video content. As described above, the electronic display 12 may display the images based on image data received from memory 20, an external storage device 22, and/or another electronic device 10, for example, via the network interface 24 and/or the I/O ports 16. The electronic display 12 may display the images once the image data has been fetched from memory 20 and processed by the image processing circuitry 27.

As described above, the electronic device 10 may be any suitable electronic device. To help illustrate, one example of a suitable electronic device 10, specifically a handheld device 10A, is shown in FIG. 2. In some embodiments, the handheld device 10A may be a portable phone, a media player, a personal data organizer, a handheld game platform, and/or the like. For illustrative purposes, the handheld device 10A may be a smart phone, such as any iPhone® model available from Apple Inc.

As depicted, the handheld device 10A includes an enclosure 28 (e.g., housing). In some embodiments, the enclosure 28 may protect interior components from physical damage and/or shield them from electromagnetic interference. Additionally, as depicted, the enclosure 28 surrounds the electronic display 12. In the depicted embodiment, the electronic display 12 is displaying a graphical user interface (GUI) 30 having an array of icons 32. By way of example, when an icon is selected either by an input device 14 or a touch-sensing component of the electronic display 12, an application program may launch.

Furthermore, as depicted, input devices 14 open through the enclosure 28. As described above, the input devices 14 may enable a user to interact with the handheld device 10A. For example, the input devices 14 may enable the user to activate or deactivate the handheld device 10A, navigate a user interface to a home screen, navigate a user interface to a user-configurable application screen, activate a voice-recognition feature, provide volume control, and/or toggle between vibrate and ring modes. As depicted, the I/O ports 16 also open through the enclosure 28. In some embodiments, the I/O ports 16 may include, for example, an audio jack to connect to external devices.

To further illustrate, another example of a suitable electronic device 10, specifically a tablet device 10B, is shown in FIG. 3. For illustrative purposes, the tablet device 10B may be any iPad® model available from Apple Inc. A further example of a suitable electronic device 10, specifically a computer 10C, is shown in FIG. 4. For illustrative purposes, the computer 10C may be any Macbook® or iMac® model available from Apple Inc. Another example of a suitable electronic device 10, specifically a watch 10D, is shown in FIG. 5. For illustrative purposes, the watch 10D may be any Apple Watch® model available from Apple Inc. As depicted, the tablet device 10B, the computer 10C, and the watch 10D each also includes an electronic display 12, input devices 14, I/O ports 16, and an enclosure 28.

As described above, an electronic display 12 may display images based at least in part on image data, for example, retrieved from the local memory 20 and/or the main memory storage device 22. Additionally, as described above, image data may be processed before being used to display a corresponding image on the electronic display 12, for example, to facilitate improving perceived image quality. In some embodiments, image data may be fetched and processed by the display pipeline implemented in the electronic device 10.

To help illustrate, a portion 34 of the electronic device 10 including a display pipeline 36 with one or more image data processing blocks 58 is shown in FIG. 6. As depicted, the portion 34 of the electronic device 10 also includes external memory 38 (e.g., memory storage device 22) and a controller 40. In some embodiments, the controller 40 may control operations of the display pipeline 36, the external memory 38, and/or other portions of the electronic device 10. The various functional blocks shown in FIG. 6 may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium) or a combination of both hardware and software elements. It should be noted that FIG. 6 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10.

To facilitate the controlling operation, the controller 40 may include a controller processor 42 and controller memory 44. In some embodiments, the controller processor 42 may execute instructions stored in the controller memory 44. Thus, in some embodiments, the controller processor 42 may be included in the processor core complex 18, the image processing circuitry 27, a timing controller in the electronic display 12, a separate processing module, or any combination thereof. Additionally, in some embodiments, the controller memory 44 may be included in local memory 20, the main memory storage device 22, external memory 38, internal memory of a display pipeline 36, a separate tangible, non-transitory, computer readable medium, or any combination thereof. Although depicted as a single controller 40, in some embodiments, one or more separate controllers 40 may be implemented to control operation of the electronic device.

For example, the electronic device 10 may include a pipeline controller 40 that controls operation of the display pipeline 36 and a supervisory controller 40 that coordinates operation of the display pipeline 36 with one or other sub-systems, such as a touch sensing sub-system, implemented in the electronic device 10. In some embodiments, the supervisory controller 40 may coordinate access to the external memory 38 by allocating memory access bandwidth (e.g., per DMA cycle) between the various sub-systems. For example, the supervisory controller 40 may allocate the display pipeline 36 a portion of the total memory access bandwidth implemented in the electronic device 10 based at least in part on an image data fetch bandwidth floor, a processing data fetch bandwidth floor, a configuration data fetch bandwidth floor, a statistics data storage bandwidth floor, and/or a combined display pipeline bandwidth floor (e.g., sum of bandwidth floor associated with memory access requester implemented in the display pipeline 36).

As described above, the display pipeline 36 may operate to process image data retrieved (e.g., fetched) from the external memory 38, for example, based at least on other data retrieved from the external memory 38. In some embodiments, the display pipeline 36 may be implemented via circuitry, for example, packaged as a system-on-chip (SoC). Additionally or alternatively, the display pipeline 36 may be included in the processor core complex 18, the image processing circuitry 27, a timing controller (TCON) in the electronic display 12, other one or more processing units, other processing circuitry, or any combination thereof.

To simplify discussion, the functions (e.g., operations) performed by the display pipeline 36 are divided between various blocks including a direct memory access (DMA) circuitry 46 (e.g., circuitry and/or logic), a fetch circuitry 59, an input buffer 61, and one or more image data processing block(s) 58 (e.g., circuitry or modules). In particular, the direct memory access (DMA) circuitry 46 may provide the display pipeline 36 access to the external memory 38. For example, the direct memory access (DMA) circuitry 46 may store (e.g., write) data from the display pipeline 36 into the external memory 38. Additionally or alternatively, the direct memory access (DMA) circuitry 46 may retrieve (e.g., read or fetch) image data from external memory 38, for example, based on a request identifying the image data received from the fetch circuitry 59 for subsequent processing via one or more image data processing block(s) 58.

In some instances, the fetch circuitry 59 may request a portion of the total memory access bandwidth when requesting image data to be input to the display pipeline 36. For example, to ensure enough image data is stored within the input buffer 61 such that the display pipeline 36 may operate efficiently, the fetch circuitry 59 may request more image data to be fetched by the direct memory access (DMA) circuitry 46 and thus, may request a greater portion of the total memory access bandwidth.

In some embodiments, the input buffer 61 may act as a reservoir to temporarily hold image data requested, for example, by the fetch circuitry 59 and retrieved from external memory 38 via the direct memory access (DMA) circuitry 46. Further, by acting as a reservoir, the input buffer 61 may allow for opportunistic allocation of total memory access bandwidth to the fetch circuitry 59. For example, to reduce likelihood of underrun conditions in the display pipeline 36, the fetch circuitry 59 may be allocated a greater portion of the total memory access bandwidth than the minimum bandwidth originally allotted, thereby enabling the fetch circuitry 59 to retrieve a greater amount of image data. In such instances, the input buffer 61, may hold the additional image data until, for example, downstream image data processing block(s) 58 are ready to process the image data. This may ensure that the display pipeline 36 has retrieved enough image data to prevent underruns.

Additionally or alternatively, in some embodiments, an image data processing block 58 request a portion of the total memory access bandwidth. The one or more image data processing block(s) 58 may process image data to facilitate improving perceived image quality when the display panel 56 uses the image data to display a corresponding image. For example, the pixel drive compensation (PDC) circuitry 48 may process image data to compensate for display pixel non-uniformity, such as transient response variations. A transient response variation could arise when a pixel emits a first amount of light during one frame and a different amount of light in a second frame. The PDC circuitry 48 may reduce or eliminate visual artifacts that could arise due to a transient response by adjusting the input pixel data by an amount that causes the pixel in the display panel 56 to properly emit the targeted amount of light in the second frame. Indeed, in at least in some instances, transient response variations may affect electrical energy stored in a display pixel and, thus, actual (e.g., perceived) luminance of the display pixel. In fact, display pixel non-uniformity may result in the actual luminance of the display pixel differing from its target luminance indicated by corresponding image data, which, at least in may be perceivable as a visible artifact, such as edge-ghosting (e.g., edge shadow), spatial stretching and/or compression, color fringing, color shift, and/or the like.

Accordingly, in some embodiments, the PDC circuitry 48 may be implemented to compensate for transient response variations by applying offset values (e.g., voltage, gain values, drive compensation values, and/or the like) to image data corresponding to one or more display pixels. For example, in some embodiments, the PDC circuitry 48 may be implemented to apply drive compensation values to achieve a target luminance (e.g., gray level) indicated by the image data in the corresponding one or more display pixels. In some embodiments, the drive compensation values to be applied to image data may be determined based at least in part on an offset map (e.g., lookup table (LUT)). Moreover, in some embodiments, the drive compensation values to be applied may be determined based at least in part on image data history of the display pixels. For example, to account for the electrical energy previously stored in the display pixel, a drive compensation value may be determined based at least in part on current image data and previous image data, such as the image data supplied to the display pixel immediately prior to the current image data. For instance, the previous image data value may correspond to pixel values of a frame displayed immediately prior to the current frame, and the previous image data may correspond to the same display pixel location in the previous frame as the display pixel location the current image data corresponds to in the current image frame. Further, in some cases, such as after the display pixel is driven to a zero target luminance (e.g., black), the drive compensation value may be determined based at least in part on multiple (e.g., two or more) previous image data values, as described in greater detail below.

As described herein, the image data processing blocks 58 may provide may process the image data to account for the operational behavior of the electronic display 12. It should be appreciated that the image data processing block(s) 58 may include additional process blocks such as a burn-in compensation (BIC) block, a burn-in statistics (BIS) block, ambient adaptive pixel (AAP) block, a dynamic pixel backlight (DPB) block, a white point correction (WPC) block, a sub-pixel layout compensation (SPLC) block, a panel response correction (PRC) block, a dithering block, an image signal processor (ISP) block, a content-dependent frame duration (CDFD) block, an ambient light sensing (ALS) block, or any combination thereof. Future references to image data processing block(s) 58 may include image processing blocks, such as those described and mentioned above, or other processing blocks.

The display pipeline 36 may further include internal memory that may be used as, for example, an output buffer 54. The output buffer 54 may temporarily store image data processed by from the image data processing block(s) 58 prior to another system component (e.g., display panel 56) retrieving the image data, for example, for display of a corresponding image on an electronic display 12. The output buffer 54, by acting as a reservoir for image data, may reduce likelihood of perceivable lag when displaying new image content on the electronic display 12 when requested by the display panel 56.

Turning now to FIG. 7, a schematic block diagram of the PDC circuitry 48 is illustrated. As illustrated, in some embodiments, the PDC circuitry 48 may include drive compensation circuitry 100 (e.g., circuitry and/or logic, software, firmware), as well as pixel modification circuitry 102 (e.g., circuitry and/or logic, software, firmware). As described in greater detail below, the drive compensation circuitry 100 may be implemented to modify image data, such as an input pixel value (e.g., sub-pixel value), driven to the display panel 56 to compensate for characterized transient response deficiencies. Further, in some embodiments, the pixel modification circuitry 102 may be implemented to modify image data before it is stored (e.g., written-back) to memory, such as external memory 38. More specifically, the pixel modification circuitry 102 may modify the image data such that the drive compensation circuitry 100 may use the modified image data as multi-frame history to determine the drive compensation provided by the drive compensation circuitry 100.

In some embodiments, the drive compensation circuitry 100 may include a set of drive compensation lookup tables 108, such as a first set of drive compensation lookup tables 108A and a second set of drive compensation lookup tables 108B. The drive compensation lookup tables 108 may be implemented as two-dimensional (2D) lookup tables. In the example of FIG. 7, the first set of drive compensation lookup tables 108A and the second set of drive compensation lookup tables 108B each include three 17×17 tables, one for each pixel color component of red, green, and blue. However, there may be more or fewer entries and, in some cases, the tables may not be symmetric. Moreover, in other examples, the drive compensation lookup tables 108A and 108B may have more dimensions than two (e.g., 3D or higher dimensions). The drive compensation lookup tables 108 may be populated based at least in part on a calibration of the electronic device 10 and/or a characterization of the influence of certain factors (e.g., a temperature, brightness, age, and/or the like of the display panel 56) on the luminance for a given pixel value (e.g., gray level). For instance, the first set of drive compensation lookup tables 108A may include drive compensation values (e.g., voltage levels, gray values, or fractional gray values) mapped to corresponding input pixel values for a brightness of the display panel 56 below a first threshold and/or within a first range (e.g., a low global panel brightness). Similarly, the second set of drive compensation lookup tables 108B may include drive compensation values mapped to corresponding input pixel values for a brightness of the display panel 56 above a second threshold and/or within a second range (e.g., a high global panel brightness), which may be the same as or different from the first threshold or first range, respectively. Moreover, in some embodiments, the first set of drive compensation lookup tables 108A and the second set of drive compensation lookup tables 108B may include a respective drive compensation lookup table for each component (e.g., color component) of a pixel, such as red (R), green (G), and blue (B). To that end, drive compensation values may be mapped to input pixel values corresponding to each component of the pixel for the different brightness settings (e.g., low global brightness, high global brightness, and/or the like) of the display panel 56. While the drive compensation lookup tables 108 are described herein as being populated based at least in part on a brightness of the display panel 56, the drive compensation lookup tables 108 may additionally or alternatively be populated based on any suitable characteristic of the electronic device 10 and/or the display panel 56. For example, the drive compensation lookup tables 108 may be populated based at least in part on a temperature, age, current, voltage, and/or the like of the electronic device 10 and/or the display panel 56. Thus, embodiments described herein are intended to be illustrative and not limiting.

In operation, the drive compensation lookup tables 108 may output a respective drive compensation value based at least in part on a current input pixel value and a previous input pixel value. As an exemplary embodiment, at a first time (t1), the drive compensation lookup tables 108 may output a respective drive compensation value based at least in part on an input pixel value (P1) and a previous input pixel value (P0), which was supplied to the display panel 56 at a time (t0) immediately prior to the first time. Before continuing, it should be noted that the previous input pixel value represents a historical pixel value that may take different values. In some cases, the previous input pixel value (P0) may represent a historical pixel value that is the pixel value was supplied to the display panel 56 at a time (t0) immediately prior to the first time. In other cases, the previous input pixel value (P0) may represent a historical pixel value that represents a multi-frame history of pixel values (accounted for in a single value) due to changes from at least two historical frames. In one particular example, the previous input pixel value (P0) may represent a historical pixel value that represents a multi-frame history of pixel values when there is a transition from zero (pixel is off) in a first frame to some non-zero value (pixel is on) in a second frame. To account for effects of turning the pixel on in the first frame that may linger beyond the second frame and into a third frame, the previous input pixel value (P0) may represent a historical pixel value that accounts for not just the second frame (when the pixel is on) but also the first frame (when the pixel was off) when determining drive compensation values for the third frame. This will be discussed further below with respect to the pixel modification circuitry 102.

In some embodiments, a lookup table value from a first of the first set of drive compensation lookup tables 108A may be determined for a respective color component in the current pixel image data using an index to the first of the first set of drive compensation lookup tables 108A. Such an index may be determined based at least in part on the current input pixel value (P1) for the respective color component (e.g., a gray level of the current input pixel value (P1)), the previous input pixel value for the respective color component (e.g., a gray level of the previous input pixel value (P0)), or a combination thereof. Because the first set of drive compensation lookup tables 108A may map drive compensation values to a subset of input pixel values and/or vice versa, the lookup table value may then be interpolated with the current pixel input value (P1) and the previous pixel input value (P0). In some embodiments, for example, the lookup table value may be interpolated using Barycentric interpolation, a hybrid Barycentric-bilinear interpolation (e.g., Barycentric interpolation in areas within some distance of a diagonal of the LUT, bilinear interpretation in other areas), bilinear-interpolation, and/or the like.

Moreover, the result of the interpolation may correspond to the portion of a first drive compensation value (D1) output by the first set of drive compensation lookup tables 108A that corresponds to the respective component. The remaining portions of the first drive compensation value (D1), which correspond to the other components of the current input pixel value (P1), may be determined as described above using respective lookup tables (e.g., a second and a third lookup table, respectively) in the first set of drive compensation lookup tables 108A. Further, a second drive compensation value (D2) may be determined as described above with reference to the first drive compensation value (D1) by using the second set of drive compensation lookup tables 108B.

Further, in some embodiments, third drive compensation value (D3) may be determined based at least in part on the first drive compensation value (D1) and the second drive compensation value (D2). For instance, a respective weight (e.g., mixing factor) may be applied, based at least in part on the global brightness (brightness) of the display panel 56, to each of the first drive compensation value (D1) and the second drive compensation value (D2). The weighted first and second drive compensation values may be combined to interpolate the third drive compensation value (D3). Accordingly, as shown in the illustrated embodiment, selection circuitry 109A (e.g., a multiplexer (mux)) may be implemented to select between the first drive compensation value (D1), the second drive compensation value (D2), and the third drive compensation value (D3) based at least in part on a select signal (Select). In some embodiments, the select signal may be provided based at least in part on the current pixel input data (P1), the global panel brightness level, and/or the like. Moreover, the output of the selection circuitry 109A may be driven to the pixel (e.g., to the display panel 56) and/or to the output buffer 54.

As such, the pixel value output to the display panel 56 may be determined based at least in part on a current input pixel value (P1) and a previous pixel value (P0) (e.g., a pixel value displayed directly prior to the current input pixel value). However, in some embodiments, compensating the image data driven to the display panel (e.g., overdriving a pixel, underdriving a pixel, and/or the like) based in part on a single frame history (e.g., the previous input pixel value (P0)) may not be sufficient to compensate for transient response deficiencies in the display panel 56. For instance, transitioning a pixel from a zero gray value (e.g., black) to a non-zero gray value using a single frame history during the pixel drive compensation may result in visible artifacts, such as transient response deficiencies. Accordingly, in some embodiments, the drive compensation values (e.g., first drive compensation value (D1), the second drive compensation value (D2), and the third drive compensation value (D3)) may be determined based at least in part on a multi-frame history. To that end, multiple input pixel values output to the display panel 56 prior to the current input pixel value (P1) may be used to determine the drive compensation values. For example, in some embodiments, two previous frames of image data may be suitable to determine the drive compensation values.

Accordingly, in some embodiments, multiple input pixel values may be read (e.g., retrieved) from memory, such as external memory 38 and/or memory 20, to be used for drive compensation of a current pixel input value. That is, for example, image data corresponding to each of a number of frames displayed before the current pixel input value may be retrieved from memory to provide a multi-frame history useful to the drive compensation of the current input pixel value. However, as discussed above, the total memory bandwidth may be fixed for accessing (e.g., fetching from and/or storing to) memory. Moreover, portions of the memory bandwidth may be used to access memory to store and/or retrieve additional data, such as burn-in statistics, configuration data, and/or the like. As such, storing and/or retrieving respective data for each of multiple previous images may reduce the memory bandwidth available for other operations, which may reduce the operational efficiency of the electronic display. Further, image data corresponding to each of a number of frames may consume additional power in the electronic device 10.

Thus, in some embodiments, the pixel modification circuitry 102 may be used to produce a historical pixel value that effectively provides a multi-frame history, which may subsequently be used by the drive compensation circuitry 100 to determine the drive compensation values. To achieve the multi-frame history, the pixel modification circuitry 102 may be implemented to modify the current input pixel value (P1) (e.g., the value of the current input pixel value (P1) before drive compensation) based at least in part on the previous input pixel value (P0) (e.g., the value of the previous input pixel value (P0) before drive compensation). Thus, as described in greater detail below, the value produced by the pixel modification circuitry 102 may capture the multi-frame history of P1 and P0 (and/or pixel values prior to P0) such that at a second time (t2) directly after the first time (t1), the multi-frame history (H) may be used in the drive compensation of a new current input pixel value (P2).

As illustrated, in some embodiments, the pixel modification circuitry 102 may modify the current input pixel value (P1) using a set of pixel modification lookup tables (LUTs) 110. The set of pixel modification lookup tables 110 may include one-dimensional (1D) lookup tables, such as a first set of pixel modification lookup tables 110A and a second set of pixel modification lookup tables 110B. In the example of FIG. 7, the first set of pixel modification lookup tables 110A and the second set of pixel modification lookup tables 110B each include three 1×17 tables, one for each pixel color component of red, green, and blue. However, there may be more or fewer entries and, in some cases, the tables may not be multi-dimensional (e.g., 2D or higher). For instance, the first set of pixel modification lookup tables 110A may include pixel modification values (e.g., pixel input modification values and/or image data modification values) mapped to corresponding input pixel values for a brightness of the display panel 56 below a first threshold and/or first range (e.g., a low global panel brightness). Similarly, the second set of pixel modification lookup tables 110B may include pixel modification values mapped to corresponding input pixel values for a brightness of the display panel 56 above a second threshold and/or range (e.g., a high global panel brightness), which may be the same as or different from the first threshold or first range, respectively. Moreover, as described above with reference to the drive compensation lookup tables 108, the first set of pixel modification lookup tables 110A and the second set of pixel modification lookup tables 110B may include a respective pixel modification lookup table for each component (e.g., color component) of a pixel, such as red (R), green (G), and blue (B). To that end, pixel modification values may be mapped to input pixel values corresponding to each component of the pixel for the different brightness settings (e.g., low global brightness, high global brightness, and/or the like) of the display panel 56. Further, while the set of pixel modification lookup tables 110 are described herein as being populated based at least in part on a brightness of the display panel 56, the set of pixel modification lookup tables 110 may additionally or alternatively be populated based on any suitable characteristic of the electronic device 10 and/or the display panel 56.

Similar to the operation of the drive compensation lookup tables 108, the set of pixel modification lookup tables 110 may output a respective pixel modification value based at least in part on the current input pixel value (P1) and the previous input pixel value (P0). For example, a lookup table value from a first of the first set of pixel modification lookup tables 110A may be determined for a respective color component in the current pixel image data using an index to the first of the first set of pixel modification lookup tables 110A. The index may be determined based at least in part on the current input pixel value (P1) for the respective color component (e.g., a gray level of the current input pixel value (P1)), the previous input pixel value for the respective color component (e.g., a gray level of the previous input pixel value (P0)), or a combination thereof. Because the first set of first set of pixel modification lookup tables 110A may map pixel modification values to a subset of input pixel values and/or vice versa, the lookup table value may then be interpolated with the current pixel input value (P1) and the previous pixel input value (P0). In some embodiments, for example, the lookup table value may be interpolated using linear interpolation, Barycentric interpolation, a hybrid Barycentric-linear interpolation (e.g., Barycentric interpolation in areas within some distance of a region of the LUT, linear interpretation in other areas), and/or the like.

Moreover, the result of the interpolation may correspond to the portion of a first pixel modification value (M1) output by the first set of pixel modification lookup tables 110A that corresponds to the respective component. The remaining portions of the first pixel modification value (M1), which correspond to the other components of the current input pixel value (P1), may be determined as described above using respective lookup tables (e.g., a second and a third lookup table, respectively) in the first set of pixel modification lookup tables 110A. Further, a second pixel modification value (M2) may be determined as described above with reference to the first pixel modification value (M1) by using the second set of pixel modification lookup tables 110B.

Further, in some embodiments, a third pixel modification value (M3) may be determined based at least in part on the first pixel modification value (M1) and the second pixel modification value (M2). For instance, a respective weight (e.g., mixing factor) may be applied, based at least in part on the global brightness (brightness) of the display panel 56, to each of the first pixel modification value (M1) and the second pixel modification value (M2), and the weighted first and second pixel modification values may be combined to interpolate the third pixel modification value (M3). Accordingly, as shown in the illustrated embodiment, selection circuitry 109B may be implemented to select between the first pixel modification value (M1), the second pixel modification value (M2), and the third pixel modification value (M3) to produce a multi-frame history (H) based at least in part on a select signal (Select). Moreover, the multi-frame history (H) may be routed to subsequent selection circuitry 109C.

As illustrated, the selection circuitry 109C may be implemented to select between the multi-frame history (H) and the current input pixel value (P1) driven to the display panel 56, which at the second time (t2), mat correspond to the previous input pixel value. More specifically, the selection circuitry 109C may be implemented to select between the two values based at least in part on the value of the previous input pixel value (P0) and a pixel modification mode. To that end, the selection circuitry 109C may be implemented to select the multi-frame history (H) when the value of the previous input pixel value (P0) meets a particular condition (e.g., is less than a threshold value, is zero), which may correspond to black (e.g., a target luminance of zero) or some relatively low, and the pixel modification mode is enabled. On the other hand, if the previous pixel input value is non-zero and/or the pixel modification mode is disabled, the selection circuitry 109C may select the current input pixel value P1. In some embodiments, for example, the pixel modification mode may be disabled to conserve power, enable the use of other features, such as a certain refresh rate, and/or the like.

Additionally or alternatively, in some embodiments, the pixel modification circuitry 102 may be implemented such that the multi-frame history (H) is calculated in response to determining the pixel modification mode is enabled and the previous input pixel value (P0) is zero. Accordingly, in some embodiments, the multi-frame history (H) is not calculated when the pixel modification mode is disabled and/or the previous input pixel value (P0) is non-zero. In such embodiments, the pixel modification circuitry 102 may be implemented to output the multi-frame history when the multi-frame history (H) is calculated and to output the current input pixel value (P1) when the multi-frame history (H) is not calculated.

The value output by the selection circuitry 109C (e.g., the current input pixel value (P1) or the multi-frame history (H)) may be written-back to memory 38 via the DMA circuitry 46, for example. Moreover, as illustrated, prior to writing the output back to memory 38, the output may be transformed and/or compressed. As such, the PDC circuitry 48 may include a transform circuitry 112 (e.g., transform circuitry and/or logic) and a compression circuitry 114 (e.g., compression circuitry and/or logic). In some embodiments, the transform circuitry 112 may be implemented to optionally convert the output from a first image data format (e.g., 4:4:4 RGB image data) to a second image data format (e.g., GUV image data and/or a 4:2:2 sub-sampling image format). To that end, in some embodiments, the output may be transformed to an image format that is easier to store, such as an image format occupying less memory. Further, the compression circuitry 114 may be implemented to compress the output using, for example, lossless compression. Accordingly, in some embodiments the memory bandwidth used to access the memory 38 for storage and/or retrieval of the output may be minimized.

To use the multi-frame history (H) produced by the pixel modification circuitry 102 the PDC circuitry 48 and/or the display pipeline 36 (e.g., fetch circuitry 59) may be implemented to retrieve the compressed multi-frame history from the external memory 38. Subsequently, the PDC block may, using a decompression circuitry 116, decompress the compressed multi-frame history (H). Further, an additional transform circuitry 118 may reverse the format transformation (e.g., conversion) performed by the transform circuitry 112. For instance, the additional transform circuitry 118 may return the multi-frame history (H) from the second image data format (e.g., GUV image data and/or a 4:2:2 sub-sampling image format) to the first image format (e.g., 4:4:4 RGB image data) output by the selection circuitry 109C.

Accordingly, the drive compensation circuitry 100 may use the multi-frame history (H) in place of a previous input pixel value to determine the drive compensation to be driven to the display panel 56. That is, for example, the multi-frame history (H) may, along with the current input pixel value (P2), serve as an input to the drive compensation lookup tables 108. Thus, the drive compensation value selected at the selection circuitry 109A may be determined based at least in part on the current input pixel value (P2) at the second time (t2) and the previous two input pixel values (P0 and P1) captured in the multi-frame history (H). Moreover, because the drive compensation is determined based at least in part on the multi-frame history (H), transient response deficiencies resulting from an input pixel value of zero prior to the current input pixel value (P2) may be reduced or eliminated.

Additionally or alternatively, if the selection circuitry 109C selected the current input pixel value (P1), at the second time (t2) the PDC circuitry 48 may be implemented to retrieve the stored input pixel value (P1) as the previous input pixel value (P1). In such embodiments, the drive compensation circuitry 100 may be implemented to determine the drive compensation to be driven to the display panel 56 based at least in part on the current input pixel value (P2) and the previous input pixel value (P1), as described above with reference to the values P1 and P0, respectively, at the first time (t1).

A flowchart of a process 200 for providing drive compensation to a current input pixel value based at least in part on a multi-frame history is illustrated in FIG. 8. While the process 200 is described using steps in a specific sequence, it should be understood that the present disclosure contemplates that the described steps may be performed in different sequences than the sequence illustrated. Further, certain described steps may be skipped or not performed altogether, while additional steps may be included in the process 200. In some embodiments, at least some of the steps of the process 200 may be implemented at least in part by that processor core complex 18 that executes instructions stored in a tangible, non-transitory, computer-readable medium, such as the controller memory 44. In alternative or additional embodiments, at least some steps of the process 200 may be implemented by the PDC circuitry 48, the display pipeline 36, and/or any other suitable components or control logic, such as another electronic device.

In some embodiments, the process 200 may be initiated by current input pixel data being processed (e.g., modified) to produce a multi-frame history (process block 202). For example, as described herein, the pixel modification circuitry 102 may produce the multi-frame history (H) based at least in part on a current input pixel value (P1) and a previous input pixel value (P0) (e.g., an input pixel value displayed directly prior to the current input pixel value). More specifically, in some embodiments, the pixel modification circuitry 102 may effectively capture the multi-frame history (H) by interpolating pixel modification values (e.g., the first pixel modification value (M1), the second pixel modification value (M2), the third pixel modification value (M3), and/or the like), the current input pixel value (P1), and the previous pixel value (P0).

The process 200 may proceed with the multi-frame history (H) being written-back to memory, such as external memory 38 and/or memory 20 (process block 204). In some embodiments, for example, the multi-frame history (H) may be written-back from the PDC circuitry 48 via DMA (e.g., via the DMA circuitry 46). Moreover, prior to writing the multi-frame history (H) back to the memory, in some embodiments, the pixel modification circuitry 102 may transform and/or compress the multi-frame history (H). In such embodiments, the bandwidth used to write the multi-frame history (H) back to the memory may be reduced compared to the bandwidth used to write-back multi-frame history (H) that is neither compressed nor transformed.

After the multi-frame history (H) is written-back to memory, the multi-frame history (H) may be retrieved from memory (process block 206). For instance, the fetch circuitry 59 may be implemented to retrieve (e.g., to request to retrieve) the multi-frame history (H) from the external memory 38. Moreover, in some embodiments, the fetch circuitry 59 may be implemented to request to retrieve the multi-frame history (H) when a current input pixel value P2 is implemented to be driven to the display panel 56 (e.g., at the second time (t2)). That is, for example, the multi-frame history may be retrieved such that the values (e.g., the current input pixel value (P1) and the previous input pixel value (P0)) used to determine the multi-frame history (H) correspond to the two pixel input data values directly previous to the current input pixel value (P2).

The method may then proceed by the current input pixel data (P2) being compensated (e.g., drive compensated) based at least in part on the multi-frame history (H), to account for transient response deficiencies (e.g., visual artifacts) (process block 208). To that end, the drive compensation circuitry 100 may drive an output pixel value to the display panel 56 and/or to the output buffer 54 based at least in part on the current input pixel data (P2), the multi-frame history (H), and certain drive compensation values, which may be stored in the drive compensation lookup tables 108. Additionally, in some embodiments, the drive compensation circuitry drive an output pixel value to the display panel 56 and/or to the output buffer 54 based at least in part on an operating characteristic of the display panel 56, such as a global brightness level, a temperature, an age, and/or the like.

It is noted that in some cases, a starting condition may be considered before performing operations according to the method 200 of FIG. 8. In particular, a situation may occur where, when transitioning through a single frame, drive compensation is based on one prior frame (e.g., a multi-frame history (H) is unavailable). This may represent a starting frame for the pixel drive compensation operations discussed herein. For example, the drive compensation operation may start with a first frame, N, however for the first frame no drive compensation may be performed since there is no multi-frame history (H) available. In this case, a single frame drive compensation operation may be performed on the first frame, and the drive compensation may be performed on subsequent frames (e.g., second frame, and so on). The single frame drive compensation operation may include performing drive compensation on the first frame, N, and writing-back the result to memory 38. The first frame, N, that was written-back may be further modified to achieve an effective two-frame history based drive compensation for subsequent frames. In this way, the first frame, N, associated with the starting condition identified a first frame to begin generation of the multi-frame history (H).

The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. For example, while the techniques are described herein with reference to values at a first time (t1) and a second time (t2), the techniques may be repeated and/or extended to any suitable number of time points. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).

Claims

1. Pixel drive compensation circuitry, comprising: pixel modification circuitry, wherein the pixel modification circuitry is configured to: receive a first input pixel data and a second input pixel data;determine whether the second input pixel data satisfies a first condition;in response to determining that the second input pixel data satisfies the first condition, modify the first input pixel data based at least in part on the second input pixel data to produce a historical pixel value;in response to determining that the second input pixel data does not satisfy the first condition, storing the first input pixel data as the historical pixel value without modification; andperform a write-back of the historical pixel value to memory communicatively coupled to the pixel modification circuitry; anddrive compensation circuitry, wherein the drive compensation circuitry is configured to: retrieve the historical pixel value from the memory; anddetermine a drive compensation value based at least in part on third input pixel data and the historical pixel value, wherein one or more electronic displays are configured to drive a pixel of one or more display panels based at least in part on the drive compensation value.

2. The pixel drive compensation circuitry of claim 1, wherein the first input pixel data corresponds to a first image frame displayed on the one or more display panels at a first time, wherein the second input pixel data corresponds to a second image frame displayed on the one or more display panels at a second time before the first time, and wherein the third input pixel data corresponds to a third image frame displayed on the one or more display panels at a third time after the first time.

3. The pixel drive compensation circuitry of claim 1, wherein the first input pixel data comprises a gray level of the pixel of the one or more display panels.

4. The pixel drive compensation circuitry of claim 1, wherein the pixel modification circuitry comprises a set of lookup tables, wherein the pixel modification circuitry is configured to modify the first input pixel data based at least in part on an interpolation of the first input pixel data, the second input pixel data, and an output of the set of lookup tables.

5. The pixel drive compensation circuitry of claim 4, wherein the set of lookup tables comprises a first set of lookup tables and a second set of lookup tables, wherein the first set of lookup tables comprises first pixel modification values calibrated based at least in part on a first range of a characteristic of the one or more display panels, wherein the second set of lookup tables comprises second pixel modification values calibrated based at least in part on a second range of the characteristic of the one or more display panels.

6. The pixel drive compensation circuitry of claim 5, wherein the characteristic comprises a brightness of the one or more display panels.

7. The pixel drive compensation circuitry of claim 1, wherein the drive compensation circuitry comprises a set of lookup tables, wherein the drive compensation circuitry is configured to determine the drive compensation value based at least in part on an interpolation of the third input pixel data, the historical pixel value, and an output of the set of lookup tables.

8. The pixel drive compensation circuitry of claim 7, wherein the interpolation comprises a Barycentric interpolation, a hybrid Barycentric-bilinear interpolation, or a combination thereof.

9. The pixel drive compensation circuitry of claim 1, wherein the pixel modification circuitry is configured to perform the write-back in response to determining that a pixel modification mode of the pixel drive compensation circuitry is enabled and that the second input pixel data corresponds to a gray level of zero.

10. The pixel drive compensation circuitry of claim 9, wherein the pixel modification circuitry is configured to, in response to determining that the pixel modification mode of the pixel drive compensation circuitry is disabled or that the second input pixel data corresponds to a non-zero gray level or in response to a starting condition, perform a write-back of the first input pixel data to the memory without modification, wherein the starting condition corresponds to a first frame to begin generation of the historical pixel value.

11. The pixel drive compensation circuitry of claim 1, wherein the pixel modification circuitry is configured to modify the first input pixel data in response to determining that a pixel modification mode of the pixel drive compensation circuitry is enabled and that the second input pixel data corresponds to a gray level of zero.

12. The pixel drive compensation circuitry of claim 1, wherein the drive compensation circuitry is configured to: retrieve fourth input pixel data from the memory; anddetermine an additional drive compensation value based at least in part on a fifth input pixel data and the fourth input pixel data, wherein the one or more electronic displays are configured to drive the pixel of the one or more display panels based at least in part on the additional drive compensation value.

13. The pixel drive compensation circuitry of claim 1, wherein the one or more display panels comprise a light-emitting diode display.

14. The pixel drive compensation circuitry of claim 1, wherein the pixel modification circuitry is configured to produce the historical pixel value based at least in part on input pixel data corresponding to three or more image frames.

15. A method for operating a pixel drive compensation circuitry implemented in an electronic device, comprising: retrieving a first input pixel value of a first image frame and a second input pixel value of a second image frame, wherein the first input pixel value and the second input pixel value correspond to a first display pixel on an electronic display, and wherein the second image frame occurs after the first image frame;performing pixel drive compensation to generate compensated second pixel data to compensate for a transient response variation that would otherwise occur on the electronic display due at least in part to a difference between the first input pixel value and the second input pixel value;driving the first display pixel of the electronic display using the compensated second pixel data;in response to determining that the first input pixel value satisfies a first condition, modifying the second input pixel value to produce a historical pixel value based at least in part on the first input pixel value, wherein the historical pixel value differs from the second input pixel value in an amount that takes into account a historical effect of the first input pixel value;in response to determining that the first input pixel value does not satisfy the first condition, storing the second input pixel value as the historical pixel value without modification;writing back the historical pixel value to memory;retrieving a third input pixel value of a third image frame and the historical pixel value, wherein the third input pixel value corresponds to the first display pixel on the electronic display, and wherein the third image frame occurs after the second image frame;performing pixel drive compensation based at least in part on the third input pixel value and the historical pixel value to generate compensated third pixel value to compensate for a transient response variation that would otherwise occur on the electronic display due at least in part to a difference between the first input pixel value, the second input pixel value, and the third input pixel value; anddriving the first display pixel of the electronic display using the compensated third pixel value.

16. The method of claim 15, wherein the first input pixel value is determined to satisfy the first condition when the first input pixel value is less than a threshold value.

17. The method of claim 15, wherein the first input pixel value is determined to satisfy the first condition when the first input pixel value represents a gray level of zero.

18. The method of claim 15, comprising compressing the historical pixel value before writing back the historical pixel value to the memory.

19. The method of claim 16, comprising decompressing the historical pixel value before or after the historical pixel value is retrieved.

20. An electronic device comprising: one or more display panels;a memory; anda display pipeline coupled between the memory and the one or more display panels, wherein the display pipeline comprises: pixel drive compensation circuitry, comprising: pixel modification circuitry, wherein the pixel modification circuitry is configured to: receive a first input pixel value and a second input pixel value;determine whether the second input pixel value satisfies a first condition;in response to determining that the second input pixel value satisfies the first condition, modify the first input pixel value based at least in part on the second input pixel value to produce a historical pixel value;in response to determining that the second input pixel value does not satisfy the first condition, store the first input pixel value as the historical pixel value without modification; andperform a write-back of the historical pixel value to the memory; anddrive compensation circuitry, wherein the drive compensation circuitry is configured to: retrieve the historical pixel value from the memory; and determine a drive compensation value based at least in part on third input pixel value and the historical pixel value, wherein the one or more display panels are configured to drive a pixel based at least in part on the drive compensation value.

21. The electronic device of claim 20, wherein the pixel modification circuitry is configured to transform the historical pixel value from a first image format to a second image format before performing the write-back of the historical pixel value to the memory.

22. The electronic device of claim 21, wherein the drive compensation circuitry is configured to, after retrieving the historical pixel value from the memory, transform the historical pixel value from the second image format to the first image format.