Patent Application
20080030510
Referring to
The first GPU 130 may be integrated in the chipset 120 as an IGP (integrated processing platform), or a discrete device out of the chipset 120. The number of the GPUs is not limited. But in this embodiment, two GPUs including the first GPU 130 and the second GPU 150 are employed to illustrate how to work on a graphics context.
The CPU 110 divides graphics content into two parts for the two GPUs, such as a frame for the GPU 130 and a frame for the GPU 150, the upper frame for the GPU 130 and the lower frame for the GPU 150, and an odd line for the GPU 130 and an even line for the GPU 150. The above methods are symmetric loading for the two GPUs. Or the graphics content is divided into two parts with different sizes, such as ⅓ frame and the rest ⅔ frame, asymmetric loading for the two GPUs. A part of the graphics content is sent to the GPU 130 to process, and the processed result of the GPU 130 is sent to the graphics memory 140 to store. The other part of the graphics content is sent to the GPU 150 to process, and also the processed result of the GPU 150 is sent to the graphics memory 160 to store.
The processed result of the second GPU 150 is sent to a memory device (not shown) from the second graphics memory 160 via the chipset 120 if a display is connected to the first GPU 130. The memory device may be a main memory electrically connected to the chipset 120 or the CPU 110. And then the processed result of the second GPU 150 is sent to the first graphics memory 140 from the memory device to be combined with the other processed graphics content of the first GPU 130 which is also stored in the first graphics memory 140. Finally, the first GPU 130 gets the combined processed result from the first graphics memory 140 and then output it to the display.
Referring to
In step 201, a CPU issues a command stream to run an application program (AP), such as a game. In step 202, An API command stream is generated via the AP. In step 203, an API (application program interface), such as an OpenGL or Direct X, receives the API command stream, and generates a graphics command stream for a video driver (or called a graphics driver). In step 204, the video driver receives the graphics command stream and then generates the first GPU command stream for the first GPU and the second GPU command stream for the second GPU. In step 205, the first GPU command stream is sent to the first GPU and the second GPU command stream is sent to the second GPU. The two GPUs process the two GPU command streams separately. In step 206, the processed results of the GPU commands are combined via a chipset and a memory device to output to a display.
The video driver uses the commands such as Ready, Go and Wait to enable the two GPUs alternately for the synchronization between the two GPUs. When one GPU is enabled, the other one is waiting by the use of the command “Wait”. When the processes executing in the GPU are done, it transmits a command “Go” to the video driver 360. The video driver 360 transmits a command “Go” to the other GPU to enable the other GPU. Moreover, it will be understood by those skilled in the art that the executing sequence and the mass or structure of the data processed in the above steps can be dynamically modified but not limited to the sequence and structure disclosure in this embodiment. Furthermore, the video diver 360 can be implemented by the use of hardware, such as Integrated Circuit, IC, which depends on the demands of user.
In conclusion, the present invention uses a video driver to implement the distribution of GPU command streams, and then accelerates graphics processes by switching the GPUs. The present invention also uses a method to integrate data by the way of writing into/reading from the main memory for accessing the processed data and the use of a chipset having abilities of bidirectional data transmission among the CPU and the main memory and the GPUs. The present invention provides a multi-GPU rendering system without using any adding connector to the GPUs in the graphics processing system, any adding elements for integrating and synchronizing image information, or GPUs having the same performance. The multi-GPU rendering system is also not limited by GPUs using the same core or manufactured by the same manufacturer.
One skilled in the art will understand that the embodiment of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.
The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
