Patent Application
20240213932
The invention relates to electronic circuits, and more particularly to radio frequency amplifier circuits.
Many modern electronic systems include radio frequency (RF) receivers; examples include cellular telephones, personal computers, tablet computers, wireless network components, televisions, cable system “set top” boxes, and radar systems. Many RF receivers are paired with RF transmitters in the form of transceivers, which often are quite complex two-way radios. In some cases, RF transceivers are capable of transmitting and receiving across multiple frequencies in multiple bands.
Amplifiers are a common component in RF transmitters, receivers, and transceivers, and are frequently used for power amplification of transmitted RF signals and for low-noise amplification of received RF signals. For many RF systems, particularly those requiring low power and/or portability (e.g., cellular telephones, WiFi-connected computers, cameras, and other devices), it has become common to use complementary metal-oxide semiconductor (CMOS) fabrication technology to create low cost, low power integrated circuits (ICs). CMOS devices include bulk CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS being a type of SOI fabrication technology).
Receiving an RF signal in many environments requires a high quality low-noise amplifier (LNA) as part of an RF “front end” (RFFE) receiver or transceiver chain of circuits. Important desired characteristics of an LNA are high gain with low noise, a wide bandwidth, good linearity, and good input and output impedance matching. However, in general, all of these factors cannot be optimized simultaneously, and accordingly there are tradeoffs between these characteristics when designing an LNA.
Five important design parameters for LNAs are gain, noise figure (NF), input-referenced third intercept point (IIP3), output reflection coefficient, and input reflection coefficient. NF is a measure of degradation of the signal-to-noise ratio (SNR) caused by components in a signal chain, with lower values indicating better performance. IIP3 is a figure of merit representing amplifier linearity, with higher values indicating better performance. In general, NF has a stricter specification requirement in high-gain modes than in low gain-modes, while IIP3 has a stricter specification requirement in low-gain modes than in high-gain modes. The output reflection coefficient is the S22 scattering parameter (or “S-parameter”) and is an indication of output impedance matching, with lower (more negative, when evaluated logarithmically) numbers indicating better impedance matching. The input reflection coefficient is the S11 S-parameter and is an indication of input impedance matching, with lower (more negative, when evaluated logarithmically) numbers indicating better performance.
Increases in the frequency of RF communications bands and channels, as well as a continuing increase in the number of bands and channels in use, has pushed current LNA architectures to their limits. For example, achieving stringent requirements for gain, percentage bandwidth, linearity, and input and output impedance matching with a traditional LNA architecture is difficult, and sometimes impossible, for some of the new 5G mobile network bands, particularly in the 3 to 6 GHz NR bands, the upcoming 7-24 GHz bands, and the millimeter wave range (e.g., 24.25 GHZ to 52.6 GHz), owing to insufficient wide-band performance (e.g., “wide-band” meaning a bandwidth from about 1.4 GHz to about 2.7 GHZ).
Wide-band LNAs present several design challenges. For example, achieving effective wide-band impedance matching at the input of an LNA is a key objective for attaining overall performance, especially NF. Known approaches to input impedance (IM) matching involve using a series inductor between an LNA input terminal and the amplification core (e.g., a cascode transistor pair) but those solutions have limited bandwidth.
For example,
The source of the common-gate FET MCG is connected to the drain of the common-source FET MCS. The drain of the common-gate FET MCG provides an amplified RF output signal at what may be regarded as an amplified-signal terminal AST of the amplification core 102. A first bias circuit (not shown) may be included to provide a suitable bias voltage CG_VBIAS to the common-gate FET MCG and a second bias circuit (not shown) may be included to provide a suitable bias voltage CS_VBIAS to the common-source FET MCS. In the illustrated example, the amplified-signal terminal AST is coupled to a voltage source VDD through an inductor L2 and to an RF output terminal RFOUT and through an output capacitor COUT. The RF output terminal RFOUT would typically be coupled to a 50-ohm load for many modern RF circuits. An inductor L3 is coupled between what may be regarded as a degeneration terminal DT of the amplification core 102 and a reference potential, such as circuit ground.
The illustrated example includes a bypass and input matching (IM) feedback circuit 104. An IM feedback portion of the bypass/IM feedback circuit 104 is coupled between the amplified-signal terminal AST (through a capacitor CBP) and the input terminal INT (through capacitor CIN), and in the illustrated example includes a resistor RFB series-coupled to a switch SFB1, the combination of which is series-coupled between capacitor CBP and capacitor CIN. In some embodiments, CBP and/or RFB may be adjustable or have fixed values. The IM feedback portion of the bypass/IM feedback circuit 104 may be enabled by closing switch SFB1 and disabled by opening switch SFB1.
A bypass portion of the bypass/IM feedback circuit 104 accommodates strong RF input signals that do not need amplification, allowing such signals to be coupled more directly to RFOUT. The bypass portion includes switches SFB2 and SFB3 coupled in series between capacitor CBP and capacitor CIN. An AC ground is coupled by a switch SFB4 to a midpoint node between switches SFB2 and SFB3. Switches SFB2 and SFB3 may both be CLOSED (OFF) and switch SFB4 OPENED (ON) to create a passive AC bypass path from RFIN through switches SFB2 and SFB3 and capacitors CBP and COUT to RFOUT. When the bypass mode is OFF, switches SFB2 and SFB3 are OPEN (ON) and switch SFB4 is CLOSED (OFF) to improve isolation. The passive AC bypass path is tied to the LNA load to achieve bypass matching.
Most of the components shown in
The basic embodiment of
TABLE 1 summarizes the passive mode negative gain for a modeled embodiment of the LNA circuit 100.
More generally, it is very challenging to achieve reasonable passive mode negative gain (−3 dB or even −6 dB, for example) for lower frequency bands in a very wide-band LNA which uses a large series inductor L1 for input matching. Accordingly, there is a need for an LNA architecture that overcomes the limitations of conventional LNA architectures.
The present invention encompasses new multi-input LNA architectures with improved passive mode negative gain performance that reconfigure the bypass path routes to achieve wide-band bypass matching and make bypass matching for lower frequency bands possible to achieve desired gain specifications.
In a first embodiment, improved wide-band performance is provided in part by a bypass path that optionally does not pass through an impedance matching network and thus has a dedicated path to RFOUT.
In a second embodiment, improved wide-band performance is provided in part by a bypass path that does not pass through an input inductor.
In a third embodiment, improved wide-band performance is provided in part by a bypass path that has a first portion that optionally does not pass through an impedance matching network and thus has a dedicated path to RFOUT, and a second portion that does not pass through an input inductor.
In a fourth embodiment, improved wide-band performance is provided in part by selectively disabling a load inductor in some modes of operation.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
The present invention encompasses new multi-input LNA architectures with improved passive mode negative gain performance that reconfigure the bypass path routes to achieve wide-band bypass matching and make bypass matching for lower frequency bands possible to achieve desired gain specifications. In general, a “multi-input LNA” means a single LNA block have multiple selectable inputs, each input having access to shared and/or dedicated bypass and active amplification paths. A single LNA block may have multiple individual LNA circuits coupled in parallel but in a compact configuration.
In the illustrated example, the LNA circuit 200 includes an amplifier core 202. An RF input signal applied to an RF input terminal RFIN is coupled through a series input matching inductor L1 and a DC blocking capacitor CIN to the input terminal INT of the amplification core 202. Suitable bias voltages VBIAS may be provided for the FETs within the amplification core 202. The amplified-signal terminal AST is coupled to an inductor L2 at a node X, which is also coupled to a voltage source VDD. A degeneration inductor L3 is coupled between the degeneration terminal DT of the amplification core 202 and a reference potential, such as circuit ground. In the illustrated embodiment, the amplifier core optionally may include a FET stack and the inductor L3 may be a variable inductor (see below for examples of a FET stack and variable inductor configurations). An adjustable degeneration inductor L3 may be used to improve linearity in low gain modes. For example, a smaller value for the degeneration inductor L3 may be used in a high gain mode or modes, and a larger value for the degeneration inductor L3 may be used in a low gain mode or modes.
The LNA circuit 200 includes a bypass/IM feedback circuit 104 coupled between the amplified-signal terminal AST (through a capacitor CBP) and the input terminal INT (through capacitor CIN). An IM feedback portion of the bypass/IM feedback circuit 104 may be enabled by closing switch SFB1 and disabled by opening switch SFB1. In various gain modes, the in-circuit presence of resistor RFB allows the Q-factor of the input impedance matching to be reduced, which increases the bandwidth of the LNA circuit 200 at the expense of gain and NF (see below for an example of a variable resistance configuration of the bypass/IM feedback circuit 104). Note that introduced feedback will naturally improve the system bandwidth as well. An advantage of using a variable or multi-state bypass/IM feedback circuit 104 is that multiple resistance values enable multiple gain modes. For instance, LNAs in mobile RF receiver devices may need multiple gain modes depending upon the range of input signal strength at the receiver. In addition, enabling multiple gain modes by using a variable or multi-state feedback resistor RFB may eliminate the need for an output attenuator (common in conventional receiver LNAs).
A bypass portion of the bypass/IM feedback circuit 104 accommodates strong RF input signals that do not need amplification, allowing such signals to be coupled more directly to RFOUT. The bypass portion includes switches SFB2 and SFB3 coupled in series between capacitor CBP and capacitor CIN. An AC ground is coupled by a switch SFB4 to a midpoint node between switches SFB2 and SFB3. Switches SFB2 and SFB3 may both be CLOSED and switch SFB4 OPENED to create a passive AC bypass path through switches SFB2 and SFB3. When the bypass mode is OFF, switches SFB2 and SFB3 are OPEN and switch SFB4 is CLOSED to improve isolation.
An added matching inductor L4 is coupled to the midpoint node between switches SFB2 and SFB3. When the passive bypass path is enabled, the matching inductor L4 resonates the parasitic capacitance at the node where inductor L4 is connected to improve the Q of the bypass path, thus reducing loss. The matching inductor L4 may be a fixed inductor or may be a variable inductor (as illustrated), which enables greater flexibility in lower frequency band matching (see below for an example of a variable inductor configuration). The matching inductor L4 may be an on-chip component, but typically would be an off-chip component to accommodate different applications. Also coupled to the midpoint node between switches SFB2 and SFB3 is a matching capacitor CM, which preferably is on-chip and may be a fixed capacitor or may be a variable capacitor (as illustrated). The matching capacitor Cy enables greater flexibility in wide-band matching (see below for an example of a variable capacitor configuration).
The capacitor CBP is coupled to node X (and thus to capacitor COUT) through a switch SBP1. Capacitor COUT is coupled to RFOUT through a switch SBP2. In addition, a second path from the bypass/IM feedback circuit 104 to RFOUT is provided through capacitor CBP2, switch SBP3, and switch SBP4, as well as through capacitor CBP (which is coupled in parallel with capacitor CBP2 when switch SBP3 is closed). A shunt connection 204 couples a node Y between capacitor CBP and switch SBP1 to a node Z between switch SBP3 and switch SBP4.
In a first mode of operation, in which IM feedback is enabled, switches SFB2 and SFB3 are OPEN and switches SFB1 and SFB4 are CLOSED in the bypass/IM feedback circuit 104, and switches SBP1 and SBP2 are CLOSED and switches SBP3 and SBP4 are OPEN. Feedback is thus provided from the amplified-signal terminal AST (through capacitor CBP) to the input terminal INT (through capacitor CIN). In a variant of the first mode of operation, if stronger feedback is needed, then switch SBP3 may be CLOSED, allowing feedback through capacitor CBP as well.
Several primary modes of bypass operation are available by setting switches SFB2 and SFB3 to CLOSED and switches SFB1 and SFB4 to OPEN in the bypass/IM feedback circuit 104 (i.e., the bypass/IM feedback circuit 104 is set to a “BYPASS” state). For example, in a first bypass mode in which a first bypass path is enabled, the bypass/IM feedback circuit 104 is set to the BYPASS state, switches SBP1 and SBP2 are CLOSED, and switches SBP3 and SBP4 are OPEN. Accordingly, this mode enables a bypass path that allows RF input signals to propagate through inductor L1, the bypass/IM feedback circuit 104, and capacitors CBP and COUT to RFOUT.
In a second mode of operation in which a second bypass path is enabled, the bypass/IM feedback circuit 104 is set to the BYPASS state, switches SBP1, SBP2, and SBP3 are CLOSED, and switch SBP4 is OPEN. This configuration couples capacitors CBP and CBP2 in parallel due to the shunt connection 204. Accordingly, this mode enables a bypass path that allows RF input signals to propagate through inductor L1, the bypass/IM feedback circuit 104, parallel capacitors CBP and CBP2, and capacitor COUT to RFOUT. In some embodiments and some modes, inductor L2 may influence the RF signal passing to RFOUT.
In a third mode of operation in which a third bypass path is enabled, the bypass/IM feedback circuit 104 is set to the BYPASS state, switch SBP4 is CLOSED, and switches SBP1, SBP2, and SBP3 are OPEN. Accordingly, this mode enables a bypass path that allows RF input signals to propagate through inductor L1, the bypass/IM feedback circuit 104, and capacitor CBP to RFOUT (through shunt connection 204), thus bypassing capacitor COUT and avoiding the impedance matching network comprising inductor L2 and capacitor COUT.
In a fourth mode of operation in which a fourth bypass path is enabled, the bypass/IM feedback circuit 104 is set to the BYPASS state, switches SBP3 and SBP4 are CLOSED, and switches SBP1 and SBP2 are OPEN. This configuration couples capacitors CBP and CBP2 in parallel due to the shunt connection 204. Accordingly, this mode enables a bypass path that allows RF input signals to propagate through inductor L1, the bypass/IM feedback circuit 104, and parallel capacitors CBP and CBP2 to RFOUT, bypassing capacitor COUT (thus avoiding the impedance matching network comprising inductor L2 and capacitor COUT).
As should be appreciated, in light of the number of controllable switches SFB1-SFB3 and SBP1-SBP4, some additional modes of operation may be available that may be useful in particular applications.
Note that the LNA amplifier core 202 may be turned OFF in any of the bypass modes to save current. The LNA amplifier core 202 may be turned OFF, for example, by setting the bias voltage for the input common-source FET MCS to ground. However, turning the LNA amplifier core 202 OFF is not required—there may be cases where it is desirable to keep the LNA amplifier core 202 ON in order to reduce gain switching time.
Selection of a mode of operation generally depends on whether a bypass path is needed, and the frequency of the input signal. For example, at high frequencies and signal strengths, the third or fourth bypass modes of operation may be preferred, since either mode avoids the impedance matching network comprising inductor L2 and capacitor COUT. Modeling the LNA circuit 200 and testing the available modes of operation over a range of frequency may determine optimal selection of modes. A controller (not shown, but a common component) coupled to the various switches controls the OPEN or CLOSED states of those switches in response to external commands and/or to provided system information, such as selected frequency band, signal strength, etc.
TABLE 2 summarizes the passive mode negative gain for two modeled embodiments of the LNA circuit 200.
Reference was made above to variable capacitors, variable resistors, variable inductors, and FET stacks.
In the illustrated example, the LNA circuit 700 is similar in many aspects to the LNA circuit 100 of
In a first bypass mode of operation, the bypass/IM feedback circuit 104 is set to the first BYPASS state and switch SwBP is CLOSED. Accordingly, this mode enables a bypass path that allows RF input signals to propagate through the bypass/IM feedback circuit 104 and capacitors CBP and COUT to RFOUT, bypassing the input inductor L1.
In some embodiments, an optional added matching inductor L4 may be coupled to the midpoint node between switches SFB2 and SFB3 to provide better matching. The optional matching inductor L4 preferably is on-chip (but may be off-chip) and may be a fixed inductor (as illustrated), or may be a variable inductor to provide greater flexibility in matching.
Selection of a mode of operation generally depends on whether a bypass path is needed, and the frequency of the input signal. Modeling the LNA circuit 700 and testing the available modes of operation over a range of frequency may determine optimal selection of modes. A controller (not shown, but a common component) coupled to the various switches controls the OPEN or CLOSED states of those switches in response to external commands and/or to provided system information, such as selected frequency band, signal strength, etc.
In the illustrated example, the LNA circuit 800 is essentially a combination of the LNA circuit 200 of
TABLE 3 summarizes the passive mode negative gain for one modeled embodiment of the LNA circuit 800.
In the illustrated example, the LNA circuit 900 includes an amplifier core 202. An RF input signal applied to an RF input terminal RFIN is coupled through a series input matching inductor L1 and a DC blocking capacitor CIN to the input terminal INT of the amplification core 202. Suitable bias voltages VBIAS may be provided for the FETs within the amplification core 202. The amplified-signal terminal AST is coupled to a load inductor L2 at a node X, which is also coupled to a voltage source VDD through a mode switch Sw1. Inductor L2 may be a fixed inductor or may be a variable inductor (as illustrated). An inductor L3 is coupled between the degeneration terminal DT of the amplification core 202 and a reference potential, such as circuit ground. In the illustrated embodiment, the amplifier core 202 optionally may include a FET stack, and the inductor L3 may be a variable inductor.
The LNA circuit 900 includes a bypass/IM feedback circuit 104 coupled between the amplified-signal terminal AST (through a capacitor CBP) and the input terminal INT (through capacitor CIN). A first bypass switch SBP1 is coupled in parallel with capacitor CBP. A capacitor CBP2 is coupled from a node between the mode switch Sw1 and inductor L2 to a reference potential. A second bypass switch SBP2 is coupled in parallel with capacitor CBP2 (note that bypass switch SBP2 and capacitor CBP2 are in different locations compared to like-named elements in other figures). A capacitor COUT is coupled between node X and the output terminal RFOUT. In some embodiments, a variable matching capacitor CM1 is coupled in parallel with capacitor COUT to provide greater flexibility in matching.
Coupled to the midpoint node between switches SFB2 and SFB3 is a matching capacitor CM2, which preferably is on-chip (but may be off-chip) and may be a fixed capacitor or may be a variable capacitor (as illustrated). Capacitor CM2 enables greater flexibility in wide-band matching.
In some embodiments, an optional selectable matching inductor L4 may be coupled to the midpoint node between switches SFB2 and SFB3 through a connecting switch Sw2 to provide greater flexibility in matching. The optional matching inductor L4, which preferably is on-chip (but may be off-chip), may be a fixed inductor (as illustrated), or may be a variable inductor to provide greater flexibility in matching.
For a non-bypass mode of operation, the IM feedback portion of the bypass/IM feedback circuit 104 is enabled (meaning switches SFB2 and SFB3 are OPEN and switches SFB1 and SFB4 are CLOSED), switch Sw1 is CLOSED, and switches Sw2, SBP1, and SBP2 are OPEN.
In a first bypass mode of operation, the bypass/IM feedback circuit 104 is set to a BYPASS state (meaning switches SFB2 and SFB3 are CLOSED and switches SFB1 and SFB4 are OPEN), switches Sw1, Sw2, and SBP2 are OPEN, and switch SBP1 is CLOSED.
In a second bypass mode of operation, which may be particularly useful for higher frequency bands (e.g., 2.3-2.7 GHZ), the bypass/IM feedback circuit 104 is set to a BYPASS state, switches Sw1 and SBP2 are OPEN, and switches Sw2 and SBP1 is CLOSED.
In a third bypass mode of operation, which may be particularly useful for lower frequency bands (e.g., 1.4-2.2 GHZ), the bypass/IM feedback circuit 104 is set to a BYPASS state, switches Sw1 and Sw2 are OPEN, and switches SBP1 and SBP2 are CLOSED.
Note that in all three of the example bypass modes of operation, the inductor L2 is disconnected from VDD by opening switch Sw1. As should be appreciated, in light of the number of controllable switches, some additional modes of operation may be available that may be useful in particular applications.
Advantages of the LNA circuit 900 include: a minimum impact on active gain states; no additional inductor needed at all (i.e., the optional matching inductor L4 may be omitted entirely); and the LNA circuit size is kept small as only a few switches and logic cells are used.
TABLE 4 summarizes the passive mode negative gain for two modeled embodiments of the LNA circuit 900.
Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
As one example of further integration of embodiments of the present invention with other components,
The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and/or affixed to the substrate 1000. While shown as generic rectangles, the passive devices 1006 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1000 to other passive devices 1006 and/or the individual ICs 1002a-1002d.
The front or back surface of the substrate 1000 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1000; one example of a front-surface antenna 1008 is shown, coupled to an IC die 1002b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1000, a complete radio may be created.
Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.
Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G New Radio, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.
As an example of wireless RF system usage,
A wireless device 1106 may be capable of communicating with multiple wireless communication systems 1102, 1104 using one or more of telecommunication protocols such as the protocols noted above. A wireless device 1106 also may be capable of communicating with one or more satellites 1108, such as navigation satellites (e.g., GPS) and/or telecommunication satellites. The wireless device 1106 may be equipped with multiple antennas, externally and/or internally, for operation on different frequencies and/or to provide diversity against deleterious path effects such as fading and multi-path interference.
The wireless communication system 1102 may be, for example, a CDMA-based system that includes one or more base station transceivers (BSTs) 1110 and at least one switching center (SC) 1112. Each BST 1110 provides over-the-air RF communication for wireless devices 1106 within its coverage area. The SC 1112 couples to one or more BSTs 1110 in the wireless system 1102 and provides coordination and control for those BSTs 1110.
The wireless communication system 1104 may be, for example, a TDMA-based system that includes one or more transceiver nodes 1114 and a network center (NC) 1116. Each transceiver node 1114 provides over-the-air RF communication for wireless devices 1106 within its coverage area. The NC 1116 couples to one or more transceiver nodes 1114 in the wireless system 1104 and provides coordination and control for those transceiver nodes 1114.
In general, each BST 1110 and transceiver node 1114 is a fixed station that provides communication coverage for wireless devices 1106, and may also be referred to as base stations or some other terminology known in the telecommunications industry. The SC 1112 and the NC 1116 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies known in the telecommunications industry.
An important aspect of any wireless system, including the systems shown in
The receiver path Rx receives over-the-air RF signals through at least one antenna 1202 and a switching unit 1204, which may be implemented with active switching devices (e.g., field effect transistors or FETs) and/or with passive devices that implement frequency-domain multiplexing, such as a diplexer or duplexer. An RF filter 1206 passes desired received RF signals to at least one low noise amplifier (LNA) 1208a, the output of which is coupled from the RFFE Module to at least one LNA 1208b in the Mixing Block (through transmission line TIN in this example). The LNA(s) 1208b may provide buffering, input matching, and reverse isolation. In some embodiments, the LNA(s) 1208a and 1208b may be a single LNA, and in any case may be instances of the novel LNAs disclosed above.
The output of the LNA(s) 1208b is combined in a corresponding mixer 1210 with the output of a first local oscillator 1212 to produce an IF signal. The IF signal may be amplified by an IF amplifier 1214 and subjected to an IF filter 1216 before being applied to a demodulator 1218, which may be coupled to a second local oscillator 1220. The demodulated output of the demodulator 1218 is transformed to a digital signal by an analog-to-digital converter 1222 and provided to one or more system components 1224 (e.g., a video graphics circuit, a sound circuit, memory devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols, such as text or other characters.
In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the differentiation between sections may be different). Digital data from one or more system components 1224 is transformed to an analog signal by a digital-to-analog converter 1226, the output of which is applied to a modulator 1228, which also may be coupled to the second local oscillator 1220. The modulated output of the modulator 1228 may be subjected to an IF filter 1230 before being amplified by an IF amplifier 1232. The output of the IF amplifier 1232 is then combined in a mixer 1234 with the output of the first local oscillator 1212 to produce an RF signal. The RF signal may be amplified by a driver 1236, the output of which is coupled to a power amplifier (PA) 1238 (through transmission line Tour in this example). The amplified RF signal may be coupled to an RF filter 1240, the output of which is coupled to at least one antenna 1202 through the switching unit 1204.
The operation of the transceiver 1200 is controlled by a microprocessor 1242 in known fashion, which interacts with system control components 1244 (e.g., user interfaces, memory/storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver 1200 will generally include other circuitry, such as bias circuitry 1246 (which may be distributed throughout the transceiver 1200 in proximity to transistor devices), electro-static discharge (ESD) protection circuits, testing circuits (not shown), factory programming interfaces (not shown), etc.
In modern transceivers, there are often more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and/or signaling modalities. Further, as should be apparent to one of ordinary skill in the art, some components of the transceiver 1200 may be positioned in a different order (e.g., filters) or omitted. Other components can be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters/attenuators, power dividers, etc.
As discussed above, the current invention improves better wide-band RF performance than conventional designs. As a person of ordinary skill in the art will understand, a system architecture is beneficially impacted by the current invention in critical ways, including better range, better reception, lower power, longer battery life, and wider bandwidth.
Another aspect of the invention includes methods for improving passive mode negative gain performance in an amplifier, particularly an LNA. For example, a first method of improving passive mode negative gain performance in an amplifier having an amplifier core coupled between an input terminal and an output terminal and having a load network coupled to the output terminal, includes providing a dedicated bypass path that enables propagation of an input radio frequency signal from the input terminal to the output terminal without connecting to the load network. A second method of improving passive mode negative gain performance in an amplifier having an amplifier core coupled to an input terminal through an input inductor, and having an output terminal and a load network coupled to the output terminal, includes providing a dedicated bypass path that enables propagation of an input radio frequency signal from the input terminal to the output terminal while bypassing the input inductor. A third method of improving passive mode negative gain performance in an amplifier having an amplifier core coupled to an input terminal through an input inductor, and having an output terminal and a load network coupled to the output terminal, includes providing a dedicated bypass path that enables propagation of an input radio frequency signal from the input terminal to the output terminal while bypassing the input inductor and/or providing a dedicated bypass path that enables propagation of an input radio frequency signal from the input terminal to the output terminal while bypassing the input inductor. A fourth method of improving passive mode negative gain performance in an amplifier having an amplifier core coupled between an input terminal and an output terminal and having a load inductor coupled to the output terminal, includes disabling the load inductor and enabling propagation of an input radio frequency signal from the input terminal to the output terminal.
While the example embodiments are LNAs, the inventive circuits and methods may also be applied to other types of amplifiers, such as power amplifiers.
It should be appreciated that the inventive architecture provides a great deal of flexibility in setting amplifier circuit component values and component states in order to achieve a variety of performance goals. For example, it may be that noise factor and input impedance matching in a maximum gain mode are to be emphasized. In other cases, it may be that linearity (IIP3) in a maximum gain mode is to be emphasized. In addition, appropriate bias levels for the amplification core 202 may be selected to ensure that the input impedance matching meets required specifications for a maximum gain mode.
Additional well-known circuit elements that might be included in some applications, such as bypass and/or DC blocking capacitors, are omitted for clarity.
The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar junction transistor (BJT), BICMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.
It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
