I. Field of the Disclosure
The technology of the disclosure relates generally to communications interfaces for integrated circuit (IC) chip to IC chip communications.
II. Background
Electronic devices have proliferated throughout society supporting a wide range of applications and uses. As the number and variety of devices expands, there is an increasing desire for electronic devices to communicate with one another. Likewise, there is a growing desire to increase the speed with which components within a single device communicate with one another to increase throughput. In response to the desire to increase speed, various techniques and protocols have been proposed and adopted.
The MIPI® Alliance is one of the leaders in developing communication protocols for use by various devices. In particular, from September 2008 to January 2009, the MIPI® Alliance approved and published a physical layer protocol and specification that specifies the physical layer of the High Speed Synchronous Serial Interface (HSI). Version 1.01.00 of this specification is available for download to subscribed MIPI members, but an overview is discussed at www.mipi.org/specifications/high-speed-synchronous-serial-interface-hsi. The MIPI HSI specification outlines a protocol that allows bidirectional, symmetrical chip to chip communications and is particularly well suited for use in mobile semiconductor applications. A particularly contemplated application of the HSI specification is to allow an application die, such as a main processor, to communicate with a cellular die (e.g., a cellular modem) within a mobile terminal. The raw throughput of this specification is limited to about 173 Mbps in each direction. While Long Term Evolution (LTE) Category 3 (CAT3) throughput can be achieved at these data rates, higher LTE categories are not supported. New solutions are desired to allow for increasingly large bandwidth and throughput requirements.
Embodiments disclosed in the detailed description include a multi-lane high speed interface for a modified High Speed Synchronous Serial Interface (HSI) system and methods. By modifying the HSI interface to include plural parallel data paths, data throughput is improved to accommodate the higher data rates. In this regard in one embodiment, an electronic device configured to operate using a modified High Speed Synchronous Serial Interface (HSI) protocol, comprises a transmit communications interface. The transmit communications interface comprises a HSI protocol data path configured to carry data from the electronic device, a HSI protocol ready path configured to carry an HSI protocol compliant READY signal, and a flag path configured to carry a FLAG signal. The transmit communications interface further comprises one or more additional data paths configured to carry additional data in parallel with the data carried by the HSI protocol data path, such that the HSI protocol data path and the one or more additional data paths carry HSI protocol compliant data striped across the HSI protocol data path and the one or more additional data paths.
In another embodiment, an electronic device configured to operate using a modified High Speed Synchronous Serial Interface (HSI) protocol, comprises a transmit communications interface. The transmit communications interface comprises means for providing a data path configured to carry data from the electronic device, means for providing a ready path configured to carry an HSI protocol compliant READY signal, and means for providing a flag path configured to carry a FLAG signal The transmit communications interface further comprises means for providing one or more additional data paths configured to carry additional data from the electronic device in parallel with the data carried by the means for providing a data path, such that the means for providing a data path and means for providing the one or more additional data paths carry HSI protocol compliant data striped across the data path and the one or more additional data paths.
In another embodiment, a method for operating a modified High Speed Synchronous Serial Interface (HSI) protocol device, comprises providing a ready path configured to carry an HSI protocol compliant READY signal, providing a flag path configured to carry FLAG signal, and providing at least two transmit data paths configured to carry data from an electronic device in parallel such that HSI protocol compliant data is striped across the at least two data paths.
With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
Embodiments disclosed in the detailed description include a multi-lane high speed interface for a modified High Speed Synchronous Serial Interface (HSI) system and methods. By modifying a HSI interface to include plural parallel data paths, data throughput is improved to accommodate higher data rates. In this regard in one embodiment, an electronic device configured to operate using a modified High Speed Synchronous Serial Interface (HSI) protocol, comprises a transmit communications interface. The transmit communications interface comprises a data path configured to carry data from the electronic device, a ready path configured to carry an HSI protocol compliant READY signal, and a flag path configured to carry an FLAG signal. The transmit communications interface further comprises one or more additional data paths configured to carry additional data from the electronic device in parallel with the data carried by the data path such that the data path and the one or more additional data paths carry HSI protocol compliant data striped across the data path and the one or more additional data paths.
In this regard,
With reference to
While the signals on the WAKE, DATA, FLAG, and READY (both AC and CA) paths are defined by the MIPI® HSI protocol,
In the MIPI® HSI protocol, the signal on the DATA path 72 may be broken into frames or streamed. An exemplary conventional framed DATA signal 73 is illustrated in
Against this backdrop, the present disclosure proposes increasing throughput by adding parallel data paths or lanes and striping the data of the original HSI standard across the data lanes. The number of additional data lanes added will determine the throughput that may be achieved. Adding one, three, or seven additional lanes are exemplary additions and the latter allows for even the highest currently contemplated throughput requirements to be accommodated.
In this regard, a system 82 according to an exemplary embodiment of the present disclosure is provided with reference to
With continuing reference to
With continuing reference to
With continuing reference to
In contrast to the framed data signal 73 of
Similarly, in
Similarly, in
With continued reference to
The addition of data lanes requires the addition of pins to the electronic devices 84, 86. The number of pins added directly corresponds to the number of lanes added. An exemplary chart 160 is provided in
Note that the addition of the additional data lanes may also necessitate defining a query and response from the application die 84 to the cellular modem die 86 wherein the application die 84 queries the cellular modem die 86 initially on just the DATA0 path as to the capabilities of the cellular modem die 86 (i.e., how many data paths can the cellular modem die 86 handle transmitting and receiving) and then instructing the cellular modem die 86 to operate on a number of transmit and receive data paths compatible with the number of data paths that the application die 84 can accommodate. For example, if the application die 84 can transmit on four data paths and receive on two data paths, but the cellular modem die 86 can transmit on eight data paths and receive on eight data paths, then the application die 84 may instruct the cellular modem die to transmit on two data paths and receive on four data paths so that the maximum throughput can be achieved.
The multi-lane high speed interface for HSI and related systems and methods, according to embodiments disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
In this regard,
Other master and slave devices can be connected to the system bus 180. As illustrated in
The CPU 172 may also be configured to access the display controller(s) 190 over the system bus 180 to control information sent to one or more displays 194. The display controller(s) 190 sends information to the display(s) 194 to be displayed via one or more video processors 198, which process the information to be displayed into a format suitable for the display(s) 194. The display(s) 194 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
The CPU(s) 172 and the display controller(s) 190 may act as master devices to make memory access requests over the system bus 180. Different threads within the CPU(s) 172 and the display controller(s) 190 may make requests. The CPU(s) 172 and the display controller(s) 190 may provide the MID over the bus, as previously described, as part of a bus transaction request.
Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The arbiters, master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a DSP, an Application Specific Integrated Circuit (ASIC), an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The embodiments disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.