The invention relates to flash memory devices, more particularly to systems and methods of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device.
As flash memory technology becomes more advanced, flash memory is replacing traditional magnetic disks as storage media for mobile systems. Flash memory has significant advantages over floppy disks or magnetic hard disks such as having high-G resistance and low power dissipation. Because of the smaller physical size of flash memory, they are also more conducive to mobile systems. Accordingly, the flash memory trend has been growing because of its compatibility with mobile systems and low-power feature. However, advances in flash technology have created a greater variety of flash memory device types that vary for reasons of performance, cost and capacity. As such, a problem arises when mobile systems that are designed for one type of flash memory are constructed using another, incompatible type of flash memory.
New generation personal computer (PC) card technologies have been developed that combine flash memory with architecture that is compatible with the Universal Serial Bus (USB) standard. This has further fueled the flash memory trend because the USB standard is easy to implement and is popular with PC users. In addition, flash memory is replacing floppy disks because flash memory provides higher storage capacity and faster access speeds than floppy drives.
In addition to the limitations introduced by the USB standard, there are inherent limitations with flash memory. First, flash memory sectors that have already been programmed must be erased before being reprogrammed. Also, flash memory sectors have a limited life span; i.e., they can be erased only a limited number of times before failure. Accordingly, flash memory access is slow due to the erase-before-write nature and ongoing erasing will damage the flash memory sectors over time.
To address the speed problems with USB-standard flash memory, hardware and firmware utilize existing small computer systems interface (SCSI) protocols so that flash memory can function as mass-storage devices similarly to magnetic hard disks. SCSI protocols have been used in USB-standard mass-storage devices long before flash memory devices have been widely adopted as storage media. Accordingly, the USB standard has incorporated traditional SCSI protocols to manage flash memory.
As the demands for larger capacity storage increase, the flash memory device needs to keep up. Instead of using single-level cell flash memory, which stores one-bit of information per cell, multi-level cell (MLC) flash memory is used. The MLC flash memory allows at least two bits per cell. However, there are a number of problems associated with the MLC flash memory. First, the MLC flash memory has a low reliability. Secondly, the MLC flash memory data programming rules require writing to an ascending page in the same block or writing to a blank new page if there are data existed in the original page. Finally, a larger capacity requires a large logical-to-physical address look up table. In the prior art approach, the size look up table is in direct portion with the capacity of the flash memory. This creates a huge problem not only to the cost, but also to the physical size of the flash memory device. Furthermore, the traditional usage of the flash memory devices is generally in a very clean and relatively mild environment, thus the packaging design such as enclosure of the flash memory device is not suitable for hostile environment such as military and heavy industrial applications.
Therefore, it would be desirable to have improved methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) flash memory device.
Briefly, a dual-personality extended External Serial Advanced Technology Attachment (eSATA) flash drive is disclosed to include a dual-personality extended eSATA plug connector. The flash memory device with MLC compatible is being removably connectable to a host thru a dual-personality extended eSATA receptacle connector. Both plug and receptacle connectors have SATA interface with 7 standard pins along with the extended USB interface with 4 standard pins.
In an alternative embodiment, the MLC flash memory device that is used with a USB connector could be replaced with eSATA connector which has more pins, for example 7 instead of 4 as a USB connector.
These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiments illustrated in the several figures of the drawing.
These and other features, aspects, and advantages of the present invention will be better understood with regard to the following description, appended claims, and accompanying drawings as follows:
a)-8(z) collectively show various perspective views and exploded perspective views of exemplary flash memory devices in accordance with several embodiments of the present invention.
In the following description, numerous details are set forth to provide a more thorough explanation of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present invention.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Used herein, the terms “upper”, “lower”, “top”, “bottom”, “front”, “back”, “rear”, “side”, “middle”, “upwards”, and “downwards” are intended to provide relative positions for the purposes of description, and are not intended to designate an absolute frame of reference. Further, the order of blocks in process flowcharts or diagrams representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention.
Embodiments of the present invention are discussed herein with reference to
The card body is configured for providing electrical and mechanical connection for the processing unit, the flash memory module, the I/O interface circuit, and all of the optional components. The card body may comprise a printed circuit board (PCB) or an equivalent substrate such that all of the components as integrated circuits may be mounted thereon. The substrate may be manufactured using surface mount technology (SMT) or chip on board (COB) technology.
The processing unit and the I/O interface circuit are collectively configured to provide various control functions (e.g., data read, write and erase transactions) of the flash memory module. The processing unit may also be a standalone microprocessor or microcontroller, for example, an 8051, 8052, or 80286 Intel® microprocessor, or ARM®, MIPS® or other equivalent digital signal processor. The processing unit and the I/O interface circuit may be made in a single integrated circuit, for application specific integrated circuit (ASIC).
The at least one flash memory module may comprise one or more flash memory chips or integrated circuits. The flash memory chips may be single-level cell (SLC) or multi-level cell (MLC) based. In SLC flash memory, each cell holds one bit of information, while more than one bit (e.g., 2, 4 or more bits) are stored in a MLC flash memory cell. A detail data structure of an exemplary flash memory is described and shown in
The fingerprint sensor is mounted on the card body, and is adapted to scan a fingerprint of a user of the first electronic flash memory device to generate fingerprint scan data. Details of the fingerprint sensor are shown and described in a co-inventor's U.S. patent application Ser. No. 12/099,421, entitled “Flash Memory Devices with Security Features” filed on Apr. 8, 2008, the entire content of which is incorporated herein by reference.
The flash memory module stores, in a known manner therein, one or more data files, a reference password, and the fingerprint reference data obtained by scanning a fingerprint of one or more authorized users of the first flash memory device. Only authorized users can access the stored data files. The data file can be a picture file, a text file or any other file. Since the electronic data storage compares fingerprint scan data obtained by scanning a fingerprint of a user of the device with the fingerprint reference data in the memory device to verify if the user is the assigned user, the electronic data storage can only be used by the assigned user so as to reduce the risks involved when the electronic data storage is stolen or misplaced.
The input/output interface circuit is mounted on the card body, and can be activated so as to establish communication with the host computing motherboard by way of an appropriate socket via an interface bus. The input/output interface circuit may include circuits and control logic associated with an External Serial Advanced Technology Attachment (eSATA) interface structure that is connectable to an associated socket connected to or mounted on the host computing motherboard.
The processing unit is controlled by a software program module (e.g., a firmware (FW)), which may be stored partially in a ROM (not shown) such that processing unit is operable selectively in: (1) a data programming or write mode, where the processing unit activates the input/output interface circuit to receive data from the host computing motherboard and/or the fingerprint reference data from fingerprint sensor under the control of the host computing motherboard, and store the data and/or the fingerprint reference data in the flash memory module; (2) a data retrieving or read mode, where the processing unit activates the input/output interface circuit to transmit data stored in the flash memory module to the host computing motherboard; or (3) a data resetting or erasing mode, where data in stale data blocks are erased or reset from the flash memory module. In operation, host computing motherboard sends write and read data transfer requests to the first flash memory device via the interface bus, then the input/output interface circuit to the processing unit, which in turn utilizes a flash memory controller (not shown or embedded in the processing unit) to read from or write to the associated at least one flash memory module. In one embodiment, for further security protection, the processing unit automatically initiates an operation of the data resetting mode upon detecting a predefined time period has elapsed since the last authorized access of the data stored in the flash memory module.
The optional power source is mounted on the card body, and is connected to the processing unit and other associated units on card body for supplying electrical power (to all card functions) thereto. The optional function key set, which is also mounted on the card body, is connected to the processing unit, and is operable so as to initiate operation of processing unit in a selected one of the programming, data retrieving and data resetting modes. The function key set may be operable to provide an input password to the processing unit. The processing unit compares the input password with the reference password stored in the flash memory module, and initiates authorized operation of the first flash memory device upon verifying that the input password corresponds with the reference password. The optional display unit is mounted on the card body, and is connected to and controlled by the processing unit for displaying data exchanged with the host computing motherboard.
A second electronic environment is shown in a second environment in
Shown in
Referring now to
In order to access the data stored in the normal usage blocks 204 of the flash memory module 201, the host computing motherboard 109 transmits a data transaction request (e.g., data read or write) along with a logical sector address (LSA) to the flash memory device (e.g., flash memory device 140 of
To carry out the address partition scheme of the present invention, the manufacturer may predefine number of sets and entries in the first physical block (i.e., PBK#0) by the IMP. Instead of mapping all of the logical sector addresses (LSA) to a physical address in a memory, only a portion of the LSA (i.e., a set) is included such that only a limited size of memory is required for address correlation and page usage information. In other words, a limited size memory is configured to hold one set of entries with each entry including an address of the corresponding physical block and a plurality of corresponding page usage flags (see
However, in order to correlate a logical block address to a unique physical block, every entry in each of the plurality of sets must correlate to a unique physical address and a set of page usage flags. Since the limited size memory only has capacity of holding one set of such information, an embodiment of the present invention requires that information of all of the plurality of sets be stored in reserved area 206 of the flash memory 201. Only a relevant set of the plurality of sets is loaded into the limited size memory in response to a particular data transfer request from a host computing system 109. The relevant set is defined as the set with one of the entries matches the entry number derived from the LSA associated with the received data transfer request.
Since there are N sets of address correlation and page usage information stored in the flash memory, each of the N sets is referred to as a partial logical-to-physical address and page usage information (hereinafter ‘PLTPPUI’) appended with a set number (e.g., ‘PLTPPUI0’, ‘PLTPPUI1’, . . . ‘PLTPPUIN’).
In order to simplify the examples and drawings in the Specification, an example with small numbers is used for demonstrate the relationship between LSA, LBA, sector, page, entry and set numbers. Those of ordinary skill in the art will understand implementation of an embodiment of the present invention can be with larger numbers. The following example uses a flash memory with four sectors per page, four pages per block and four entries per set and a logical sector address 159 (i.e., LSA=159) is represented by a binary number “10 01 11 11”. As a result, the least significant four bits of LSA represent sector and page numbers with the two lowest bits for the sector number and the next two for the page number, as each two-bit represents four distinct choices—0, 1, 2 and 3. After truncating the four least significant bits of LSA, the remaining address becomes the corresponding logical block address (LBA). In this example, LBA has a binary value of ‘1001’. Because there are four entries per set in this example, two least significant bits of LBA represent the entry number (i.e., offset number in each set). The remaining high bits of LBA represent the set number. A summary of this example is listed in Table 1.
According to one aspect of the present invention, an indexing scheme enables the processing unit 102 to translate logical sector addresses (LSAs) and/or logical block addresses (LBAs) provided, in conjunction with a data transfer request, by the host computing motherboard 109 to physical block numbers or addresses (PBK#) in the flash memory device 140. The indexing scheme comprises a plurality of sets of PLTPPUI and physical characteristics of the flash memory such as total number of sets, entries, pages and sectors. And ratios among the set, entry, page and sector. The processing unit 102 can utilize the indexing scheme to determine which sectors of the flash memory are available for each particular data transfer request.
The microcontroller 302 with a flash memory controlling program module 304 (e.g., a firmware (FW)) installed thereon is configured to control the data transfer between the host computing motherboard 109 and the at least one flash memory module 103. The ACPUM 306 is configured to provide an address correlation table, which contains a plurality of entries, each represents a correlation between a partial logical block address (i.e., entries) to the corresponding physical block number. In addition, a set of page usage flags associated with the physical block is also included in each entry. The ACPUM 306 represents only one of the N sets of PLTPPUI, which is stored in the reserved area of the flash memory. In order to keep tracking the physical location (i.e., physical block number) of each of the N sets of PLTPPUI, the physical location is stored in the PLTPPUI tracking table 308. Each item is the PLTPPUI tracking table 308 corresponds a first special logical address to one of the N sets of PLTPPUI. The wear leveling counters and bad block indicator for each physical block is stored in a number of physical blocks referred by corresponding second special logical addresses (e.g., ‘0xFFFFFF00’). The WL/BB tracking table 310 is configured to store physical block numbers that are assigned or allocated for storing these physical block wear leveling counters and bad blocks. The ACPUM modification flag (ACPUMF) 312 is configured to hold an indicator bit that tracks whether the ACPUM 306 has been modified or not. The page buffer 314 is configured to hold data in a data transfer request. The page buffer 314 has a size equaling to the page size of the flash memory 201. The sector update flags 316 are configured to hold valid data flag for each of the corresponding sectors written into data area of the page buffer 314. For example, four sector update flags are be required for a page buffer comprising four sectors. The page buffer 314 also includes a spare area for holding other vital information such as error correction code (ECC) for ensuring data integrity of the flash memory.
Each set of the PLTPPUI is stored in the reserved area 206 of the flash memory 201 of
Similar to the data structure of the PLTPPUI tracking table, an exemplary data structure 450 of a WL/BB tracking table 310 is shown in
Referring now to
The process 500 starts in an ‘IDLE’ state until the microcontroller 302 receives a data transfer request from a host (e.g., the host computing board 109 of
If the decision 504 is ‘no’, the process 500 moves to decision 506. The process 500 checks whether the contents of the page buffer 430 need to be stored. In one implementation, the process 500 checks the sector update flags 432 that correspond to sectors in the page buffer 430. If any one of the flags 432 has been set to ‘valid’, then the contents of the page buffer 430 must be stored to the corresponding page of the corresponding physical block of the MLC flash memory at 550 (i.e., the decision 506 is ‘yes’). Detailed process of step 550 is shown and described in
Otherwise if ‘no’ at decision 506, the process 500 moves the decision 510 directly. It is then determined if the ACPUM 306 has been modified. If ‘yes’, the process 500 moves to 580, in which, the process 500 writes the contents of the ACPUM 306 to one of a plurality of first special logical addresses (e.g., ‘0xFFFF0000’ for PLTPPUI0, or ‘0xFFFF0001’ for PLTPPUI1, etc.) for storing corresponding set of PLTPPUI in the reserved area of the flash memory. The ACPUM modification flag 412 is reset at the end of 580. Detailed process of step 580 is shown and described in
Next, at decision 518, if the data transfer request is a data read request, the process 500 continues with a sub-process 520 shown in
If the data transfer request is a data write or program request, the process 500 continues with a sub-process 530 shown in
If ‘yes’ at decision 532, the process 500 moves to decision 534. It is determined if the received data sector is in the same entry and page numbers. If ‘yes’, the process 500 writes the received data sector to the page buffer 430 at 538 before going to the ‘IDLE’. If ‘no’ at decision 534, the process 500 writes the page buffer contents to the corresponding page of the physical block of the flash memory at 550. Next, the process 500 sets the ACPUM modification flag 412 to a ‘modified’ status at 536. Next, at 538, the process 500 writes the received data sector to the page buffer before going back to the ‘IDLE’ state.
Finally, in additional to managing data read and write requests, the process 500 regularly performs a background physical block recycling process so that the blocks containing only stale data can be reused later. When the process 500 is in the ‘IDLE’ state, it performs test 540, in which it is determined if the idle time has exceeded a predefine time period. If ‘yes’, the process 500 performs the background recycling process, which may include issuing a dummy data write request to force the page buffer 430 and/or modified ACPUM 306 to be written to corresponding locations of the flash memory at 542. In one embodiment, the dummy data write/program command may be issued to rewrite some of seldom touched physical blocks, for example, physical blocks used for storing user application or system program modules.
Referring to
If ‘yes’ at decision 552, the process 500 searches for a blank physical block based on the wear leveling (WL) rule; once found, the process 500 designates it as a new block at 562. Then, the process 500 updates the ACPUM 306 with the new physical block number for the entry number and keeps the page usage flags the same. It is noted that the entry number is derived from the received LSA. Next, at 566, the process 500 copies all valid pages with page number less than the current page number from the old to the new physical block if needed. The current page number if the page number derived from the received LSA. Then, the process 500 writes the valid data sectors based on the sector update flags 432 from the page buffer 430 to the page register of the corresponding page of the new physical block at 568. Finally if necessary, the process 500 copies all valid pages with page number greater than the current page number from the old to the new physical block at 570. The process 500 resets the sector update flags at 558 before returning.
Referring back to decision 584, if ‘yes’, the process 500 searches a blank physical block as a new physical block (e.g., new physical block (PBK#1012) in
The sequence of the data write requests starts with (a) writing to LSA=0, which corresponds to set 0 (i.e., PLTPPUI0), entry 0, page 0 and sector 0. PLTPPUI0 is loaded into ACUPUM 604, in which the first entry (i.e., entry 0) corresponds to physical block ‘PBK#2’ and page usage flags 606 are not set. The ACPUMF 614 is set to a ‘unmodified’ status. The sector data (S0) is written to the first sector of the page buffer 610 and the corresponding flag in the sector update flags 612 is set to a ‘V’ for valid data. The corresponding path in the process 500 for writing LSA=0 is as follows:
The next data write request (b) is to write to LSA=1. The corresponding path is the process 500 is as follows:
The next data write request (c) is to write to LSA=3 (
The next data write request (d) is to write to LSA=9 (
The next data write request (e) is to write to LSA=54 (
Finally, the next data write request (f) is to write to LSA=171 (
Referring now to
Shown in
If ‘yes’ at the decision 716, the process 700 follows the ‘yes’ branch to another decision 718. It is then determined whether the stored tracking number is newer than the one listed in the PLTPPUI tracking table 308. For example, the contents in the PLTPPUI tracking table is initialized to zero, any stored tracking number (TN) greater than zero indicates that the stored records are newer. If ‘no’ at decision 718, the process 700 skips this physical block similar to the ‘no’ branch of decision 716. However, if ‘yes’ at decision 718, the process 700 searches and locates a highest written page in this physical block ‘PBK#’ at 720. Next, at 722, the process 700 writes the ‘PBK#’, TN and highest page number in the PLTPPUI tracking table corresponding to the first special logical address. Finally, the process 700 increments the physical block count ‘PBK#’ by one at 724, then moves to decision 726 to determine either moving back to 714 for processing another physical block or ending the step 710.
Details of step 730 are shown in
Next, at 742, the physical block counter ‘PBK#’ is incremented by one. The process 700 moves to another decision 744, it is determined if there is additional block in the ‘mth’ group. If ‘yes’, the process 700 goes back to step 736 reading another WL counters of another physical block to repeat the above steps until the decision 744 becomes ‘no’. The process 700 updates the stored WL/BB tracking table 310 at 746. At next decision 748, it is determined if there is any more physical block. If ‘yes’, the process 700 increments the group counter at 749 then goes back to 734 for repeating the above steps for another group. Otherwise, the step 730 returns when the decision 748 is ‘no’.
Each entry record of PLTPPUI is 18-byte, which is a sum of 2-byte physical block number plus 128-bit (i.e., 16-byte) of page usage flags (i.e., 128 pages per block). Using 2048-byte page buffer as a scratch memory can only hold a group of 113 entry records. One may use a larger memory such as ACPUM 306 as the scratch memory, which may hold more entry records thereby reducing the initialization time.
a)-8(z) collectively show various perspective views and exploded perspective views of a dual-personality Extended External Serial Advanced Technology Attachment (eSATA) plug connector 800 of a flash memory device, in accordance with several embodiments of the present invention.
The flash memory device of which the plug connector 800 is a part of a flash memory device analogous to the flash memory device of
The plug connector 800 contains a first row of four pins thereby making interface with industry standard USB (extended), and a second row of seven pins thereby making interface with eSATA (standard).
a) shows a perspective view of a dual-personality extended eSATA plug connector 800, in accordance with an exemplary embodiment of the present invention. The plug connector 800 is shown to be a three-dimension rectangle. The plug connector 800 is encapsulated by a top cover 802 and a bottom cover 803 that join together to form housing 801. Disposed on both top cover 802 and bottom cover 803 are metal holes 804. The holes 804 are shown disposed substantially on a side opposite to pins 806 and aligned with respect to each other. A connector substrate 810 is disposed inside of the connector 800. Disposed substantially on each of the vertical sides of substrate 810 are side tracks 809. Side tracks 809 serve to align the plug connector 800 securely within the dual-personality extended eSATA receptacle connector 880. The substrate has connected thereto the pins 806 for establishing electrical connection between the connector 800 and the printed circuit board (PCB). The connector 800 is in conformance with the industry-adopted eSATA standard.
b) shows a front perspective view of connector substrate 810. The substrate 810 is shown to include connector substrate front end 815, connector substrate back end 814, receptacle cavity 811, receptacle cavity top surface 812, receptacle cavity bottom surface 813, contact fingers 805 and side tracks 809. Not shown in
c) shows a back perspective view of connector substrate 810. The substrate 810 is shown to include substrate front end 815, substrate back end 814, side tracks 809, pins 806, first row pins 807 and second row pins 808. Not shown in
d) shows a side perspective of connector substrate 810. Substrate 810 is shown to include substrate front end 815, substrate back end 814, side tracks 809, and pins 806. Substrate 810 is shown bisected by a center line.
e) shows a section view of connector substrate 810 above the center line. This view shows only the USB compliant contact fingers and pins. Substrate 810 is shown to include receptacle cavity top surface 812, first row pins 807, and USB contact fingers 817. USB contact fingers 817 contain 4 individual contact fingers, which are disposed on receptacle cavity top surface 812. The USB contact fingers 817 and SATA contact fingers 818 are situated relative to one another in a manner so that their individual contact fingers are spaced apart in an interleaved fashion thereby allowing the rows to make electrical contact with a mating connector of a host to which electrical contact is intended.
f) shows a section view of connector substrate 810 below the center line. This view shows only the SATA compliant contact fingers and pins. Substrate 810 is shown to include receptacle cavity bottom surface 813, second row pins 808, and SATA contact fingers 818. SATA contact fingers 818 contain 7 individual contact fingers, which are disposed on receptacle cavity bottom surface 813.
Referring to
In an exemplary application, a special design for industrial and military application on the finished assembly of the flash drive 834 includes a conforming coating to achieve the purposes of preventing oxidation of integrated circuit leads or soldering area; covering or protecting extreme temperature exposure either cold or hot; and waterproofing for certain military or industrial applications. The procedure of applying the conforming coating to the flash memory device includes: 1) placing a masking cap or tape on specific area(s) such as connectors, switches; 2) spraying or brushing the conforming coating material (e.g., HumiSeal® 1B73); and 3) inspecting the coated area with ultraviolet (UV) lights for imperfection (e.g., bubbles, missed coating area).
PCBA 836 is generally used for mechanically supporting and electrically connecting electronic components using conductive pathways, or traces, etched from copper sheets laminated onto a non-conductive substrate. The core unit is also referred to as a print circuit board assembly (PCBA).
h) shows a perspective top view of the flash drive 834 including the connector 800, MLC controller IC 840, PCB 836, and first row pins 807. The MLC controller IC 840 are shown mounted on a PCBA top surface 846. The first row pins 807 of the connector 800 are shown physically connected to the PCBA top surface 846 causing electrical coupling of the connector 800 to the PCBA 836.
i) shows a perspective bottom view of the flash drive 834. The MLC memory IC 838 is shown mounted on a PCBA bottom surface 844 of the flash drive 834. The second row pins 808 of the connector 800 are shown physically connected to the PCBA bottom surface 844 causing electrical coupling of the connector 800 to the PCBA 836.
j) through 8(m) show various perspective views of an extended dual-personality eSATA flash drive 852, in accordance with another embodiment of the present invention.
Fig. (k) shows a perspective top view of the flash drive 852. The COB 854 is mounted onto a PCBA top surface 856 of a PCBA 858, which is analogous to the PCBA 836. The COB 854's bottom surface has COB contact fingers 859, which are soldered to PCB top surface 856. The COB contact fingers 859 comprise the first row COB contact fingers 860 and the second row COB contact fingers 862. Two different COB contact finger configurations are formed onto the COB 854. In one embodiment, shown in FIG. (1), a standard configuration includes a first row COB contact fingers 860. In another embodiment, a second row COB contact fingers 822 is used in combination with the first row, as shown in
Referring now to
Referring to
p) shows an exploded view of flash drive 851. Flash drive 851 is shown to include upper housing 825, PCBA 836, and bottom housing 826. Upper housing 825 is shown to include connector cut-out 845 and upper snap coupling tabs 847. Tabs 847 are disposed on the lateral sides of upper housing 825. Upper snap coupling tabs 847 are shown to be arranged in a rectangular saw-toothed pattern. The saw-toothed pattern as shown on upper snap coupling tabs 847 is complementary with those of lower snap coupling slots 848. Complementary, as defined herein, indicates a repeating pattern of rectangular blocks and gaps which fit generally snugly together when pressed against its corresponding partner repeating pattern. Similarly, bottom housing 826 is shown to include connector cut-out 845 and lower snap coupling slots 848. Slots 848 are disposed upon the lateral sides of lower housing 826. PCBA 836 is shown to include connector 800 and MLC controller IC 840. Not shown in
q) shows press/push flash drive 849 in accordance with an embodiment of the present invention. Flash drive 849 is comprised of connector 800, upper housing 825, lower housing 826, slide button 861, and slide button opening 863. In
r) shows an exploded perspective of flash drive 849. Flash drive 849 is comprised of upper housing 825, core unit carrier 846, PCBA 836, and lower housing 826. Upper housing 825 is shown to include slide button opening 863 and connector cut-out 845. Core unit carrier 846 is shown to include slide button 861 and lock tab 865. Lock tab 865 works in concert with lock grooves 868 (not shown in
The upper housing 825 and bottom housing 826 may be attached to each other via variety of method, including using a snap-together mechanism or ultrasonic welding around edges of upper housing 825 and bottom housing 826. The plug connector 800 is coupled to the PCBA 836 electrically and physically such that control signals and power can pass through. U.S. patent Application Ser. No. 11/845,747, Filed Aug. 27, 2007 entitled: “PRESS/PUSH USB FLASH DRIVE WITH DEPLOYING AND RETRACTING FUNCTIONALITIES WITH ELASTICITY MATERIAL AND FINGERPRINT VERIFICATION CAPABILITY” offers greater details regarding the press/push flash drive 849.
s) shows a perspective view of press/push flash drive 866 in accordance with yet another embodiment of the present invention. Flash drive 866 is shown to include connector 800, upper housing 825, lower housing 826, slide button 861, and slide button opening 863. In
t) shows an exploded perspective of flash drive 866. Flash drive 866 is comprised of upper housing 825, core unit carrier 846, PCBA 836, and lower housing 826. Upper housing 825 is shown to include slide button cut-out 867 and connector cut-out 845. Core unit carrier 846 is shown to include slide button 861 and lock tab 865. Lock tab 865 works in concert with lock grooves 868 (disposed on lower housing 826 and upper housing 825 (not shown)) to lock the plug connector 800 at deployed and retracted positions. The core unit carrier 846 fits substantially securely underneath upper housing 825, positioned such that slide button 861 is exposed between the slide button cut-outs 867. PCBA 836 is shown to include connector 800 and MLC controller IC 840. Not shown in
The upper housing 825 and bottom housing 826 may be attached to each other via variety of method, including using a snap-together mechanism or ultrasonic welding around edges of upper housing 825 and bottom housing 826. The plug connector 800 is coupled to the PCBA 836 electrically and physically such that control signals and power can pass through. U.S. patent application Ser. No. 11/845,747, Filed Aug. 27, 2007 entitled: “PRESS/PUSH USB FLASH DRIVE WITH DEPLOYING AND RETRACTING FUNCTIONALITIES WITH ELASTICITY MATERIAL AND FINGERPRINT VERIFICATION CAPABILITY” offers greater details regarding the press/push flash drive 866.
The deploying and retracting the USB plug connector out of and into the housing plus the locking mechanism between the lock tabs (core unit carrier) and the lock grooves (housing) are described in details in a co-pending of U.S. patent application Ser. No. 11/845,747, filed Aug. 27, 2007.
u) shows a side perspective view of locking swivel cap flash drive 870. Flash drive 870 is shown to include upper housing 825, bottom housing 826, and swivel cap 869. The swivel cap 869 rotates around the flash drive, and locks in an open position at substantially 180 degrees, and locks in a closed position at substantially 0 degrees.
v) shows an exploded view of locking swivel cap flash drive 870. Flash drive 870 is shown to include upper housing 825, PCBA 836, bottom housing 826, and swivel cap 869. Top housing 825 is comprised of lock holes 873, pivot hole 874, connector cut-out 845, and upper snap coupling tabs 847. The pivot hole houses the pivot pin 872 when the swivel cap 869 is joined with the flash drive unit 875, comprising of the PCBA 836 covered with upper housing 825 and bottom housing 826. The PCBA 836 is shown to include connector 800 and MLC memory IC 838. Not shown in
Swivel cap 869 is shown to include pivot pin 872 and lock pins 871. The swivel cap 869 rotates around the pivot pin 872. The lock pins 871 rotate within the swivel cap 869, where the lock pins 871 lock into the lock holes 873 and the at both a substantially 180 degree (“open position”) and substantially 0 degree (“closed position”). That is, the lock pins 871 snap into the holes 873 when the swivel cap 869 is rotated, and serve to lock the USB flash drive 870 in the open or closed position. When the USB flash drive 870 is locked in the closed position, the connector 800 and PCBA 836 is fully enclosed within the swivel cap 869 to protect the flash drive 870 from physical damage. When the flash drive 870 is locked in the open position, the connector 800 is fully exposed for operation. In ordinary use, flash drive unit, comprising of the PCBA 836 covered with upper housing 825 and bottom housing 826, and swivel cap 869 are permanently attached to each other, preventing the swivel cap 869 from being misplaced. U.S. patent application Ser. No. 11/929,857 filed Oct. 30, 2007 entitled: “UNIVERSAL SERIAL BUS (USB) FLASH DRIVE HAVING LOCKING PINS AND LOCKING GROOVES FOR LOCKING SWIVEL CAP” offers greater detail regarding the swivel cap flash drive.
w) shows a side perspective view of the dual-personality extended eSATA receptacle connector 880. Receptacle connector 880 is shown to be comprised of metal cover 881 and connector substrate 882. Metal cover 881 is shown to be a three-dimension rectangle. Metal cover 881 substantially encloses the four sides of the connector substrate 882 while leaving the contact fingers 883 of substrate 882 accessible for interfacing with plugs. Receptacle connector 880 can advantageously interface with the dual-personality extended eSATA plug connector of
x)(i) shows a top view of connector substrate 882. Connector substrate 882 is shown to include USB contact fingers 876 and center island top surface 877. USB contact fingers 876 include 4 individual contact fingers, in conformity with the USB standard. The USB contact fingers 876 are disposed along the center island top surface 877.
x)(ii) shows a side view of connector substrate 882. Connector substrate 882 is shown to include substrate front end 878, substrate back end 879, and first row pins 885, and back row pins 886 (not shown).
x)(iii) shows a bottom view of connector substrate 882. Connector substrate 882 is shown to include SATA contact fingers 888 and center island bottom surface 887. SATA contact fingers 888 include 7 individual contact fingers, in conformity with the SATA standard. The SATA contact fingers 888 are disposed along the center island bottom surface 887. When a USB or SATA connector is plugged into the dual-personality extended eSATA receptacle connector 880, no selection mechanism need be used to select a particular type of available connection, i.e. USB or SATA. If USB is present, then no electrical connection will be made with the SATA contact fingers 888. If SATA is present, no electrical connection will be made with the USB contact fingers 876.
y)(i) shows a top side perspective view of connector substrate 882. Connector substrate 882 is shown to include center island top surface 877 and center island 889. Disposed on center island top surface are USB contact fingers 876.
y)(ii) shows a bottom side perspective view of connector substrate 882. Connector substrate 882 is shown to include center island bottom surface 887, center island 889, first row pins 885, and back row pins 886. The center island 889 is operative to slide into the receptacle cavity of the connector 800 when the plug and receptacle are interfaced with each other. The back end of the connector substrate 879 has 2 rows of pins for PCB interface. The first row pins 885 have 4 pins in conformity with the USB standard, and the back row pins 886 has 7 pins in conformity with the SATA standard.
z) shows a side view and a top perspective view of receptacle connector 880 attached to mother board PCBA 890. Inside the chassis of the host system, a cable assembly with one end with a receptacle connector and one end with a plug connector is operative to establish a communication link between the flash memory device and the motherboard. One end of the cable with the receptacle connector is mounted and exposed through the host system's chassis and connected to the plug connector 800 and the other end of the cable with a plug connector is coupled with the motherboard PCBA 890 with the receptacle connector 880 as shown in
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Embodiments of the present invention also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable medium. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.)), etc.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method operations. The required structure for a variety of these systems will appear from the description below. In addition, embodiments of the present invention are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of embodiments of the invention as described herein.
Although the present invention has been described with reference to specific embodiments thereof, these embodiments are merely illustrative, and not restrictive of, the present invention. Various modifications or changes to the specifically disclosed exemplary embodiments will be suggested to persons skilled in the art. For example, whereas the size of the data area of a page has been shown to hold four sectors of 512-data, a page holds other number of sectors such as eight may be used. In summary, the scope of the invention should not be restricted to the specific exemplary embodiments disclosed herein, and all modifications that are readily suggested to those of ordinary skill in the art should be included within the spirit and purview of this application and scope of the appended claims.
This application is a continuation-in-part (CIP) of co-pending U.S. patent application for “Flash Memory Devices with Security Features”, Ser. No. 12/099,421, filed Apr. 8, 2008 which is a continuation-in-part (CIP) of co-pending U.S. patent application for “Methods and Systems of Managing Memory Addresses in a Large Capacity Multi-Level Cell (MLC) based flash memory device”, Ser. No. 12/025,706, filed Feb. 4, 2008. This application is also a CIP of U.S. patent application for “Electronic data Flash Card with Various Flash Memory Cells”, Ser No. 11/864,671, filed Sep. 28, 2007 and U.S. patent application for “System and Method for Controlling Flash Memory”, Ser. No. 10/789,333, filed Feb. 26, 2004. This application is also a continuation-in-part (CIP) of co-pending U.S. patent application for “Data security for Electronic Data Flash Card”, Ser. No. 11/685,143, filed on Mar. 12, 2007, which is a CIP of U.S. patent application for “System and Method for Providing Security to a Portable Storage Device”, Ser. No. 11/377,235, filed on Mar. 15, 2006. This application is also a CIP of co-pending U.S. patent application for “Backward Compatible Extended USB Plug and Receptacle with Dual Personality”, Ser. No. 11/864,696, filed Sep. 28, 2007, which is a CIP of U.S. patent application for “Electronic Data Storage Medium with Fingerprint Verification Capability”, Ser. No. 11/624,667, filed Jan. 18, 2007, which is a divisional application of U.S. patent application Ser. No. 09/478,720, filed Jan. 6, 2000, now U.S. Pat. No. 7,257,714 issued on Aug. 14, 2007, which has been petitioned to claim the benefit of CIP status of one of inventor's earlier U.S. patent application for “Integrated Circuit Card with Fingerprint Verification Capability”, Ser. No. 09/366,976, filed on Aug. 4, 1999, now issued as U.S. Pat. No. 6,547,130. This application is also a CIP of U.S. patent application for “Extended Secure-Digital (SD) Devices and Hosts”, Ser No. 10/854,004, filed May 25, 2004, which is a CIP of U.S. patent application for “Dual-Personality Extended USB Plug and Receptacle with PCI-Express or Serial-At-Attachment extensions, Ser. No. 10/708,172, filed Feb. 12, 2004, now issued as U.S. Pat. No. 7,021,971. This application is also a CIP of co-pending U.S. patent application for “Extended USB Plug, USB PCBA, and USB Flash Drive with Dual-Personality”, Ser. No. 11/866,927, filed Oct. 3, 2007, and U.S. patent application for “Press/Push USB Flash Drive with Deploying and Retracting Functionalities with Elasticity Material and Fingerprint Verification Capability”, Ser. No. 11/845,747, filed Aug. 27, 2007, and U.S. patent application for “Universal Serial Bus (USB) Flash Drive having Locking Pins and Locking Grooves for Locking Swivel Cap”, Ser. No. 11/929,857, filed Oct. 30, 2007.
Number | Date | Country | |
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Parent | 09478720 | Jan 2000 | US |
Child | 11624667 | US |
Number | Date | Country | |
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Parent | 12099421 | Apr 2008 | US |
Child | 12113023 | US | |
Parent | 11076514 | Mar 2005 | US |
Child | 12099421 | US | |
Parent | 10854004 | May 2004 | US |
Child | 11076514 | US | |
Parent | 10708172 | Feb 2004 | US |
Child | 10854004 | US | |
Parent | 11866927 | Oct 2007 | US |
Child | 10708172 | US | |
Parent | 11845747 | Aug 2007 | US |
Child | 11866927 | US | |
Parent | 11929857 | Oct 2007 | US |
Child | 11845747 | US | |
Parent | 11864696 | Sep 2007 | US |
Child | 11929857 | US | |
Parent | 11624667 | Jan 2007 | US |
Child | 11864696 | US | |
Parent | 09366976 | Aug 1999 | US |
Child | 09478720 | US |