Patent Application
20160285439
I. Field of the Disclosure
The technology of the disclosure relates generally to flip-flop circuits used in integrated circuits (ICs), and particularly to flip-flop circuits used in multi-power domain ICs.
II. Background
Processor-based systems have become commonplace throughout society due, in part, to their increasing functionality and versatility. This increase in functionality and versatility has been enabled by providing increasingly powerful processing capabilities in small packages as loosely recognized by Moore's Law. These systems require access to a power supply that provides voltage for powering operations. Some of these systems may be mobile and/or portable, and thus, may be powered through a limited power source, such as a battery. Therefore, reducing power consumption while keeping a high level of performance is of great interest.
Lower power consumption may be achieved in a processor-based system if the voltage level of the power supply providing power to the processor-based system is reduced. However, performance of the processor-based system may become degraded if the voltage level is reduced, because particular components of the processor-based system may need to operate at a higher voltage level to perform at a desired level of performance. For example, it may be desired for sequential logic circuits that are clocked by a clock signal, such as a flip-flop, to operate using a higher voltage level to maintain a higher level of performance. However, combinational logic circuits (e.g., gates) that are not clocked by the clock signal provide a better energy/performance trade off under a lower voltage level. That is, a combinational logic circuit may provide an acceptable level of performance using a lower operating voltage, and thus, less energy. In this regard, rather than providing a single higher voltage level for all components, a processor-based system can be configured to operate in multiple voltage domains, with each voltage domain operating at its own particular voltage level. Components that can operate at a lower voltage level can be powered in the lower voltage domain, which is powered by a lower voltage supply level. Components that require a higher voltage level for performance, or other reasons, can be powered in the higher voltage domain, which is powered by a higher voltage supply level. In this manner, power is conserved by the components that can operate in the lower voltage domain, as opposed to all components operating in the higher voltage domain. Such processor-based systems are generally referred to as multi-power domain integrated circuits (ICs).
For example, in particular multi-power domain ICs, to exploit a multi-power domain design in combination with a deep pipeline strategy for an optimal power performance and area (PPA) envelope, flip-flops may be designed to operate in the higher voltage domain to minimize insertion loss and increase throughput. Insertion loss is the delay from an input to an output transition of a flip-flop. However, to provide for combinational logic to operate in a lower voltage domain, voltage level shifters are employed to shift input signals from combinational logic in a lower voltage domain to a higher voltage domain to be provided as input signals to the flip-flop. For example, voltage level shifters are employed to shift an input signal in a lower voltage domain level (e.g., logic high=˜0.5 Vdd) to a higher voltage domain level (e.g., logic high=˜1.0 Vdd). The higher voltage domain signal is input as a data signal into the flip-flop operating in the higher voltage domain. Further, voltage level shifters are provided to shift output signals from the flip-flop from a higher voltage domain to a lower voltage domain before such signals reach combinational logic. However, these voltage level shifters consume area and power, and decrease throughput.
Aspects disclosed in the detailed description include multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs). Related methods are also disclosed. In this regard, a multi-level conversion flip-flop circuit is provided that is configured to latch a representation of a received input data signal in a lower voltage domain in a latch circuit in a higher voltage domain. In this manner, the multi-level conversion flip-flop operates in the higher voltage domain to minimize insertion loss/delay, thereby increasing performance, without the need to provide separate voltage level shifters to shift the input data signal from the lower voltage domain to the higher voltage domain. Furthermore, combinational logic can operate at a lower voltage level to reduce power consumption. Further still, area and power may be conserved as a result of eliminating the separate voltage level shifters at input and output stages of the flip-flop.
In this regard, in certain aspects disclosed herein, to allow a representation of the input data signal in the lower voltage domain to be latched in a latch circuit in the higher voltage domain, the multi-level conversion flip-flop circuits employ gate-controlled, control transistors. The gate-controlled, control transistors control activation of the latch circuit operating in the higher voltage domain. The gate-controlled, control transistors include a clock control transistor, gated by a clock signal, coupled to a data control transistor, gated by the input data signal. By coupling the input data signal to the gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the gate-controlled, control transistors are configured to activate or control the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to the clock signal. This allows for a level shift from the lower voltage domain to the higher voltage domain to occur within the multi-level conversion flip-flop circuits without the need to provide a separate voltage level shifter to voltage level shift the input data signal into the higher voltage domain before being input into the multi-level conversion flip-flop circuit.
Further, providing a gate-controlled data transistor in the multi-level conversion flip-flop circuits can provide other non-limiting benefits. For example, because the latch circuit is activated by the data control transistor, the latch circuit is not activated unless there is a state change in the input data signal. This reduces dynamic power, thereby reducing power consumption and contributing to the circuit's stability, as opposed to the latch circuit latching the input data signal every clock cycle even if the input data signal level has not changed. Also, providing the data control transistor can avoid or reduce voltage drift of the input data signal. This is as opposed to a drain/source connection in a pass/transmission transistor configuration that propagates the input data signal through the pass/transmission transistor's channel. Avoiding voltage drift can provide for more stable operation of multi-level conversion flip-flop circuits than when using a pass/transmission transistor.
In this regard, in one aspect, a flip-flop circuit is provided. The flip-flop circuit comprises an input stage in a lower voltage domain. The input stage is configured to receive an input data signal on a data input in the lower voltage domain and a clock signal on a clock input. The flip-flop circuit also comprises a master stage in a higher voltage domain than the lower voltage domain. The master stage comprises a control circuit. The control circuit comprises a clock control transistor including a gate electrode configured to receive the clock signal, a first current electrode, and a second current electrode coupled to a first current electrode of a data control transistor. The data control transistor comprises a gate electrode coupled to the data input to receive the input data signal, the first current electrode coupled to the second current electrode of the clock control transistor, and a second current electrode. The control circuit is configured to generate a control signal based on an activation of the clock control transistor by the clock signal and the data control transistor by the input data signal.
The master stage further comprises a latch circuit. The latch circuit comprises a first latch node coupled to the control circuit to receive the control signal. The latch circuit is configured to store a latched voltage as a first latched input data in the higher voltage domain, based on the input data signal in response to the control signal from the control circuit. The flip-flop circuit further comprises a slave stage in the higher voltage domain. The slave stage is configured to receive the first latched input data from the master stage and latch the first latched input data as a second latched output data. The flip-flop circuit further comprises an output stage. The output stage is configured to provide the second latched output data as a flip-flop output.
In another aspect, a flip-flop circuit is provided. The flip-flop circuit comprises a means for receiving an input data signal on a data input in a lower voltage domain. The flip-flop circuit further comprises a means for receiving a clock signal on a clock input. The flip-flop circuit further comprises a means for controlling a means for latching. The means for controlling comprises a clock control means for receiving the clock signal at a gate electrode and coupling a first current electrode of the clock control means to a first current electrode of a data control means in response to the clock signal. The data control means is for receiving the input data signal at a gate electrode and coupling the first current electrode of the data control means to a second current electrode of the data control means in response to the input data signal. The means for latching is for storing a latched voltage as a first latched input data in a higher voltage domain based on the input data signal, in response to the clock control means and the data control means. The flip-flop circuit further comprises a means for receiving the first latched input data from the means for latching, and latching the first latched input data as a second latched output data. The flip-flop circuit further comprises a means for outputting the second latched output data as a flip-flop output.
In another aspect, a method for latching an input data signal in a flip-flop circuit is provided. The method comprises receiving, at an input stage, an input data signal on a data input in a lower voltage domain. The method further comprises receiving, at the input stage, a clock signal on a clock input. The method further comprises receiving the clock signal at a gate electrode of a clock control transistor. The clock control transistor comprises a first current electrode and a second current electrode coupled to a first current electrode of a data control transistor. The method further comprises receiving the input data signal at a gate electrode of the data control transistor. The data control transistor comprises the first current electrode coupled to the second current electrode of the clock control transistor, and a second current electrode. The method further comprises generating a control signal based on an activation of the clock control transistor by the clock signal and the data control transistor by the input data signal. The method further comprises storing a latched voltage as a first latched input data at a first latch node in a higher voltage domain than the lower voltage domain, based on the input data signal in response to the control signal. The method further comprises latching the first latched input data as a second latched output data in a slave stage. The method further comprises outputting the second latched output data as a flip-flop output.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs). Related methods are also disclosed. In this regard, a multi-level conversion flip-flop circuit is provided that is configured to latch a representation of a received input data signal in a lower voltage domain in a latch circuit in a higher voltage domain. In this manner, the multi-level conversion flip-flop operates in the higher voltage domain to minimize insertion loss/delay, thereby increase performance, without the need to provide separate voltage level shifters to shift the input data signal from the lower voltage domain to the higher voltage domain. Furthermore, combinational logic can operate at a lower voltage level to reduce power consumption. Further still, area and power may be conserved as a result of eliminating the separate voltage level shifters at input and output stages of the flip-flop.
In this regard,
With reference to
In this example, an inverter 118 is coupled between the clock input 114 and clock control transistors 122 and 126 such that the signal activating the clock control transistors 122 and 126 is an inverted representation of the clock signal CLK (CLK_), and such that the active state of the clock signal CLK is a fall-edge transition. However, the dual-level conversion flip-flop circuit 102 could be configured for the clock signal CLK active state to be the rising edge of the clock signal CLK. Throughout the disclosure both the clock signal CLK and the inverted representation of the clock signal CLK (CLK_) may be referred to as clock signals CLK and CLK_, respectively.
With continuing reference to
The gate-controlled, control transistors 122-128 include a clock control transistor 122 gated by the clock signal CLK_, coupled to a data control transistor 124 gated by the input data signal D. The clock control transistor 122 and the data control transistor 124 are coupled together in an ANDing configuration. When the clock control transistor 122 and the data control transistor 124 are activated, they generate a control signal 130 at a first latch node 132 corresponding to a ground level connection. When at least one of the clock control transistor 122 and the data control transistor 124 is not activated, they generate a floating state at the first latch node 132, which allows the latch circuit 104 to drive the control signal 130 in the higher voltage domain Vddh.
The gate-controlled, control transistors 122-128 further include a clock control transistor 126 gated by the clock signal CLK_, coupled to a data control transistor 128 gated by an inverted representation of input data signal D (D_). The clock control transistor 126 and the data control transistor 128 are coupled together in an ANDing configuration. When the clock control transistor 126 and the data control transistor 128 are activated, they generate a control signal 134 at a second latch node 136 corresponding to the ground level connection. When at least one of the clock control transistor 126 and the data control transistor 128 is not activated, they generate a floating state at the second latch node 136, which allows the latch circuit 104 to drive the control signal 134 in the higher voltage domain Vddh.
By coupling the input data signal D and the inverted input data signal D_ to the gates of the data control transistors 124 and 128, respectively, the input data signal D in the lower voltage domain Vddl is not directly latched into the latch circuit 104. Instead, the gate-controlled, control transistors 122-128 are configured to control the latch circuit 104 to latch a voltage in the higher voltage domain Vddh representing the logic value of the input data signal D in the lower voltage domain Vddl in response to the clock signal CLK_. This allows for a level shift from the lower voltage domain Vddl to the higher voltage domain Vddh to occur within the dual-level conversion flip-flop circuit 102 without the need to provide a separate voltage level shifter to voltage level shift the input data signal D into the higher voltage domain Vddh before being input into the dual-level conversion flip-flop circuit 102.
With continuing reference to
The aspects described above with reference to the gate-controlled, control transistors 122-128 can provide additional non-limiting benefits to a multi-level conversion flip-flop circuit, such as the dual-level conversion flip-flop circuit 102 of
With the above description of the components of the dual-level conversion flip-flop circuit 102, a more detailed discussion of the operation of the dual-level conversion flip-flop circuit 102 will now be provided with reference to the flowchart in
First, the dual-level conversion flip-flop circuit 102 receives an input data signal D in a lower voltage domain Vddl and a clock signal CLK (block 202). The clock control transistor 122 receives the clock signal CLK and the data control transistor 124 receives the input data signal D (block 204). The dual-level conversion flip-flop circuit 102 generates a control signal 130 based on the activation of a clock control transistor by the activation of the clock control transistor 122 and the data control transistor 124 (block 206). The dual-level conversion flip-flop circuit 102 then stores a latched voltage in the higher voltage domain Vddh as a first latched data signal 112, based on the input data signal D in response to the control signal 130 (block 208). The dual-level conversion flip-flop circuit 102 latches the first latched data signal 112 as a second latched output data Q′ (block 210). The dual-level conversion flip-flop circuit 102 outputs the second latched output data Q′ as a flip-flop output Q (block 212).
As discussed above, the dual-level conversion flip-flop circuit 102 is configured to latch a representation of an input data signal D, received in the lower voltage domain Vddl, in a latch circuit 104 in the higher voltage domain Vddh. One way to provide such a latch circuit 104 is to provide the input data signal D and the clock signal CLK as control signals to control transistors of a cross-coupled inverter circuit. The cross-coupled inverter circuit may store a representation of the input data signal D in a manner similar to how a 6-transistor (6T) configuration static random access memory (6T SRAM) stores data. Gate-controlled, control transistors controlled by the input data signal D may be used to store the representation of the input data signal D in the cross-coupled inverter circuit operating in the higher voltage domain Vddh. Furthermore, gate-controlled, control transistors controlled the clock signal CLK may be used to control the timing for latching the representation of the input data signal D in the cross-coupled inverter circuit operating in the higher voltage domain Vddh. In this manner, the clock and data control transistors control activation of the cross-coupled inverter circuit to set the voltage level stored in an output node of the cross-coupled inverter circuit based on the clock signal CLK and the input data signal D.
In this regard,
The latch circuit 104 further includes a PMOS transistor 310 and an NMOS transistor 312, wherein the respective gates of the PMOS transistor 310 and the NMOS transistor 312 are connected to form an input of the second inverter 304. Also, each of the PMOS transistor 310 and the NMOS transistor 312 has one of their respective current electrodes connected to form an output of the second inverter 304. A remaining current electrode of the PMOS transistor 310 is connected to the voltage source of the higher voltage domain Vddh. A remaining current electrode of the NMOS transistor 312 is connected to the ground level connection of the dual-level conversion flip-flop circuit 102. The PMOS transistor 310 and the NMOS transistor 312 are activated in a complementary manner similar to how the PMOS transistor 306 and the NMOS transistor 308 are activated, and thus, their activation will not be explained further.
With continuing reference to
Although the dual-level conversion flip-flop circuit 102, described with reference to
In this regard,
With reference to
The head pair transistor circuit 404 further includes a PMOS transistor 410, having a first electrode coupled to the second current electrode of the PMOS transistor 406 and to the power input of the first inverter 302, a gate electrode coupled to the clock signal CLK_, and a second electrode coupled to the second current electrode of the PMOS transistor 408 and to the power input of the second inverter 304. Thus, the PMOS transistor 410 functions as a bridge transistor between the power input of the first inverter 302 and the power input of the second inverter 304. When the clock signal CLK is in a high logic state, the clock signal CLK_ is in a low logic state, and the PMOS transistor 410 is turned on, thereby causing the voltage source Vdd to reach the power input of the first and second inverters 302 and 304, independent of the input data signal D being in a high logic state or a low logic state. When the clock signal CLK is in a low logic state, the clock signal CLK_ is in a high logic state, and the PMOS transistor 410 is turned off, thereby causing the voltage source Vdd to reach the power input of only one of the first and second inverters 302 and 304, based on the state of the input data signal D.
Accordingly, when the clock signal CLK is in a low logic state, the clock signal CLK_ is in a high logic state, which turns on the clock control transistor 122 and the clock control transistor 126, allowing the writing of the logic value of the input data signal D into the latch circuit 104. Setting the clock signal CLK_ in a high logic state turns the PMOS transistor 410 off and allows the voltage source Vdd to reach the power input of only one of the first and second inverters 302 and 304, based on the state of the input data signal D. In particular, setting the clock signal CLK_ in a high logic state turns the PMOS transistor 410 off and allows the voltage source Vdd to reach a power input of one of the two inverters. The powered inverter uses the voltage for latching the representation of the input data signal D into the latch circuit 104. The other inverter does not receive the voltage This prevents the establishment of a path between the voltage source Vdd and ground level during the period in which the cross-coupled inverter structure reaches steady state, thus reducing a dynamic power loss.
For example, when the input data signal D is a logic high, the head pair transistor circuit 404 provides the voltage source Vdd only to the second inverter 304, which requires the voltage source Vdd in order to set the second latch node 136 to a logic high in the higher voltage domain Vddh. Accordingly, head pair transistor circuit 404 does not create a path between the voltage source Vdd and ground level while the cross-coupled inverter structure reaches a steady state, thus reducing dynamic power loss.
In detail, the head pair transistor circuit 504 of
The multi-level conversion flip-flop circuits for multi-power domain ICs and related methods according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.
In this regard,
Other master and slave devices can be connected to the system bus 608. As illustrated in
The CPU(s) 602 may also be configured to access the display controller(s) 620 over the system bus 608 to control information sent to one or more displays 626. The display controller(s) 620 sends information to the display(s) 626 to be displayed via one or more video processors 628, which process the information to be displayed into a format suitable for the display(s) 626. The display(s) 626 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The master devices and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
