Patent Application
20250175174
This application claims priority under 35 U.S.C. § 119 to European patent application EP 23212581.5, filed Nov. 28, 2023, the entire disclosure of which is incorporated herein by reference.
The present disclosure relates to a power semiconductor device, a control circuit for di/dt control of a power semiconductor device, an electronic device including such power semiconductor device and such control circuit, and a method of multi-level di/dt control of a power semiconductor device.
Power semiconductor based switches, such as insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), gallium nitride (GaN) semiconductor devices, and etcetera, are typically designed to switch as fast as possible to achieve minimum turn-on and turn-off power losses. However, when a freewheeling diode (also known as flyback diode) is used with the switch, at turn-on transient, the freewheeling diode typically requires a slow transition to reduce the reverse recovery current and diode transition power loss. At turn-off, the power semiconductor device typically requires a low overshoot voltage to avoid avalanche breakdown which needs to slow down the turn-off transient. A power semiconductor device typically includes one or more of such semiconductor-based switches.
Known power semiconductor devices use fixed-value gate resistors to achieve the above engineering objective. However, such fixed-value gate resistor-based solution needs to compromise switching performance between low and high switching currents. Alternative solutions are known that use a closed-loop gate drive control method, which can realize good control of the switching transient. However, such closed-loop control circuit typically requires very high design bandwidth, resulting in stability, complexity and reliability challenges in designing and applying such circuits.
A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure can encompass a variety of aspects and/or a combination of aspects that are not set forth.
According to an aspect of the present disclosure, a power semiconductor device is presented. The power semiconductor device can include a power semiconductor die forming a power switch. The power switch can include an input pad, an output pad and a control pad. The power semiconductor device can further include a collector power terminal coupled to the input pad of the power switch. The power semiconductor device can further include an auxiliary gate terminal coupled to the control pad of the power switch. The power semiconductor device can further include an emitter power terminal. The power semiconductor device can further include two or more inductance/resistance pairs, wherein each inductance/resistance pair includes a common stray inductance and a resistance which are arranged in series between the output pad of the power switch and the emitter power terminal. The power semiconductor device can further include a plurality of auxiliary emitter terminals. The auxiliary emitter terminals can be coupled to both sides of the inductance/resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance/resistance pair.
In an embodiment, the common stray inductance and the resistance can be formed by wire bonds and/or substrate copper tracks.
In an embodiment, a first inductance value of the common stray inductance and/or a first resistance value of the resistance is the same in different inductance/resistance pairs.
In an embodiment, a second inductance value of the common stray inductance and/or a second resistance value of the resistance is different in different inductance/resistance pairs.
In an embodiment, a plurality of power semiconductor dies can form a plurality of power switches.
In an embodiment, the power semiconductor device can further include a device package. The collector power terminal, the auxiliary gate terminal, the emitter power terminal and the plurality of auxiliary emitter terminals can extend through the device package.
According to an aspect of the present disclosure, a control circuit for di/dt control of a power semiconductor device is presented. The power semiconductor device can include one or more of the above-described features. The control circuit can be arranged to be coupled to a plurality of inductance/resistance pairs of the power semiconductor device. The control circuit can be arranged to form a gate drive current return loop through an inductance/resistance pair. The control circuit can be arranged to select the inductance/resistance pair. Thus, multi-level di/dt control can be achieved.
In an embodiment, the control circuit can include a plurality of electronics switches. Each electronic switch can be arranged to be coupled to one side of one inductance/resistance pair.
In an embodiment, the control circuit can further include an input arranged to receive a di/dt selection input signal. The control circuit can further include a demultiplexer circuit arranged to receive the di/dt selection input signal via the input and coupled to the plurality of electronics switches. The control circuit can further include one or more oscillation damp resistors coupled between the electronics switches and a gate drive power supply ground.
The control circuit can further include an input arranged to receive a di/dt selection input signal. The control circuit can further include a demultiplexer circuit arranged to receive the di/dt selection input signal via the input and coupled to the plurality of electronics switches. The control circuit can further include one or more oscillation damp resistors coupled between the electronics switches and a gate drive power supply ground. The control circuit can further include a diode. One side of the diode can be arranged to be coupled to one side of a first of the inductance/resistance pairs. The one side of the first of the inductance/resistance pairs can be coupled to an output pad of a power switch of the power semiconductor device. The other side of the diode can be coupled to the gate drive power supply ground.
In an embodiment, the one side of the diode can be an anode of the diode.
In another embodiment, the one side of the diode can be a cathode of the diode.
The control circuit can further include a first input arranged to receive di/dt reference input signal. The control circuit can further include a second input arranged to receive a di/dt feedback signal. The control circuit can further include a di/dt process logic circuit arranged to receive the di/dt reference input signal via the first input. The control circuit can further include a demultiplexer circuit coupled to the di/dt processing logic circuit and coupled to the plurality of electronics switches. The control circuit can further include one or more oscillation damp resistors coupled between the electronics switches and a gate drive power supply ground. The control circuit can further include a di/dt detect circuit arranged to receive the di/dt feedback signal via the second input and arranged to be coupled to one side of a first of the inductance/resistance pairs. The one side of the first of the inductance/resistance pairs can be coupled to an output pad of a power switch of the power semiconductor device. The control circuit can further include an error amplify circuit arranged to receive the di/dt reference input signal via the first input and arranged to receive the di/dt feedback signal via the second input. The error amplify circuit can be coupled to a gate drive circuit for gate drive level close loop di/dt control.
According to an aspect of the present disclosure, an electronic device is presented. The electronic device can include a power semiconductor device having one or more of the above-described features. The electronic device can further include a control circuit having one or more of the above-described features.
In an embodiment, the electronic device can further include a gate drive circuit arranged to be coupled to an input pad and a control pad of a power switch of the power semiconductor device.
Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts.
The figures are intended for illustrative purposes only and do not serve as a restriction of the scope of the protection as laid down by the claims.
It will be readily understood that the components of the embodiments, as generally described herein and illustrated in the appended figures, could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that can be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification can, but do not necessarily, refer to the same example.
Furthermore, the described features, advantages, and characteristics of the present disclosure can be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages can be recognized in certain embodiments that are not present in all embodiments of the present disclosure. Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification can, but do not necessarily, all refer to the same embodiment.
Di/dt control, often referred to as di/dt protection or current slew rate control, is a technique used in power electronics and power semiconductor devices to limit the rate of change of current (di/dt) during switching transitions. It can be employed to manage and reduce electromagnetic interference (EMI), minimize voltage spikes and ringing, and/or prevent excessive stress on components, especially in high-frequency applications. Di/dt control is commonly used in devices like MOSFETs, IGBTs and other power switches.
Di/dt control is especially important in applications where high-frequency switching is required, such as in switch-mode power supplies (SMPS), motor drives, and radio-frequency (RF) systems. By managing the rate of change of current, it helps to ensure that the system operates efficiently, reliably, and with reduced EMI, while also extending the lifespan of components.
Stray inductance in the context of MOSFETs, IGBTs, and other power semiconductor devices refers to parasitic inductance. This parasitic inductance can be present in various parts of the circuit and interconnections and can have an impact on the performance and switching characteristics of a power semiconductor device. Stray inductance can affect the switching speed and efficiency of a semiconductor device in high-frequency applications. When the power semiconductor device switches on or off, voltage spikes can be generated due to the rapid change in current. These voltage spikes can lead to ringing and can cause unwanted oscillations in the circuit. Stray inductance exacerbates these issues because it stores energy in the form of a magnetic field, and when the current changes quickly, it can induce voltage spikes and ringing.
This disclosure presents a semiconductor device including multiple gate drive auxiliary emitter terminals and a di/dt control circuit to utilize these auxiliary emitter terminals to realize substantially real-time multi-level di/dt control.
The solution of the present disclosure can utilize the negative feedback effect of a common stray inductance to the gate drive loop to realize the multi-levels of di/dt control. Here, the common stray inductance is the parasitic inductance coupled between the gate drive loop and power emitter path. This parasitic inductance can be created by wire bonds and/or copper tracks on the substrate.
Compared to conventional fixed-value gate resistor methods, the proposed solution advantageously reduces switching losses and turn on/off time delays. Furthermore, the proposed solution is less complex compared to, e.g., known closed-loop gate drive control solutions while being able to realize substantial real-time multi-level di/dt control with improved circuit stability and reliability.
The power switch can be formed by any semiconductor die 2, such as an IGBT, SiC MOSFET, GaN, and etcetera. The power switch typically includes an input pad, e.g., a collector in an IGBT or a drain in a MOSFET, an output pad, e.g., an emitter in an IGBT or a source in a MOSFET, and a control pad, e.g., a gate in an IGBT or in a MOSFET. In the following, the power semiconductor die and the power switch formed by the semiconductor die can both be referenced by the numeral “2”. There can be a single power semiconductor die 2 integrated into the package 1. Alternatively, there can be multiple power semiconductor dies 2 integrated into the package 1, e.g., multiple semiconductor dies 2 in parallel or semiconductor dies 2 in series to form half-bridge or multi-level topologies.
The freewheeling diode die 3 forms a freewheeling diode. In the following, the freewheeling diode die and the freewheeling diode formed by the freewheeling diode die can both be referenced by the numeral “3”.
The power switch 2 of the power semiconductor device 1000 typically includes a freewheeling diode 3, but it is possible that no freewheeling diode 3 is used with the power switch 2. In the latter example, the power semiconductor device 1000 can include a power semiconductor die 2 without a freewheeling diode die 3.
The auxiliary emitter terminals 8-11 provide a pin interface for di/dt control. Contrary to conventional semiconductor device that typically include a single auxiliary emitter terminal, the power semiconductor device 1000 of the present disclosure includes multiple auxiliary emitter terminals 8-11. Between the auxiliary emitter terminals 8-11, the parasitic inductances 4 and resistances 5 are pairwise coupled with the emitter current path from power semiconductor dies 2 and freewheeling diode dies 3 to power terminal 12, such as shown in
In
The circuit diagram 2000 of
The circuit diagram of
The gate drive circuit part 2002 drives the power switch 2 through gate drive circuit block 14 and gate resistor 18 according to the PWM input signal 27. The di/dt control circuit part 2004 creates the gate drive current return loop from gate drive power supply 19 to the power supply ground 20, which flows through one of the branches with common stray inductance 4 and resistance 5. Branch selection can be performed by demultiplexer circuit 21 and electronics switches 23 according to the di/dt selection input 28. Since the common stray inductance 4 and resistance 5 are coupled with the emitter current path from power semiconductor die(s) 2 and freewheeling diode die(s) 3 to power terminal 12, there is a voltage drop generated on the common stray inductance 4 and resistance 5 due to current change (or di/dt) in the emitter current path during turn-on and turn-off transitions. Since the voltage drop plays a negative effect on the gate drive loop for the semiconductor device, it helps to slow down and stabilize the turn-on and turn-off current transition speed, which establishes a stable di/dt value. In the four auxiliary emitter terminals 8-11, auxiliary emitter terminal 8 provides the fastest turn-on and turn-off speed, which generates the highest di/dt value. Auxiliary emitter terminal 9 provides the 2nd fastest turn-on and turn-off speed and 2nd highest di/dt value. While auxiliary terminals 10 and 11 provide the 3rd and 4th highest di/dt value, respectively.
The circuit diagram 2100 of
In the example of
The circuit diagram 2200 of
In the example of
Moreover, in the example of
The gate drive circuit part 2002, 2102, 2202, the di/dt control circuit part 2004, 2104, 2204, and the power semiconductor device 1000, 1100, such as shown in the circuit diagrams 2000, 2100, 2200 of
At turn-on transient, di/dt are adjusted successfully as shown in plot 120, while no obvious influence on dv/dt as plotted in 110 or turn-on gate voltage delay as shown in plot 100. Similarly at turn-off transient, di/dt is adjusted as shown in plot 220, with no obvious changes of dv/dt as shown in 210. It is worth to notice that the overshoot voltage can be reduced greatly from 630V to 430V. Further, there is no turn-off gate voltage delay as shown in plot 200.
Table 1 presents detailed numerical results for the simulation validation as illustrated in
In the first scenario, the converter system of the present disclosure uses a common stray inductance of 2 nH, resistance of 10 mΩ and 2 Ω turn-on and turn-off gate resistors (Rg_on/Rg_off) to achieve a 1.6 kA/us di/dt for turn-on and 2.0 kA us for turn-off. To achieve a similar level di/dt control performance in a conventional solution, the turn-on and turn-off gate resistors (Rg_on/Rg_off) need to be as high as 16 Ω and 13 Ω, respectively. As a result, in the solution of the present disclosure, the turn-on switching loss (Eon) is decreased from 1.452 mJ to 0.885 mJ and the turn-off loss (Eoff) is decreased from 1.001 mJ to 0.802 mJ. Advantageously, in the solution of the present disclosure, these two switching losses have thus been decreased 39% and 20%, respectively, which decreases overall system power loss, decreases device junction temperature and decreases the design cost of the power semiconductor device and converter system.
Moreover, with the solution of the present disclosure, the turn-on delay (tdon) is advantageously decreased from 35.8 ns to 15.0 ns, while the turn-off delay (tdoff) is advantageously decreased from 432.3 ns to 184.4 ns, which is more than halved. A higher turn-on and turn-off delay will need high value bridge dead time in order to avoid short circuit which sacrifices the utility of converter input current, thus lower turn-on and turn-off delays are preferred.
Moreover, voltage transition speed (dv/dt_fall and dv/dt_rise) is advantageously increased when using the solution of the present disclosure.
In the comparison between the solution of the present disclosure and the conventional solution, switching current rise time (tr), fall time (tf) and turn-off surge voltage (Voff_surge) are kept substantially the same as these variables are directly related to the di/dt value which is kept the same in each scenario.
A similar comparison can be made between the solution of the present disclosure and the conventional solution based on columns 4 and 5 of Table 1 related to the second scenario (di/dt of 1.1-1.3 kA/us).
| Number | Date | Country | Kind |
|---|---|---|---|
| 23212581.5 | Nov 2023 | EP | regional |
