Claims
- 1. A display controller for controlling a display where the display provides an image as a pixel array displayed in sequential frames, where each pixel has a selectable data value in each frame, said display controller comprising,
- frame means for establishing a number of sequential frames as a frame set,
- data means for providing the data value of each of said pixels in the array to define the image,
- pattern means for providing modulation patterns, said patterns including patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related,
- modulation means, operable over said number of sequential frames, for modulating the data values of pixels with said patterns whereby the intensity level of said pixels over said number of sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.
- 2. The display controller of claim 1 wherein said pixel array is P formed of pixels p.sub.i,j, wherein F is the number of frames in a frame set and wherein P is represented by P.sub.1, P.sub.2. . . , P.sub.f, . . . . , P.sub.F where P.sub.f is the value of P in each frame, f, and wherein,
- said pattern means provides said modulation patterns U having pattern values, u.sub.f, for the frame f so that the modulated image U*P for the frame f has modulated pixel values u.sub.f *(p.sub.i,j).sub.f where (p.sub.i,j).sub.f is the value of pixel p.sub.i,j for the f frame.
- 3. The display controller of claim 2 wherein F equals 16.
- 4. The display controller of claim 3 wherein said the pixel array P is partitioned into N pixel groups P.sup.1, P.sup.2, . . . , P.sup.n, . . . , P.sup.N where each pixel group P.sup.n may have different values represented by P.sup.n.sub.f, in each frame, f, so that pixel groups for the pixel array P in frame f have the values P.sup.1.sub.f, P.sup.2.sub.f, . . . , P.sup.n.sub.f, . . . , P.sup.N.sub.f and wherein,
- said pattern means provides the patterns U with modulation groups U.sup.1, U.sup.2, . . . , U.sup.n, . . . , U.sup.N each group having patterns having values, u.sup.n.sub.f, for each frame f, said patterns including patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related, said modulation means forms the modulated image as U*P where "*" is an operator and where U*P is expressed as U.sup.1 *P.sup.1, U.sup.2 *P.sup.2, . . . , U.sup.n *P.sup.n, . . . . , U.sup.N *P.sup.N.
- 5. The display controller of claim 4 wherein,
- said pattern means provides each said modulation group U.sup.n with a set of patterns U.sup.n 1, U.sup.n2, . . . , U.sup.n g, . . . U.sup.n G where G is the number of patterns in the set for the group U.sup.n g where each pattern in a set U.sup.n has a different number of 1's and 0's to provide a different modulation and each pattern U.sup.n g in the set U.sup.n includes F pattern values u.sup.n g.sub.1, u.sup.n g.sub.2, . . . , u.sup.n g.sub.f, . . . , U.sup.n g.sub.F,
- said modulation means for each frame, f, forms the modulated image U*P with modulated pixel values u.sup.n g.sub.f *(p.sub.i,j).sup.n.sub.f where (P.sub.i,j).sup.n.sub.f is the data value of the pixel P.sub.i,j for the pixel array P.sup.n in the f frame and u.sup.n g.sub.f is the binary 1 or binary 0 value of the u.sup.n g pattern in the f frame.
- 6. The display controller of claim 5 wherein N=2 and the image pixel array P is formed of pixel groups P.sup.1 and P.sup.2 which are modulated by modulation groups U.sup.1 and U.sup.2 to form the modulated image U.sup.1 *P.sup.1, U.sup.2 *P.sup.2.
- 7. The display controller of claim 6 wherein U.sup.2 is represented by Z and U.sup.1 is represented by U and the image P, having pixel groups P.sup.1 and P.sup.2 where P.sup.1 is formed of pixels P.sub.i,j and p.sub.i+1,i+1 and where P.sup.2 is formed of adjacent pixels P.sub.i,j+1 and P.sub.i+1,j and wherein,
- said modulation means forms the modulation U*P.sup.1, Z,P.sup.2 designated as UZ*P.
- 8. The display controller of claim 7 wherein the U*P.sup.1, Z*P.sup.2 array of modulated pixels for a frame f is given as follows:
- ______________________________________u.sub.f *p.sub.1,1 z.sub.f *p.sub.1,2 u.sub.f *p.sub.1,3 . . . z.sub.f *p.sub.1,lz.sub.f *p.sub.2,1 u.sub.f *p.sub.2,2 z.sub.f *p.sub.2,3u.sub.f *p.sub.3,1 z.sub.f *p.sub.3,2 u.sub.f *p.sub.3,3. .. .. .z.sub.f *p.sub.l,1 u.sub.f *p.sub.l,2 z.sub.f *p.sub.l,3 u.sub.f *p.sub.l,j______________________________________ .
- 9. The display controller of claim 8 wherein the U*P.sup.1,Z*P.sup.2 array of modulated pixels for a frame set F as a function of frame f for particular scale patterns Ug.sub.f and Zg.sub.f each having gray scale modulations Ug*P.sup.1,Zg*P.sup.2 is given as follows:
- ______________________________________Ug.sub.f *p.sub.1,1 Zg.sub.f *p.sub.1,2 Ug.sub.f *p.sub.1,3 . . . Zg.sub.f *p.sub.1,lZg.sub.f *p.sub.2,1 Ug.sub.f *p.sub.2,2 Zg.sub.f *p.sub.2,3Ug.sub.f *p.sub.3,1 Zg.sub.f *p.sub.3,2 Ug.sub.f *p.sub.3,3. .. .. .Zg.sub.f *p.sub.l,1 Ug.sub.f *p.sub.l,2 Zg.sub.f *p.sub.l,3 Ug.sub.f *p.sub.l,j______________________________________
- 10. The display controller of claim 8 wherein the modulated pixel array Ug*P.sup.1,Zg*P.sup.2 is further partitioned with the modulation patterns Ug and Zg partitioned into first patterns .sup.1 Ug and .sup.1 ZUg which tend to cause charge accumulation of one polarity and second inverse patterns .sup.2 Ug and .sup.2 Zg, respectively, which tend to cause charge accumulation of the opposite polarity, said frame means provides charge set reverse signal after a number of frames establishing a charge set,
- said modulation means for the pixel groups P.sup.1 and P.sup.2 modulates for a charge set with the first patterns lug and .sup.1 Zg to form the modulated pixel array .sup.1 Ug*P.sup.1, .sup.1 Zg*P.sup.2 as follows:
- ______________________________________.sup.1 Ug.sub.f *p.sub.1,1 .sup.1 Zg.sub.f *p.sub.1,2 .sup.1 Ug.sub.f *p.sub.1,3 . . . .sup.1 Zg.sub.f *p.sub.1,l.sup.1 Zg.sub.f *p.sub.2,1 .sup.1 Ug.sub.f *p.sub.2,2 .sup.1 Zg.sub.f *p.sub.2,3.sup.1 Ug.sub.f *p.sub.3,1 .sup.1 Zg.sub.f *p.sub.3,2 .sup.1 Ug.sub.f *p.sub.3,3. .. .. ..sup.1 Zg.sub.f *p.sub.l,1 .sup.1 Ug.sub.f *p.sub.l,2 .sup.1 Zg.sub.f *p.sub.l,3 .sup.1 Ug.sub.f *p.sub.l,j______________________________________
- and alternately in response to said charge set signal modulates said pixel groups P.sup.1 and P.sup.2 with the second patterns .sup.2 Ug and .sup.2 Zg to form the modulated pixel array .sup.2 Ug*P.sup.1, .sup.2 Zg*P.sup.2 as follows:
- ______________________________________.sup.2 Ug.sub.f *p.sub.1,1 .sup.2 Zg.sub.f *p.sub.1,2 .sup.2 Ug.sub.f *p.sub.1,3 . . . .sup.2 Zg.sub.f *p.sub.1,l.sup.2 Zg.sub.f *p.sub.2,1 .sup.2 Ug.sub.f *p.sub.2,2 .sup.2 Zg.sub.f *p.sub.2,3.sup.2 Ug.sub.f *p.sub.3,1 .sup.2 Zg.sub.f *p.sub.3,2 .sup.2 Ug.sub.f *p.sub.3,3. .. .. ..sup.2 Zg.sub.f *p.sub.l,1 .sup.2 Ug.sub.f *p.sub.l,2 .sup.2 Zg.sub.f *p.sub.l,3 .sup.2 Ug.sub.f *p.sub.l,j______________________________________
- whereby the alternation of the modulated pixel array .sup.1 Ug*P.sup.1, .sup.1 Zg*P.sup.2 with the modulated pixel array .sup.2 Ug*P.sup.1, .sup.2 Zg*P.sup.2 over charge sets tends to cancel the charge accumulation to 0.
- 11. The display controller of claim 10 wherein the second patterns .sup.2 Ug and .sup.2 Zg are inverses of the first patterns .sup.1 Ug and .sup.1 Zg, respectively.
- 12. The display controller of claim 10 wherein said charge set is 256 frames.
- 13. The display controller of claim 1 wherein,
- said frame means establishes a number of said frame sets as a charge set and provides a reverse signal after each charge set,
- said pattern means provides first and second sets of patterns, said first set of patterns tending to cause charge accumulation of one polarity, said second set of patterns tending to cause charge accumulation of the opposite polarity, said pattern means responsive to said reverse signal to switch from one of said first and second sets of patterns to the other whereby accumulated charges tend to cancel.
- 14. The display controller of claim 1 wherein the number of bits in said scale patterns is equal to said number of frames in a frame set.
- 15. The display controller of claim 1 wherein the number of frames is equal to 16 and wherein the number of bits in each scale pattern is 16.
- 16. The display controller of claim 1 wherein said scale pattern means stores eight scale patterns.
- 17. The display controller of claim 16 wherein said scale patterns include scale patterns U1, U2, U3, U4, U5, U6, U7 and U9 as follows:
- ______________________________________U1 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0U2 = 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0U3 = 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0U4 = 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1U5 = 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1U6 = 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1U7 = 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1U8 = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.______________________________________
- 18. The display controller of claim 6 wherein said scale patterns include scale patterns U1, U2, U3, U4, U5, U6, U7, and U8 as follows:
- ______________________________________U1 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0U2 = 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1U3 = 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1U4 = 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0U5 = 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0U6 = 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0U7 = 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1U8 = 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.______________________________________
- 19. The display controller of claim 1 wherein said scale pattern means stores sixteen scale patterns.
- 20. The display controller of claim 19 wherein said scale patterns include scale patterns U1, U2, U3, U4, U5, U6, U7, U8, Z1, Z2, Z3, Z4, Z5, Z6, Z7, and Z8 as follows:
- ______________________________________U1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Z1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0U2 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0Z2 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1U3 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0Z3 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1U4 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1Z4 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0U5 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1Z5 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0U6 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1Z6 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0U7 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1Z7 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1U8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Z8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1______________________________________
- 21. The display controller of claim 1 wherein a first plurality of said scale patterns having first values are used to modulate first groups of display frames, wherein a second plurality of said scale patterns having second values are used to modulate second groups of said display frames, wherein the number of frames in said first and second groups is the same, and wherein the first and second groups alternate.
- 22. A display controller for controlling a display where the display provides an image formed of an array of pixels repeatedly presented in sequential frames, where each pixel has a pre-determined location in the array that is the same from frame to frame, where each pixel has a selectable data value, and where the data values of pixels are modifiable in each frame, said display controller comprising,
- first frame means for establishing a first number of sequential frames,
- second frame means for establishing a second number of sequential frames where said second number is greater than said first number,
- data means for providing the data value of each of said pixels in an array to define the image,
- scale pattern means for providing a first group of scale patterns and a second group of scale patterns, said patterns including patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related, said first group of scale patterns and said second group of scale patterns each having first patterns formed with particular numbers of 1's and 0's in a forward sequence and having and corresponding second patterns formed with particular numbers of 1's and 0's in an inverse sequence,
- modulation means, repeatedly operable over sets of said first number of sequential frames, for modulating the data value of pixels with ones of said first patterns or corresponding ones of said second patterns whereby the average intensity level of each pixel over said sets of said first number of sequential frames is controlled as a function of the data value of the pixel and as a function of the number of 1's in said ones of said first or second patterns,
- reversing means, operable after each set of said second number of sequential frames, for switching from one of said first patterns or said second patterns to the other of said first patterns or said second patterns, said display tending to have a charge accumulation of one polarity during one set of said second number of sequential frames and a charge accumulation of opposite polarity during a subsequent set of said second number of sequential frames whereby the charge tends to cancel.
- 23. The display controller of claim 22 wherein the number of bits in said scale patterns is equal to said first number of sequential frames.
- 24. The display controller of claim 22 wherein the first number of frames is equal to 16 and wherein the number of bits in each scale pattern is 16.
- 25. The display controller of claim 22 wherein the second number of frames is equal to 256.
- 26. The display controller of claim 22 wherein said scale pattern means stores thirty scale patterns.
- 27. The display controller of claim 26 wherein said scale patterns include a first set of scale patterns .sup.1 U1, .sup.1 U2, .sup.1 U3, .sup.1 U4, .sup.1 U5, .sup.1 U6, .sup.1 U7, .sup.1 U8, .sup.1 Z1, .sup.1 Z2, .sup.1 Z3, .sup.1 Z4, .sup.1 Z5, .sup.1 Z6, .sup.1 Z7, and .sup.1 Z8 as follows:
- ______________________________________.sup.1 U1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.sup.1 Z1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.sup.1 U2 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0.sup.1 Z2 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1.sup.1 U3 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0.sup.1 Z3 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1.sup.1 U4 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1.sup.1 Z4 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0.sup.1 U5 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1.sup.1 Z5 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0.sup. 1 U6 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1.sup.1 Z6 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0.sup.1 U7 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1.sup.1 Z7 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1.sup.1 U8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.sup.1 Z8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1______________________________________
- a second set of scale patterns .sup.2 U1, .sup.2 U2, .sup.2 U3, .sup.2 U4, .sup.2 U5, .sup.2 U6, .sup.2 U7, .sup.2 U8, .sup.2 Z1, .sup.2 Z2, .sup.2 Z3, .sup.2 Z4, .sup.2 Z5, .sup.2 Z6, .sup.2 &, and .sup.2 Z8, as follows:
- ______________________________________.sup.2 U1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.sup.2 Z1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.sup.2 U2 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0.sup.2 Z2 1 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0.sup.2 U3 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1.sup.2 Z3 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0.sup.2 U4 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0.sup.2 Z4 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1.sup.2 U5 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1.sup.2 Z5 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1.sup. 2 U6 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1.sup.2 Z6 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1.sup.2 U7 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0.sup.2 Z7 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1.sup.2 U8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.sup.2 Z8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1______________________________________
- 28. The display controller of claim 22 wherein said first and second groups are represented by U and Z, respectively, and the image is represented by P, having pixel groups P.sup.1 and P.sup.2 where P.sup.1 is formed of pixels p.sub.i,j and p.sub.i+i,j+1 and where P.sup.2 is formed of adjacent pixels p.sub.ij+1 and p.sub.i+1j and wherein,
- said modulation means forms the modulation U*P.sup.1, Z*P.sup.2 designated as UZ*P.
- 29. The display controller of claim 28 wherein the U*P.sup.1, Z*P.sup.2 array of modulated pixels for a frame f is given as follows:
- ______________________________________u.sub.f *p.sub.1,1 z.sub.f *p.sub.1,2 u.sub.f *p.sub.1,3 . . . z.sub.f *p.sub.1,lz.sub.f *p.sub.2,1 u.sub.f *p.sub.2,2 z.sub.f *p.sub.2,3u.sub.f *p.sub.3,1 z.sub.f *p.sub.3,2 u.sub.f *p.sub.3,3. .. .. .z.sub.f *p.sub.l,1 u.sub.f *p.sub.l,2 z.sub.f *p.sub.l,3 u.sub.f *p.sub.l,j______________________________________ .
- 30. The display controller of claim 28 wherein the U*P.sup.1, Z*P.sup.2 array of modulated pixels is modulated for a frame set F, where F equals said first number, as a function of frame f for particular scale patterns Ug.sub.f and Zg.sub.f each having gray scale modulations Ug*P.sup.1,Zg*P.sup.2 as follows:
- ______________________________________Ug.sub.f *p.sub.1,1 Zg.sub.f *p.sub.1,2 Ug.sub.f *p.sub.1,3 . . . Zg.sub.f *p.sub.1,lZg.sub.f *p.sub.2,1 Ug.sub.f *p.sub.2,2 Zg.sub.f *p.sub.2,3Ug.sub.f *p.sub.3,1 Zg.sub.f *p.sub.3,2 Ug.sub.f *p.sub.3,3. .. .. .Zg.sub.f *p.sub.l,1 Ug.sub.f *p.sub.l,2 Zg.sub.f *p.sub.l,3 Ug.sub.f *p.sub.l,j______________________________________
- 31. The display controller of claim 28 wherein the modulated pixel array Ug*P.sup.1,Zg*P.sup.2 is further partitioned with the modulation patterns Ug and Zg partitioned into first patterns .sup.1 Ug and .sup.1 ZUg which tend to cause charge accumulation of one polarity and second inverse patterns .sup.2 Ug and .sup.2 Zg, respectively, which tend to cause charge accumulation of the opposite polarity, said frame means provides charge set reverse signal after a number of frames establishing a charge set,
- said modulation means for the pixel groups P.sup.1 and P.sup.2 modulates for a charge set with the first patterns .sup.1 Ug and .sup.1 Zg to form the modulated pixel array .sup.1 Ug*P.sup.1, .sup.1 Zg*P.sup.2 as follows:
- ______________________________________.sup.1 Ug.sub.f *p.sub.1,1 .sup.1 Zg.sub.f *p.sub.1,2 .sup.1 Ug.sub.f *p.sub.1,3 . . . .sup.1 Zg.sub.f *p.sub.1,l.sup.1 Zg.sub.f *p.sub.2,1 .sup.1 Ug.sub.f *p.sub.2,2 .sup.1 Zg.sub.f *p.sub.2,3.sup.1 Ug.sub.f *p.sub.3,1 .sup.1 Zg.sub.f *p.sub.3,2 .sup.1 Ug.sub.f *p.sub.3,3. .. .. ..sup.1 Zg.sub.f *p.sub.l,1 .sup.1 Ug.sub.f *p.sub.l,2 .sup.1 Zg.sub.f *p.sub.l,3 .sup.1 Ug.sub.f *p.sub.l,j______________________________________
- and alternately in response to said charge set signal modulates said pixel groups P.sup.1 and P.sup.2 with the second patterns .sup.2 Ug and .sup.2 Zg to form the modulated pixel array .sup.2 Ug*P.sup.1, .sup.2 Zg*P.sup.2 as follows:
- ______________________________________.sup.2 Ug.sub.f *p.sub.1,1 .sup.2 Zg.sub.f *p.sub.1,2 .sup.2 Ug.sub.f *p.sub.1,3 . . . .sup.2 Zg.sub.f *p.sub.1,l.sup.2 Zg.sub.f *p.sub.2,1 .sup.2 Ug.sub.f *p.sub.2,2 .sup.2 Zg.sub.f *p.sub.2,3.sup.2 Ug.sub.f *p.sub.3,1 .sup.2 Zg.sub.f *p.sub.3,2 .sup.2 Ug.sub.f *p.sub.3,3. .. .. ..sup.2 Zg.sub.f *p.sub.l,1 .sup.2 Ug.sub.f *p.sub.l,2 .sup.2 Zg.sub.f *p.sub.l,3 .sup.2 Ug.sub.f *p.sub.l,j______________________________________
- whereby the alternation of the modulated pixel array .sup.1 Ug*P.sup.1, .sup.1 Zg*P.sup.2 with the modulated pixel array .sup.2 Ug*P.sup.1, .sup.2 Zg*P.sup.2 over charge sets tends to cancel the charge accumulation to 0.
- 32. The display controller of claim 31 wherein the second patterns .sup.2 Ug and .sup.2 Zg are inverses of the first patterns .sup.1 Ug and .sup.1 Zg, respectively.
- 33. A computer system including a display subsystem having display memory, a display controller, and a display where said display controller controls the display where said display provides an image as a pixel array displayed in sequential frames, where each pixel has a selectable data value in each frame, said display controller further including,
- frame means for establishing a number of sequential frames as a frame set,
- data means for providing the data value of each of said pixels in the array to define the image,
- pattern means for providing modulation patterns, said patterns including patterns each formed of sequences of different numbers of both 1's and 0's that are not phase related,
- modulation means, operable over said number of sequential frames, for modulating the data values of pixels with said patterns whereby the intensity level of said pixels over said number of sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.
- 34. The computer system of claim 28 wherein said pixel array is partitioned into a character array and wherein said display memory stores two bytes of data for each of the characters in the character array.
- 35. The computer system of claim 29 having means for operating in text mode or in graphic mode, and where for each character in text mode operation, one of said two bytes per character is encoded data representing the text character and the other byte represents character attributes for the text character.
- 36. The computer system of claim 30 wherein said display controller includes decode means for decoding the encoded data for the text character to form the character pixels representing the character image.
- 37. The computer system of claim 30 wherein said display controller includes a pixel preprocessor including means for decoding the character attributes and multiplexing means for multiplexing input data as a function of the mode and includes a pixel processor for modulating the pixel data.
- 38. A display controller for controlling a display where the display provides an image as a pixel array displayed in sequential frames, where each pixel has a selected data value in each frame, said display controller comprising,
- frame means for establishing a number of sequential frames as a frame set,
- data means for providing the data value of each of said pixels in the array to define the image,
- means for providing modulation patterns, said patterns including patterns each formed of sequences of different numbers of both 1's and 0's, where said sequences are not phase related,
- modulation means, operable over said number of sequential frames, for modulating said pixels with said patterns whereby the intensity level of said pixels over said number of sequential frames is controlled as a function of the data value of the pixels and as a function of the patterns.
Parent Case Info
This application is a continuation-in-part of the application.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5221971 |
Allen et al. |
Jun 1993 |
|
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
744710 |
Aug 1991 |
|