Claims
- 1. A method, comprising:
transforming a stream of asynchronous transfer mode cells into a stream of bonded asynchronous transfer mode cells; demultiplexing the stream of bonded asynchronous transfer mode cells into a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells; and transmitting the plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells to a remote location via a plurality of permanent virtual circuits,
characterized in that the transmitted plurality of streams of inverse multiplexed bonded asynchronized transfer mode cells can be multiplexed into a multiplexed stream of asynchronized transfer mode cells after transmission via at least two permanent virtual circuits, which compose the plurality of permanent virtual circuits, that do not have an identical bit-rate.
- 2. The method of claim 1, wherein at least two of the plurality of permanent virtual circuits are characterized by different bit-rates.
- 3. The method of claim 1, further comprising monitoring a bit-rate capacity for each of the plurality of permanent virtual circuits.
- 4. The method of claim 3, wherein demultiplexing includes allocating bonded asynchronous transfer mode cells to the plurality of permanent virtual circuits as a function of their respective bit-rates.
- 5. The method of claim 1, wherein transforming the stream of asynchronous transfer mode cells into the stream of bonded asynchronous transfer mode cells includes adding a plurality of control octets to each cell of the stream of asynchronous transfer mode cells.
- 6. The method of claim 1, wherein transforming the stream of asynchronous transfer mode cells into the stream of bonded asynchronous transfer mode cells includes converting an asynchronous transfer mode cell into a partial bonded asynchronous transfer mode cell.
- 7. The method of claim 1, wherein the plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells includes a partial page of a memory.
- 8. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 1.
- 9. A field programmable gate array programmed to perform the method of claim 1.
- 10. A circuit board comprising the field programmable gate array of claim 9.
- 11. An integrated circuit, comprising the field programmable gate array of claim 9.
- 12. A circuit board, comprising the integrated circuit of claim 11.
- 13. A network, comprising the circuit board of claim 12.
- 14. A method, comprising:
multiplexing a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells received from a plurality of permanent virtual circuits, into a stream of bonded asynchronous transfer mode cells; and transferring the stream of bonded asynchronous transfer mode cells into a stream of asynchronous transfer mode cells, characterized in that the received plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells can be multiplexed into the stream of bonded asynchronous transfer mode cells after reception via at least two permanent virtual circuits, which compose the plurality of permanent virtual circuits, that do not have an identical bit-rate.
- 15. The method of claim 14, where transforming includes re-sequencing the stream of asynchronous transfer mode cells.
- 16. The method of claim 15, wherein re-sequencing includes utilizing a plurality of control octets.
- 17. The method of claim 14, wherein transforming the stream of bonded asynchronous transfer mode cells includes removing a plurality of control octets from each cell of the stream of bonded asynchronous transfer mode cells.
- 18. The method of claim 14, wherein transforming the stream of bonded asynchronous transfer mode includes converting a partial bonded asynchronous transfer mode cell into an asynchronous transfer mode cell.
- 19. The method of claim 14, wherein transforming the stream of bonded asynchronous transfer mode cells includes transforming a partial page of a memory.
- 20. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 14.
- 21. A field programmable gate array programmed to perform the method of claim 14.
- 22. A circuit board, comprising the field programmable gate array at claim 21.
- 23. An integrated circuit, comprising the apparatus of claim 21.
- 24. A circuit board, comprising the integrated circuit of claim 23.
- 25. A network, comprising the circuit board of claim 24.
- 26. A method, comprising:
characterizing capacities of a plurality of permanent virtual circuits with a plurality of bit-rate octets; utilizing a counter state as a pointer into an array composed of the plurality of bit-rate octets; incrementing the counter until a one is read; allocating a plurality of bonded asynchronous transfer mode cells to a permanent virtual circuit associated with a bit-rate octet in which the one was read proportionally to a number of ones in the bit-rate octet in which the one was read.
- 27. The method of claim 26, wherein incrementing a counter includes utilizing a pseudo-random noise counter to randomly advance the counter.
- 28. An apparatus, comprising:
an asynchronous transfer mode network switch coupled to a plurality of permanent virtual circuits; a bus coupled to the asynchronous transfer mode network switch; and a bonding engine coupled to the bus, characterized in that a bi-directional transformation between a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells and a stream of asynchronous transfer mode cells can be performed when at least two permanent virtual circuits, which compose the plurality of permanent virtual circuits, do not have an identical bit-rate.
- 29. The apparatus of claim 28, wherein the bus includes a utopia bus.
- 30. A bonded asynchronous transfer mode cell, comprising:
a plurality of header octets; a plurality of control octets coupled to the plurality of header octets; and a plurality of information octets coupled to the plurality of control octets.
- 31. The bonded asynchronous transfer mode cell of claim 30, wherein each of the plurality of control octets includes at least one member selected from the group consisting of: block identification, page identification, payload type indicator, cell loss priority, control flag, and address of last valid octet.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to, and claims a benefit of priority under 35 U.S.C. 119(e) 120 from, copending U.S. Ser. No. 60/344,542, filed Nov. 7, 2001, now pending, the entire contents of which are hereby expressly incorporated by reference for all purposes.
Provisional Applications (1)
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Number |
Date |
Country |
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60344542 |
Nov 2001 |
US |