Multi-mode current-to-voltage converter

Abstract

A method and circuit are provided to perform current-to-voltage conversions. The circuit is operational in one linear mode based on channel-length-modulation effects in the saturation region and two non-linear modes based on a current operation overrunning the saturation region and a logarithmic function of drain current versus gate-to-source voltage, respectively. An adaptive process is provided to set-up the quiescent point of the circuit. The conversion gain is variable with respect to the conversion mode, the current range, and the length of the converting transistor.

Description

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for current-to-voltage conversion which is able to provide sensitive current-to-voltage detection for a small amplitude AC current signal, even if the AC current signal has a DC component which varies greatly over a very wide range.

BACKGROUND OF THE INVENTION

Existing approaches to current-to-voltage conversion in VLSI are usually based on:

(1) Charge integration. A current charging or discharging a capacitor during a given period transduces itself linearly into a voltage. This process introduces a delay that is the time required for the charge integration and is inversely proportional to the current. The dynamic range of the input current is usually below three decades. Moreover, the capacitor is a critical device as its capacitance should be voltage-independent.

(2) Characteristic of drain-to-source voltage versus drain current of a MOS transistor biased in the triode region. The equivalent resistance in this region is almost constant when the drain-to-source voltage is small, so it can be used for a linear current-to-voltage conversion. The conversion gain (output voltage over input current) is low, about a couple of milli-volts per micro-ampere. Thus, an input current varying in a nano-ampere range cannot be correctly converted. Furthermore, as the output voltage signal is small, an amplifier is usually required.

(3) Characteristic of gate-to-source voltage versus drain current of a MOS transistor biased in the saturation region. This feature makes a logarithmic conversion. The conversion gain of a logarithmic converter is of the order of one hundred millivolts per decade of current. Moreover, the logarithmic compression reduces the chance to detect current derivatives.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a method and circuit for the realization of a highly sensitive current detector operational in a very wide dynamic range and capable of performing linear and high-gain current-to-voltage conversions. The detection can be done in a linear and a non-linear mode of operation of the circuit, combining the advantages of high-gain in a linear conversion and large dynamic range in a logarithmic conversion in one circuit.

Another object of the invention is to provide a circuit with a simple structure composed of a minimum number of transistors on-chip for efficient current to voltage conversion. The circuit does not require any off-chip capacitors or resistors, and is capable of operating in a linear mode on a single clock.

Yet another object of the current invention is to introduce minimal delay into a current-to-voltage conversion, while allowing an input current varying in a nano-ampere, or even sub-nano, range to be correctly converted.

In accordance with a first aspect of the present invention, there is provided a method for adapting a three-terminal semiconductor device having an operating point and used for current-to-voltage conversion, to a variation of input current level in order to maintain the operation of the device in the linear portion of a curve belonging to a family of i-v curves selected in response to a bias voltage and comprising a linear and a non-linear portion. The three-terminal semiconductor device has an input current terminal, a bias terminal, and a common terminal. A bias voltage between the bias terminal and common terminal controls the current flow between the input current terminal and the common terminal.

The method comprises steps of setting the bias voltage to a preset value in order to position the operating point of the device to an initial value, detecting a change in level of the direct current component of an input current, and adjusting the bias voltage value in response to the change in current level in order to adapt the operating point of the device to an alternate i-v curve so as to remain in the linear portion of a curve.

The current I IN of the device can be set so as to maximize the range of output voltage V OUT by situating the operating point at approximately the middle of the saturation region. Setting the bias voltage to a preset value to position the operating point can be done using a structure of two cascoded transistors, one of which is drain-gate shorted, to sample an input current.

The step of detecting a change in level of an input current can be done upon closing of a switch and the bias voltage of the semiconductor device is adjusted with respect to a newly sampled input current.

In accordance with a second aspect of the present invention, there is provided a circuit to perform current-to-voltage conversion comprising a three-terminal semiconductor device, having an input current terminal, a bias terminal, and a common terminal. A bias voltage between the bias terminal and common terminal controls the current flow between the input current terminal and the common terminal, whereby the output voltage to be measured is present at the input current terminal. The device has an operating point situated on a curve belonging to a family of i-v curves, the curves comprising a linear and a non-linear portion. The circuit also comprises circuitry to detect a level of an input current, and circuitry to adjust the bias voltage value in response to the input current level detected.

More specifically, this can be done by connecting a structure of two cascoded transistors, one of which is drain-gate shorted, to the bias voltage terminal of the three-terminal semiconductor device, and to a clocked transistor, which is connected to the input current terminal of the semiconductor device.

As an alternative, logarithmic mode can also be achieved by simply replacing the clocked transistor by a wire, an off-chip resistance, or a logic gate using a voltage-controlled switch. It is preferable for the entire circuit to reside on an integrated circuit chip but this does not exclude the possibility of having off-chip components.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood by way of the following detailed description of a preferred embodiment with reference to the appended drawings, in which:

FIG. 1 a shows a schematic view of a MOS transistor.

FIG. 1 b shows a graph of the drain current i D versus the drain-to-source V DS according to the prior art in which the equivalent drain-to-source resistance of the MOS transistor is given by r DS =∂v DS /∂i D when the gate-to-source voltage is constant.

FIG. 2 is a circuit diagram of the current-to-voltage converter according to the preferred embodiment.

FIG. 3 is a graph illustrating the quiescent point Q (V GO , V DSO , I D ) and an operating point (V GO , V OUT , i IN ) of the converting transistor T 0 . The Q point is set by a reference current I D . If the current changes from I D to i IN while V GO remains unchanged, V OUT changes from V DSO to V OUT . We have r DS =(V OUT −V DSO )/(i IN −I D ), which is almost constant if the converting transistor T 0 operates in the saturation region. The output voltage V OUT =r DS (i IN −I D )+V DSO is a linear function of the input current i IN .

FIG. 4 is a graph of the output voltage versus the input current in the linear conversion mode. i IN and V OUT are linearly scaled. Each V GO determines a current range in which the converting transistor T 0 operates in the saturation region and the current-to-voltage conversion is linear. The gain of the linear conversion (r DS ) increases with the decrease of V GO .

FIG. 5 is a graph of nonlinear conversion with a constant V GO . The circuit operation spans the saturation and triode regions. The conversion gain is given by mean(r DS )=(V OUT −V DSO )/(i IN −I D ) varying from point to point. When i IN changes to i IN ,|i' IN −I' D |>|i IN −I D | mean(r DS ), changes to mean(r' DS ), mean(r' DS )<mean(r DS ).

FIG. 6 is a circuit diagram of the current-to voltage converter with a unit for different implementations of the clock.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1 a and 1 b show what happens to a MOS transistor biased in saturation region with its gate-to-source voltage held constant. The equivalent drain-to-source resistance of the transistor (r DS =∂V DS /∂I D ) has a finite and almost constant value because of channel-length-modulation effect. This equivalent resistance, r DS , increases with the decrease of the gate-to-source voltage of the transistor.

The circuit diagram of the preferred embodiment for the current-to-voltage converter is illustrated in FIG. 2 . The input current i IN can be converted into the output voltage V OUT in different modes:

1/Linear mode when the NMOS switch T 3 is off and the transistor T 0 operates in the saturation region. In FIG. 3 , we can see that, assuming that the gate-to-source voltage of the transistor T 0 has been preset to V GO according to a reference current I D , the quiescent point of T 0 is at Q (V GO , V DSO , I D ). When the input current changes from I D to i IN , the operating point of T 0 will be shifted to (V GO , V OUT , i IN ). We have (V OUT −V DSO )/(i in −i D )=r DS . The variable r DS is the equivalent drain-to-source resistance of T 0 in the saturation region and it is quasi-constant with a given V GO . The output voltage is then determined by V OUT =r DS (i IN −I D )+V DSO , varying linearly with i IN .

In FIG. 4 , we can see that a given value of V GO determines a r DS and specifies a current range for a linear conversion. Assuming that the input current can vary from 1 pA to 100 μA, the variation can be covered by many adjacent ranges. In each range, the converting transistor T 0 has a constant gate-to-source voltage V GO and operates in the saturation region. The drain-to-source resistance r DS of T 0 is constant within a given range but varies from range to range. A current signal in the lowest range receives the highest r DS , i.e. the highest conversion gain. Therefore, an automatic gain control (AGC) can be realized naturally.

2/Nonlinear mode when the NMOS switch T 3 is off and the transistor T 1 overruns the saturation region while V GO is fixed. FIG. 5 shows how this nonlinear mode extends the conversion in case of a large current difference |i IN −I D |. The ratio decreases when |i IN −I D | increases. Thus, while keeping a gain of a linear conversion high for small current variations, a compressed gain is automatically applied when the current variation is large. The dynamic range of the input current is, therefore, widened by the nonlinear operation.

3/Logarithmic mode when NMOS switch T 3 is on. The loop consisting of T 0 , T 1 and T 2 ,seen in FIG. 2 , is closed. The output voltage V OUT =V GO +V GS2 , where V GS2 is the gate-to-source voltage of T 2 . As the current flowing in the transistors T 1 and T 2 is mirrored from i IN , both V GO and V GS2 vary with i IN . If the input current i IN is well below one micro-ampere, T 0 , T 1 and T 2 operate in weak inversion mode, the characteristic V OUT versus i IN will be logarithmic. If the input current i IN is in micro-ampere range, V OUT versus i IN follows square-root rule.

It should be noticed that a linear conversion can be obtained only if the input current i IN is comparable to the reference I D in terms of magnitude. Thus, implementing an adaptive process to set up a suitable quiescent point (V GO , V DSO , I D ) for an unknown current signal is a key issue in the circuit design. As an input current signal is usually composed of a small varying component superposed on a large DC component, the Q point can be set up by the input current: When T 3 is turned on, the input current creates a voltage at the node V OUT . This voltage is sampled and a corresponding V GO is established. Then, when T 3 is turned off, the sampled voltage serves to establish the reference current which adapts automatically to the input current range.

The two transistors, T 2 and drain-gate-shorted T 1 , forming a cascoded structure, function as the following:

(1) Positioning the quiescent operating point (Q point) of the converting transistor T 0 at, approximately, the middle of the saturation region to maximize the range of the output voltage V OUT . The MOS switch T 3 is on to set up the Q point. In this case, we have V DSO =V GO +V GS2 >V GO −V tn , V tn is the threshold voltage of the converting transistor T 0 and V DS =V GO −V tn is the boundary point of the saturation region (see FIG. 1 b ). Thus, in terms of drain-to-source voltage, the distance between the boundary point and the Q point is V GS2 +V tn , almost the half-range of the drain-to-source voltage of T 0 for the saturation mode.

(2) Attenuating the effect of charge injection. The MOS switch T 3 is on to set up a Q point and then is off for a current conversion. Switching T 3 off can shift the Q point. The cascoded structure of T 1 and T 2 reduces this shift. When T 3 is turned off, charge released from the channel of T 3 is injected into the connected gate node V G2 which is not the critical gate node V GO of the converting transistor T 0 . The charge injection produces a small voltage variation ΔV G2 (see the article by WILSON, W. B., MASSOUD, H. Z., SWASON, E. J., GEORGE, R. T. and FAIR, R. B.: ‘Measurement and Modeling of charge feed-through in n-channel MOS analog switches’, IEEE J. Solid-State Circuits, 1985, SC-20, pp. 1206-1213) which is then transferred to the node V GO , resulting in a variation of ΔV GO , i.e. a shift of the Q point. The voltage transfer function for small signal is given by:

(Δ V GO /ΔV G2 )=(1)/(1+( g m1 /g m2 )+( g mb2 /g m2 )+((1 /g m2 )·(1 /r 01 ∥ r*02* )))<1,

where g m1 and g m2 are, respectively, the transconductances of the T 1 and T 2 , r 01 and r 02 are their output resistances, and g mb2 is the body-transconductance of T 2 . If g m1 =n gm2 and n>1, we will have ΔV GO ≈ΔV G2 /(l+n). Thus, the voltage variation caused by the charge injection will be reduced by a factor of (l+n).

(3) Accelerating the Q point set-up. When T 3 is on, T 0 , T 1 , T 2 and T 3 form a negative feedback loop facilitating a quick establishment of V GO .

(4) Eliminating voltage variation coupling form the output node V OUT to the gate nodes of T 0 , T 1 and T 2 respectively. When T 3 is off, there is no current path connecting the node V G2 to the rest of the circuit. As CK=0, the voltage variation at the node V OUT cannot be coupled to the node V G2 . Therefore, the gate voltage V G2 is constant and so is the current flowing through the cascoded transistors T 1 and T 2 . This current determines the value of V GO . V GO is thus constant and independent of the output voltage V OUT .

The invented circuit appeals by its high conversion gain combined with a wide current range (sub-nA up to 100 μA), real-time operation, and simplicity which signifies small silicon surface and low power dissipation. Moreover, its implementation and application can be facilitated by deepening-sub-micron technology. A great importance of its applications in VLSI is anticipated, because

1) The importance of developing current-mode signal processing circuits is growing as the voltage swing is decreasing with shrinking transistor feature size. The invented circuit can be used in current signal processing, e.g. detection of current derivative. Moreover, in current mode circuits, the final signals to be outputted are voltages, high speed and simply-structured current-to-voltage converters are always needed.

2) Optical signal processing is getting more and more involved in VLSI, for instance, in CMOS image sensors or industrial robots. Photocurrents converted from luminous flux can cover a very wide range (e.g. six decades can be expected) which is difficult for an electronic circuit to match without lowering its sensitivity of signal detection. The invented circuit can perform, in a very wide range, a high-gain detection of current variation while removing the slowly varying signal component (e.g. the signal of the background). Furthermore, as the circuit is very simple, it fits large scale integration of CMOS optical sensors for high-resolution two-dimensional signal sensing and processing.

The present invention is a multi-mode current-to-voltage converter. The proposed converter can operate in a linear mode or non-linear mode. In the linear mode, the output voltage varies linearly with the variation of the input current with respect to a reference level which adapts automatically to the input current level. The conversion gain depends on the current level. The lower the current level, the higher the gain. The converter is operational in a dynamic range of sub-nano-Amperes to 100 micro-Amperes, corresponding to a range of conversion gain of IV/nA to 0.03V/uA. The conversion is performed instantaneously after the initial process for the reference set-up. If the current level is in a micro-Ampere range, the time required for the initial process is a couple of nano-seconds and the operating frequency can reach 100 MHz or more.

In the non-linear mode, the output voltage of the converter varies logarithmically with the input current. The conversion is performed without delay. The time required for the initial process is the same as that in the linear mode.

Transistor T 3 in FIG. 2 , operating as a clock transistor, can be replaced by a resistance for a slower logarithmic mode. This resistor would have to be off-chip due to its size but it could serve the same function as the clocked transistor T 3 . Another alternative to the clocked transistor is a logic inverter using a voltage-controlled switch. This component could be off-chip or on-chip. It is preferable for the entire circuit to reside on-chip but this does not exclude the possibility of using only discrete components to build the circuit and having each of these components off-chip.

An alternative to the preferred embodiment is the use of two comparators instead of transistors. For set current ranges such as those seen in FIG. 4 , the comparators would act as voltage detectors and when the voltage level is detected to be below or above an acceptable value, the bias voltage of transistor T 0 would be shifted and the operation of transistor T 0 would be described by an alternate i-v curve, maintaining the operating point of T 0 within a linear portion of an i-v curve. The comparators would replace the circuitry composed of transistors T 1 , T 2 , and T 3 .

Claims

1. A method for adapting a semiconductor device having an operating point and used for current-to-voltage conversion, to a variation of input current in order to maintain the operation of the device in a substantially linear portion of a saturation region of a curve belonging to a family of i-v curves selected in response to an input voltage and comprising a linear and an adjacent non-linear portion, wherein said semiconductor device has at least an input current terminal, a bias terminal, and a common terminal, whereby a bias voltage between said bias terminal and said common terminal controls a rate of voltage variation at said input current terminal according to said variation of input current, and the output voltage is present at said input current terminal, said method comprising:setting said bias voltage to a preset value in order to position said operating point of the device to an initial value in the saturation region; detecting a change in level of a direct current component of said input current; and adjusting the bias voltage value in response to said change in order to adapt said operating point of the device to an alternate i-v curve so as to remain in the substantially linear portion of the saturation region of a curve.

2. The method as defined in claim 1, further comprising setting the current IIN of said device so as to maximize the range of output voltage VOUT by situating said operating point at approximately a middle of a saturation region.

3. The method as defined in claim 1, wherein said step of setting said bias voltage to a preset value further comprises providing a structure of two cascoded transistors, of which one is drain-gate shorted, to position said operating point of said device.

4. The method as defined in claim 1, wherein said step of setting said bias voltage to a preset value further comprises sampling an input current to set up a corresponding bias voltage to initially set said operating point of said device.

5. The method as defined in claim 1, wherein said step of detecting a change in level of the direct current component of an input current further comprises attenuating the effect of charge injection into said device upon closing of a switch.

6. The method as defined in claim 1, wherein said steps of detecting a change in level of the direct current component of an input current and adjusting the bias voltage value in response to said change further comprises sampling a new input current to adjust said bias voltage to a new corresponding value.

7. The method as defined in claim 1, further comprising multi-mode current-to-voltage conversion, wherein an output voltage can vary linearly or logarithmically with the variation of an input current level.

8. A current-to-voltage converter circuit comprising:a semiconductor device having at least an input current terminal, a bias terminal, and a common terminal, whereby a bias voltage between said bias terminal and said common terminal controls the rate of voltage variation at said input current terminal according to the variation of input current, whereby the output voltage is present at said input current terminal, said device having an operating point situated in a substantially linear portion of a saturation region on a curve belonging to a family of i-v curves, said curves comprising a linear and an adjacent non-linear portion; and circuitry adjusting said bias voltage value in order to adapt said operating point of said device to a detected input current level, whereby said current-to-voltage converter circuit remains within a linear portion of the saturation region of said curve yielding a large voltage difference for a small change in said input current while said circuit adapts to changes in a DC component in said input current.

9. A circuit as defined in claim 8, wherein said adjusting circuitry comprises a structure of two cascaded transistors, one of which is drain-gate shorted, connected to said bias terminal of said semiconductor device, said transistors having a predetermined width/length ratio.

10. A circuit as defined in claim 8, wherein the width/length ratio of a first one of said two cascoded transistors is greater than the width/length ratio of said drain-gate shorted second transistor of said cascoded structure and the width/length ratio of said device is as small as is allowed by the technology.

11. A circuit as defined in claim 9, further comprising detecting circuitry wherein a clocked transistor is connected to a gate of a first one of said two cascaded transistors, and to said input current terminal of said semiconductor device.

12. A circuit as defined in claim 9, wherein said cascaded structure is connected to said node of said output voltage by means of a wire.

13. A circuit as defined in claim 9, wherein said cascaded structure is connected to said node of said output voltage by means of a resistor.

14. A circuit as defined in claim 9, wherein said cascaded structure is connected to said node of said output voltage by means of a logic gate using a voltage-controlled switch.

15. A circuit as defined in claim 11, wherein the width and length of said clocked transistor are the minimum allowed in the technology.

16. A circuit as defined in claim 11, wherein said circuitry resides on an integrated circuit chip.

17. A circuit as defined in claim 12, wherein said circuitry resides on an integrated circuit chip.

18. A circuit as defined in claim 13, wherein said circuitry resides on an integrated circuit chip.

19. A circuit as defined in claim 14, wherein said circuitry resides on an integrated circuit chip.