Patent Grant
12231098
This application is a 35 USC 371 national phase filing of International Application No. PCT/US2020/043067, filed Jul. 22, 2020, the disclosure of which is incorporated herein by reference in its entirety.
The technology of the disclosure relates generally to a power management apparatus.
Mobile communication devices, such as smartphones, have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.
The redefined user experience has also led to the rise of so-called wearable devices, such as smartwatches. Over time, these wearable devices have evolved from simple companion devices to mobile communication devices into full-fledged multi-functional wireless communication devices. Nowadays, most wearable electronic devices are often equipped with digital and analog circuitries capable of communicating a radio frequency (RF) signal(s) in a variety of wireless communication systems, such as long-term evolution (LTE), Wi-Fi, Bluetooth, and so on. Like mobile communication devices, wearable devices often employ sophisticated power amplifiers to amplify RF signal(s) to help improve coverage range, data throughput, and reliability of the wearable devices.
Envelope tracking (ET) is a power management technology designed to improve efficiency levels of power amplifiers. In this regard, it may be desirable to employ ET across a variety of wireless communication technologies to help reduce power consumption and thermal dissipation in wearable devices. Notably, the RF signal(s) communicated in different wireless communication systems may correspond to different modulation bandwidths (e.g., from 80 KHz to over 200 MHz). As such, it may be further desirable to ensure that the power amplifiers can maintain optimal efficiency and linearity across a wide range of modulation bandwidth.
Embodiments of the disclosure relate to a multi-mode power management apparatus. In embodiments disclosed herein, the multi-mode power management apparatus can be configured to operate in different power management modes across a wide range of modulation bandwidth (e.g., 80 KHz to over 200 MHz). The multi-mode power management apparatus includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC), which are implemented in separate dies. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management apparatus can selectively output one or more of the ET voltages and the low-frequency voltage to different stages (e.g., driver stage and output stage) of a power amplifier circuit, thus helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide range of modulation bandwidth.
In one aspect, a multi-mode power management apparatus is provided. The multi-mode power management apparatus includes a PMIC configured to generate a low-frequency current and a low-frequency voltage. The multi-mode power management apparatus also includes an ETIC. The ETIC includes a first node coupled to the PMIC. The ETIC also includes a second node coupled to the first node via a multifunction circuit. The ETIC also includes a first voltage circuit configured to generate a first ET voltage based on a first ET target voltage. The ETIC also includes a second voltage circuit configured to generate a second ET voltage based on a second ET target voltage. The ETIC also includes a control circuit. The control circuit is configured to cause the first node and the second node to output one or more of the first ET voltage, the second ET voltage, and the low-frequency voltage. The control circuit is also configured to cause the first node and the second node to output at least the low-frequency current.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments of the disclosure relate to a multi-mode power management apparatus. In embodiments disclosed herein, the multi-mode power management apparatus can be configured to operate in different power management modes across a wide range of modulation bandwidth (e.g., 80 KHz to over 200 MHz). The multi-mode power management apparatus includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC), which are implemented in separate dies. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management apparatus can selectively output one or more of the ET voltages and the low-frequency voltage to different stages (e.g., driver stage and output stage) of a power amplifier circuit, thus helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide range of modulation bandwidth.
In examples discussed herein, the multi-mode power management apparatus 10 can be configured to operate in different power management modes, depending on modulation bandwidth of the RF signal 18. In a non-limiting example, the multi-mode power management apparatus 10 operates in a first power management mode when the modulation bandwidth is greater than 160 MHz (>160 MHz), a second power management mode when the modulation bandwidth is between 1 MHz and 160 MHz (>1 MHz and ≤160 MHz), a third power management mode when the modulation bandwidth is between 120 KHz and 1 MHz (>120 KHz and ≤1 MHz), a fourth power management mode when the modulation bandwidth is between 80 KHz and 120 KHz (>80 KHz and ≤120 KHz), or a fifth power management mode when the modulation bandwidth is below 80 KHz (≤80 KHz). Thus, by operating in different power management modes based on the modulation bandwidth of the RF signal 18, the multi-mode power management apparatus 10 can maintain optimal efficiency and linearity of the multi-stage power amplifier circuit 16 across a wide range of modulation bandwidth.
The PMIC 12 is configured to generate a low-frequency voltage VDC (e.g., a constant voltage or a modulated constant voltage) and a low-frequency current IDC (e.g., a direct current or a modulated direct current). The ETIC 14 includes a first voltage circuit 28A configured to generate a first ET voltage VCCA and a second voltage circuit 28B configured to generate a second ET voltage VCCB. The ETIC 14 includes a first node 30A and a second node 30B, which may be coupled to the output stage 22 and the driver stage 20 of the multi-stage power amplifier circuit 16, respectively. The first node 30A is coupled to the first voltage circuit 28A and the PMIC 12. The second node 30B is coupled to the second voltage circuit 28B and to the first node 30A via a multifunction circuit 32 (denoted as “LDO/SW”). In a non-limiting example, the multifunction circuit 32 may include a low dropout (LDO) and a switch (not shown).
The ETIC 14 includes a control circuit 34, which can be any type of microcontroller, or a field-programmable gate array (FPGA), as an example. It should be appreciated that functionality of the control circuit 34 may be shared between multiple control circuits and/or controllers without affecting functionality and operation of the multi-mode power management apparatus 10.
The control circuit 34 is coupled to the first voltage circuit 28A, the second voltage circuit 28B, and the multifunction circuit 32. As discussed in detail below, the control circuit 34 can individually or collectively control the first voltage circuit 28A, the second voltage circuit 28B, and the multifunction circuit 32 to cause the first node 30A and the second node 30B to output one or more of the low-frequency voltage VDC, the first ET voltage VCCA, and the second ET voltage VCCB in the different power management modes. In addition, the control circuit 34 can also individually or collectively control the first voltage circuit 28A, the second voltage circuit 28B, and the multifunction circuit 32 to cause the first node 30A and the second node 30B to output at least the low-frequency current IDC in the different power management modes.
The control circuit 34 may provide a feedback signal 36 to the PMIC 12. The feedback signal 36 enables the PMIC 12 to adjust the low-frequency current IDC and/or the low-frequency voltage VDC accordingly. The control circuit 34 may be coupled to a transceiver circuit 38 that generates the RF signal 18. In this regard, the control circuit 34 may be able to determine the modulation bandwidth of the RF signal 18 and, thus, the different power management modes based on an indication 40 from the transceiver circuit 38.
In a non-limiting example, the PMIC 12 includes a multi-level charge pump (MCP) 42 configured to generate the low-frequency voltage VDC at multiple levels based on a battery voltage VBAT (e.g., 0×VBAT, 1×VBAT, or 2×VBAT). The PMIC 12 also includes a power inductor 44 configured to induce the low-frequency current IDC based on the low-frequency voltage VDC. The PMIC 12 further includes a controller 46, which can be any type of microcontroller or microprocessor, as an example. The controller 46 receives the feedback signal 36 from the control circuit 34 in the ETIC 14. Accordingly, the controller 46 can control the MCP 42 to adjust the low-frequency voltage VDC and, thus, adjust the low-frequency current IDC accordingly.
The first voltage circuit 28A includes a first voltage amplifier 48A (denoted as “vAmpA”) configured to generate a first initial ET voltage VAMPA based on a first ET target voltage VTGTA and a first supply voltage VSUPA. In this regard, the first initial ET voltage VAMPA can correspond to a time-variant voltage envelope that tracks (e.g., rises and falls) a time-variant target envelope of the first ET target voltage VTGTA. The first supply voltage VSUPA may be adjusted to cause the first voltage amplifier 48A to adjust amplitude of the first initial ET voltage VAMPA and thus adjust amplitude of the first ET voltage VCCA.
The first voltage circuit 28A also includes a first offset capacitor 50A having a first capacitance CA (e.g., 4.7 μF) coupled between the first voltage amplifier 48A and the first node 30A. The first offset capacitor 50A is configured to raise the first initial ET voltage VAMPA by a first offset voltage VOFFA (e.g., 0.8 V) to generate the first ET voltage VCCA (VCCA=VAMPA+VOFFA).
The first voltage circuit 28A also includes a first switch 52A (denoted as “SW”) coupled between a first coupling node 54A and a ground (GND). The first voltage circuit 28A further includes a first feedback loop 56A configured to provide a feedback of the first ET voltage VCCA to the first voltage amplifier 48A.
The second voltage circuit 28B includes a second voltage amplifier 48B (denoted as “vAmpB”) configured to generate a second initial ET voltage VAMPB based on a second ET target voltage VTGTB and a second supply voltage VSUPB. In this regard, the second initial ET voltage VAMPB can correspond to a time-variant voltage envelope that tracks (e.g., rises and falls) a time-variant target envelope of the second ET target voltage VTGTB. The second supply voltage VSUPB may be adjusted to cause the second voltage amplifier 48B to adjust amplitude of the second initial ET voltage VAMPB and thus adjust amplitude of the second ET voltage VCCB.
The second voltage circuit 28B also includes a second offset capacitor 50B having a second capacitance CB (e.g., 10-100 nF) coupled between the second voltage amplifier 48B and the second node 30B. The second offset capacitor 50B is configured to raise the second initial ET voltage VAMPB by a second offset voltage VOFFB (e.g., 0.8 V) to generate the second ET voltage VCCB (VCCB=VAMPB+VOFFB).
The second voltage circuit 28B also includes a second switch 52B (denoted as “SW”) coupled between a second coupling node 54B and the GND. The second voltage circuit 28B further includes a second feedback loop 56B configured to provide a feedback of the second ET voltage VCCB to the second voltage amplifier 48B.
The ETIC 14 includes a supply voltage circuit 58 configured to generate the first supply voltage VSUPA and the second supply voltage VSUPB. In a non-limiting example, the supply voltage circuit 58 can generate each of the first supply voltage VSUPA and the second supply voltage VSUPB at multiple levels to help maintain efficiency and linearity of the first voltage amplifier 48A and the second voltage amplifier 48B.
The ETIC 14 may include a first voltage equalizer circuit 60A (denoted as “VRF”) and a second voltage equalizer circuit 60B (denoted as “VRF”). The first voltage equalizer circuit 60A is configured to generate the first ET target voltage VTGTA based on a common ET target voltage VTGT. The second voltage equalizer circuit is configured to generate the second ET target voltage VTGTB based on the common ET target voltage VTGT. The common ET target voltage VTGT is so generated to have a time-variant voltage envelope that tracks (rises and falls) a time-variant signal envelope of the RF signal 18.
In one embodiment, in the first power management mode, the control circuit 34 is configured to cause the first node 30A to output the first ET voltage VCCA and the low-frequency current IDC. The control circuit 34 is also configured to cause the second node 30B to output the second ET voltage VCCB and an adjusted low-frequency current I′DC that is proportional to the low-frequency current IDC. In this regard, the driver stage 20 is receiving the second ET voltage VCCB and the adjusted low-frequency current I′DC, while the output stage 22 is receiving the first ET voltage VCCA and the low-frequency current IDC.
Notably, the RF signal 18 has been amplified by the power amplifier 24 in the driver stage 20 when the RF signal 18 reaches the output stage 22. As such, the RF signal 18 will correspond to a higher amplitude at the output stage 22 than at the driver stage 20. As such, the first ET voltage VCCA needs to be greater than or equal to the second ET voltage VCCB (VCCA≥VCCB) to prevent the RF signal 18 from being distorted at the output stage 22 (e.g., due to amplitude clipping).
More specifically, the control circuit 34 activates the first voltage amplifier 48A and the second voltage amplifier 48B to cause the first node 30A and the second node 30B to output the first ET voltage VCCA and the second ET voltage VCCB, respectively. The control circuit 34 controls the LDO regulator in the multifunction circuit 32 to generate the adjusted low-frequency current I′DC. The control circuit 34 also closes the switch in the multifunction circuit 32 to provide the adjusted low-frequency current I′DC to the second node 30B. The control circuit 34 further opens the first switch 52A and the second switch 52B to cause the first node 30A and the second node 30B to output the low-frequency current IDC and the adjusted low-frequency current I′DC, respectively.
The control circuit 34 may determine a voltage differential across the first offset capacitor 50A (e.g., a difference between VVCCA and VAMPA). The voltage differential across the first offset capacitor 50A may serve as an indication of surplus or shortfall of the low-frequency current IDC at the first node 30A. Accordingly, the control circuit 34 generates the feedback signal 36 based on the voltage differential. Accordingly, the controller 46 in the PMIC 12 can control the MCP 42 based on the feedback signal 36 to cause the low-frequency voltage VDC and the low-frequency current IDC to decrease or increase.
The control circuit 34 may determine a voltage differential across the second offset capacitor 50B (e.g., a difference between VCCB and VAMPB). The voltage differential across the second offset capacitor 50B may serve as an indication of surplus or shortfall of the adjusted low-frequency current I′DC at the second node 30B. Accordingly, the control circuit 34 may control the LDO regulator in the multifunction circuit 32 to decrease or increase the adjusted low-frequency current I′DC.
Notably, when the RF signal 18 progresses trough the driver stage 20 and the output stage 22 of the multi-stage power amplifier circuit 16, the RF signal 18 can experience a temporal delay between the driver stage 20 and the output stage 22. As a result, the RF signal 18 can experience an instantaneous amplitude variation between the driver stage 20 and the output stage 22. In this regard, the first voltage equalizer circuit 60A and the second voltage equalizer circuit 60B can be configured to delay the first ET target voltage VTGTA from the second ET target voltage VTGTB by a determined temporal delay between the driver stage 20 and the output stage 22 of the multi-stage power amplifier circuit 16. As a result, the second ET voltage VCCB will be delayed from the first ET voltage VCCA by the determined temporal delay, thus helping to accommodate the temporal delay between the driver stage 20 and the output stage 22.
In another embodiment, in the second power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output the first ET voltage VCCA and the low-frequency current IDC. Specifically, the control circuit 34 activates the first voltage amplifier 48A and deactivates the second voltage amplifier 48B to cause the first node 30A and the second node 30B to each output the first ET voltage VCCA. The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A to receive the low-frequency current IDC. The control circuit 34 further opens the first switch 52A and the second switch 52B to cause the first node 30A and the second node 30B to each output the low-frequency current IDC. The control circuit 34 is further configured to generate the feedback signal 36 based on the voltage differential across the first offset capacitor 50A.
In another embodiment, in the third power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output the second ET voltage VCCB and the low-frequency current IDC. Specifically, the control circuit 34 deactivates the first voltage amplifier 48A and activates the second voltage amplifier 48B to cause the first node 30A and the second node 30B to each output the second ET voltage VCCB. The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A to receive the low-frequency current IDC. The control circuit 34 further opens the first switch 52A and the second switch 52B to cause the first node 30A and the second node 30B to each output the low-frequency current IDC. The control circuit 34 is further configured to generate the feedback signal 36 based on the voltage differential across the first offset capacitor 50A.
In another embodiment, in the fourth power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output the low-frequency voltage VDC and the low-frequency current IDc. Specifically, the control circuit 34 deactivates the first voltage amplifier 48A and the second voltage amplifier 48B. As a result, none of the first ET voltage VCCA and the second ET voltage VCCB will be generated. The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A to receive the low-frequency current IDC. The control circuit 34 further closes the first switch 52A and opens the second switch 52B such that the low-frequency voltage VDC at the first node 30A and the second node 30B is modulated across the first offset capacitor 50A to track an average power of the RF signal 18. In this regard, the low-frequency voltage VDC can be referred to as an average power tracking (APT) voltage. The control circuit 34 is further configured to generate the feedback signal 36 based on the voltage differential across the first offset capacitor 50A and the PMIC 12 can modulate the low-frequency current IDC accordingly. As a result, both the driver stage 20 and the output stage 22 will operate based on the low-frequency voltage VDC and the low-frequency current IDC.
In another embodiment, in the fifth power management mode, the control circuit 34 is configured to cause the first node 30A and the second node 30B to each output the low-frequency voltage VDC and the low-frequency current IDC. Specifically, the control circuit 34 deactivates the first voltage amplifier 48A and the second voltage amplifier 48B. As a result, none of the first ET voltage VCCA and the second ET voltage VCCB will be generated. The control circuit 34 also disables the LDO regulator and closes the switch in the multifunction circuit 32 to couple the second node 30B to the first node 30A to receive the low-frequency current IDC. The control circuit 34 further opens the first switch 52A and closes the second switch 52B such that the low-frequency voltage VDC at the first node 30A and the second node 30B is modulated across the second offset capacitor 50B to track the average power of the RF signal 18. In this regard, the low-frequency voltage VDC is also the APT voltage. The control circuit 34 is further configured to generate the feedback signal 36 based on the voltage differential across the first offset capacitor 50A and the PMIC 12 can modulate the low-frequency current IDC accordingly. As a result, both the driver stage 20 and the output stage 22 will operate based on the low-frequency voltage VDC and the low-frequency current IDC.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2020/043067 | 7/22/2020 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2021/016350 | 1/28/2021 | WO | A |
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