MULTI-MODE VCO FOR DIRECT FM SYSTEMS

Abstract

Systems for multi-mode phase modulation are disclosed. Systems provide for direct modulation of a multi-mode voltage controlled oscillator (VCO). A fractional-N counter may be used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal. The multi-mode VCO may be characterized by a first frequency gain during operation in a first mode and by a second frequency gain during operation in a second mode where signals controlling the first and second operating modes are provided by a control circuit. The control circuit may include a switch to provide control signals to the VCO.

Description

FIELD OF THE INVENTION

The present invention relates generally to phase/frequency modulators, and more particularly, to a multi-mode architecture for direct phase/frequency modulation of a phase-locked loop.

BACKGROUND OF THE INVENTION

Phase modulation schemes are very effective and are therefore widely used in communication systems. A simple example of a phase modulation scheme is quaternary phase shift keying (QPSK). FIG. 1 shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four phase offsets. FIG. 2 shows a typical QPSK (or in-phase (I)/quadrature (Q)) modulator used to generate a phase-modulated signal. This technique relies on orthogonal signal vectors to realize the phase offsets—an inherently linear technique, since it depends solely on the matching of these orthogonal signals.

The I/Q modulator provides a straightforward approach to generating phase-modulated signals that is also suitable for more complex schemes such as wideband Code-Division Multiple Access (CDMA) and Orthogonal Frequency Division Multiplexing (OFDM) systems. It is also possible to generate the phase-modulated signals using a phase-locked loop (PLL). This approach offers reduced circuitry and lower power consumption and, as a result, finds widespread use in narrowband systems. Unfortunately, the flexibility of the voltage-controlled oscillator (VCO) within the PLL architecture is limited. This is a severe disadvantage in multi-mode systems. It would therefore be advantageous to have a flexible, multi-mode VCO for use by a phase modulator.

SUMMARY OF THE INVENTION

A very efficient system for multi-mode phase modulation is provided. Embodiments of the inventive system include circuitry for direct modulation of a multi-mode voltage-controlled oscillator (VCO) used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal.

In one aspect the present invention is directed to a phase-locked loop module which includes a multi-mode voltage-controlled oscillator for generating an output signal of a frequency determined at least in part by a control voltage. The multi-mode voltage-controlled oscillator is characterized by a first frequency gain during operation in a first mode and a second frequency gain during operation in a second mode. The phase-locked loop module also includes divider circuit for dividing the output signal to produce a frequency-divided signal. A phase/frequency detector is disposed to compare phases between an input reference signal and the frequency-divided signal and to produce at least one phase error signal. A charge pump circuit produces a charge pump signal in response to the at least one phase error signal. A loop filter produces the control voltage in response to the charge pump signal.

In another aspect the invention relates to a multi-mode voltage-controlled oscillator including a first input port, a second input port and an LC tank circuit. The LC tank circuit is configured to operate in accordance with a first frequency gain in response to a first signal received at the first input port and in accordance with a second frequency gain in response to a second signal received at the second input port.

The present invention also pertains to a multi-mode modulation apparatus comprising a phase-locked loop and a switching network. The phase-locked loop includes a multi-mode voltage-controlled oscillator configured to realize a first frequency gain in response to a first control signal and a second frequency gain in response to a second control signal. The switching network is disposed to generate the first control signal during operation in a first mode and the second control signal during operation in a second mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 shows a constellation diagram that illustrates how quaternary phase shift keying (QPSK) maps two-bit digital data to one of four offsets;

FIG. 2 shows a diagram of a typical I/Q modulator;

FIG. 3 shows a phase-locked loop (PLL) that is used to synthesize a radio frequency carrier signal;

FIG. 4 shows a mathematical model of the PLL shown in FIG. 3;

FIG. 5 shows an integration filter;

FIG. 6 shows one embodiment of a fractional-N PLL using a □□ modulator;

FIG. 7 illustrates one embodiment of a fractional-N PLL that supports direct frequency or phase modulation;

FIG. 8 shows a graph of the phase noise spectrum produced by a fractional-N PLL supporting direct modulation;

FIG. 9 shows a graph that illustrates the relationship between PLL bandwidth and modulation accuracy of a fractional-N PLL supporting direct modulation;

FIG. 10 a shows a detailed view of a voltage-controlled oscillator (VCO);

FIG. 10 b shows one embodiment of a VCO tank circuit that includes an auxiliary port to support linear phase/frequency modulation;

FIG. 11 shows the capacitance-voltage relationship for an accumulation-mode MOSFET device;

FIG. 12 shows the linear capacitance-voltage response from back to back MOSFET devices;

FIG. 13 shows one embodiment of a VCO tank circuit that includes two auxiliary ports to support direct phase/frequency modulation; and

FIG. 14 shows one embodiment of a multi-mode phase/frequency modulator.

DETAILED DESCRIPTION

FIG. 3 is a phase-locked loop (PLL) 305. The PLL 305 includes a voltage-controlled oscillator (VCO) 310, a feedback counter 320, a phase/frequency detector (P/FD) 330, a charge pump (CP) 340, and an integration filter (LPF) 350. Elements of the PLL 305 of FIG. 3 are described by the mathematical model shown in FIG. 4.

The PLL 305 uses feedback to minimize the phase difference between a very accurate reference signal and its output (RF) signal. As such, it produces an output signal at a frequency given by f_VCO=Nf_REF, where f_vco is the frequency of the VCO 310 output signal, N is the value of the feedback counter 320, and f_REF is the frequency of the reference signal.

The VCO 310 produces an output signal at a frequency set by the control voltage v_ctrl according to v_out(t)=A cos(ω₀t+K_vco∫v_ctrl(t)dt), where ω_o is the free-running frequency of the VCO 310 and K_vco is the gain of the VCO 310. The gain K_vco describes the relationship between the excess phase of the carrier Φ_out and the control voltage V_ctrl with $\frac{{\Phi }_{\mathrm{out}}\left(s\right)}{v_{\mathrm{ctrl}}\left(s\right)}=\frac{K_{\mathrm{vco}}}{s},$ where K_vco is in rads/V. The VCO 310 drives the feedback counter 320, which simply divides the output phase Φ_out by N.

When the PLL 305 is locked, the phase detector 330 and charge pump 340 generate an output signal i_CP that is proportional to the phase difference Δθ between the two signals applied to the phase detector 330. The output signal i_CP can therefore be expressed as $i_{\mathrm{CP}}\left(s\right)=K_{\mathrm{pd}}\frac{\Delta \theta \left(s\right)}{2\pi },$ where K_pd is in A/radians and Δθ is in radians.

Attention is now drawn to FIG. 5, which depicts an implementation of the integration filter 350. The integration filter 350 includes a resistor R₁ 510 and capacitors C₁ 520 and C₂ 530. As shown, the integration filter 350 transforms the output signal i_CP to the control voltage v_ctrl as follows $v_{\mathrm{ctrl}}\left(s\right)=i_{\mathrm{out}}\left(s\right)\left(\frac{{\mathrm{sR}}_1{C}_1+1}{s^2{R}_1{C}_1{C}_2+s\left(C_1+C_2\right)}\right),$ where a zero (e.g., at 1/R₁C₁) has been added to stabilize the second order system and the capacitor C₂ 530 has been included to reduce any ripple on the control voltage V_crtl. Combining the above relationships yields the composite open-loop transfer function $\mathrm{GH}\left(s\right)=K_{\mathrm{PD}}\frac{K_{\mathrm{VCO}}}{s}\left[\frac{{\mathrm{sR}}_1{C}_1+1}{s^2{R}_1{C}_1{C}_2+s\left(C_1+C_2\right)}\right],$ which includes two poles at the origin (due to the VCO 310 and the integration filter 350). The closed-loop response of the system is $T\left(s\right)=\frac{{\mathrm{NK}}_{\mathrm{PD}}{K}_{\mathrm{VCO}}\left({\mathrm{sR}}_1{C}_1+1\right)}{s^3{\mathrm{NR}}_1{C}_1{C}_2+s^{2}N\left(C_1+C_2\right)+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\left({\mathrm{sR}}_1{C}_1+1\right)},$ which includes the stabilizing zero and two complex poles. The equation T(s) describes the response of the PLL 305 to the low-noise reference signal.

The value N of the feedback counter 320 sets the output frequency of the PLL 305. Its digital structure restricts N to integer numbers. As a result, the frequency resolution (or frequency step size) of the integer-N PLL 305 is nominally set by f_REF. Fortunately, it is possible to dramatically decrease the effective frequency step by manipulating the value of N to yield a non-integer average value. This is the concept of a fractional-N PLL described with respect to FIGS. 6, 7 and 14.

FIG. 6 is a fractional-N PLL 605 that uses a ΔΣ modulator 660 to develop non-integer values of N. The ΔΣ modulator 660 advantageously pushes spurious energy (created by the changing values of the feedback counter 620) to higher frequencies to be more effectively attenuated by the integration filter 650. It can be shown that the effective value of N is simply the average value described by $N=\frac{\sum _{x=1}^{P}N\left[x\right]}{P},$ where N[x] is the sequence of values of the feedback counter 620. This expands to N[x]=N_int+n[x], where N_int is the integer part and n[x] is the fractional part of N[x]. The ΔΣmodulator 660 generates the sequence n[x], that satisfies $\frac{\sum _{x=1}^{P}n\left[x\right]}{P}=\frac{k}{M},$ where k is the input to the ΔΣ modulator 660 with resolution M. In practice, the order of the ΔΣ modulator 660 dictates the range of n[x].

The ΔΣ modulator 660 introduces quantization noise that appears at the output of the PLL 605 along with other noise sources. These noise sources all map differently to the output of the PLL 605, depending on the associated transfer function. Noise applied with the reference signal is affected by the transfer function described earlier. This transfer function is represented by $T_1\left(s\right)=\frac{{\mathrm{NK}}_{\mathrm{PD}}{K}_{\mathrm{VCO}}\left({\mathrm{sR}}_1{C}_1+1\right)}{s^3{\mathrm{NR}}_1{C}_1{C}_2+s^{2}N\left(C_1+C_2\right)+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\left({\mathrm{sR}}_1{C}_1+1\right)},$ which shows a low pass response. The above transfer function similarly shapes any noise at the output of the feedback counter 620. Noise generated by the VCO 610 is subject to a different transfer function $T_2\left(s\right)=\frac{s^{2}N\left({\mathrm{sR}}_1{C}_1{C}_2+C_1+C_2\right)}{\begin{array}{c}{s}^2{\mathrm{NR}}_1{C}_1{C}_2+\\ s\left[N\left(C_1+C_2\right)+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}{R}_1{C}_1\right]+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\end{array}},$ which shows a high pass response.

The noise at the output of the feedback counter 620 is dominated by the ΔΣ modulator 660. It creates a pseudo-random sequence n[x] possessing a quantization error approximately equal to ±½ N or $\Delta =\frac{1}{N},$ It follows that the quantization noise spectral density for this error, assuming a uniform distribution, is expressed by $e_{\mathrm{rms}}^2\left(f\right)=\frac{1}{6N^2{f}_{\mathrm{REF}}}.$ over the frequency range of dc to f_REF/2. This quantization noise is advantageously shaped by an L^th order ΔΣ modulator 660 according to DS(z)=(1−z⁻¹)^L. In the PLL 605, the feedback counter 620 acts as a digital accumulator and reduces the effects of the ΔΣ modulator 660. That is, the output phase from the feedback counter 620 depends on its previous output phase. The transfer function for the feedback counter 620 is therefore $P\left(z\right)=2\pi \frac{z^{-1}}{1-z^{-1}},$ Combining these terms shows that the output noise of the feedback counter 620 is equal to n²(f)=_rms²(f)[DS(f)]²[P(f)]², which yields $n^2\left(f\right)=\frac{2}{3}{\frac{{\pi }^2}{N^2{f}_{\mathrm{REF}}}\left[2\sin \left(\frac{\pi f}{f_{\mathrm{REF}}}\right)\right]}^L,$ and appears at the output of the PLL 605 shaped by transfer function T₁(s) presented above. Direct phase/frequency modulation further increases phase noise because an additional noise source is added to the system of FIG. 6.

FIG. 7 shows a fractional-N PLL 705 supporting direct VCO modulation. The system of FIG. 7 directly modulates the VCO 710 and thereby controls the frequency of the VCO 710. To realize phase modulation, the modulation signal PM(t) must therefore be differentiated (e.g., via a differentiator device 770) with $\mathrm{fm}\left(t\right)=\frac{d}{dt}\left[\mathrm{pm}\left(t\right)\right].$ This is due to the fundamental relationship $\theta \left(t\right)={\int }_0^{t}f\left(t\right)dt,$ which shows that frequency integrates over time.

Any noise present at the frequency modulation (FM) port of the VCO 710 appears at the output of the PLL 705 (e.g., RF signal), modified by the following transfer function $T_3\left(s\right)=\frac{s^2{\mathrm{NK}}_{\mathrm{FM}}\left({\mathrm{sR}}_1{C}_1{C}_2+C_1+C_2\right)}{\begin{array}{c}{s}^2{\mathrm{NR}}_1{C}_1{C}_2+s[N\left(C_1+C_2\right)+\\ K_{\mathrm{PD}}{K}_{\mathrm{VCO}}{R}_1{C}_1]+K_{\mathrm{PD}}{K}_{\mathrm{VCO}}\end{array}}.$ As shown in chart 800 of FIG. 8, any noise associated with an FM signal v_FM adds to the system and increases the phase noise spectrum.

The feedback of the PLL 705 naturally resists the direct phase/frequency modulation of the VCO 710. To avoid this effect, the FM signal is also applied to the feedback counter 720 through the ΔΣ modulator 760. This ideally subtracts the frequency modulation applied at the VCO 710 so that the output of the counter 720 represents only the RF carrier frequency.

Direct VCO modulation requires near exact control of the frequency of the VCO 710. This is because frequency errors produce phase deviations that accumulate with time. Fortunately, the feedback of the PLL 705 helps to reduce any frequency error. This is because the output of the VCO 710 is driven by the feedback of the PLL 705 to exactly f_VCO=Nf_REF+RMf_REF, which is also essentially equal to f_VCO=K_VCOv_ctrl+K_FMv_FM, where v_ctrl is the error signal produced by the phase/frequency detector 730, v_FM is the FM signal applied to the VCO 710, and K_FM is the gain of the VCO 710 associated with the FM signal. Consequently, the error signal v_ctrl compensates for any VCO 710 gain errors within the bandwidth of the integration filter 750.

Outside the bandwidth of the PLL 705, the effect of the feedback decreases. This makes setting the gain K_FM of the VCO 710 (“VCO gain K_FM”) to its designed value critical. As illustrated by chart 900 of FIG. 9, it also means a wider bandwidth can achieve better modulation accuracy. In the EDGE transmit system, the modulation accuracy (measured using error vector magnitude (EVM)) improves significantly as the bandwidth of the PLL 705 increases from 25 k to 75 kHz.

Calibration is required to accurately set the VCO gain K_FM. This can be accomplished by scaling the FM signal (e.g., by α in FIG. 7) to compensate for variations in the VCO gain K_FM and thereby stabilizing the K_FMv_FM product. Ideally, the VCO gain K_FM should be set low to minimize the added noise from the FM signal. This is because the VCO gain K_FM amplifies the added noise (due to circuit and quantization effects) associated with the FM signal. In practice, the VCO gain K_FM cannot be set too low as there are linearity issues as well as FM signal amplitude limits.

The K_FMv_FM product sets the range of the frequency modulation. That is, the maximum frequency deviation Δf_max is simply Δf_max=K_FMmax(v_FM), where max(v_FM) represents the peak or amplitude of the FM signal. In general, the required Δf_max for reasonable performance is about four to five times the system's symbol rate.

The design shown in FIG. 7 of the direct VCO modulation system for multi-mode applications is complicated. It requires the ability to achieve different Δf_max ranges and as such different K_FMv_FM products. In practice, the VCO gain K_FM must be set for the largest required Δf_max since the FM signal amplitude is limited. This means any different K_FMv_FM products are achieved by changing α and thereby scaling the FM signal. Unfortunately, scaling (e.g., reducing) the amplitude of the FM signal may increase the added noise in the system of FIG. 7. This can be unacceptable when the symbol rate and Δf_max change dramatically. For example, the symbol rate for GSM/EDGE is 270 ksps while it is 3.84 Msps, or about 14 times larger, for WCDMA.

The multi-mode VCO 710 provides selectable gains K_FM to optimally accommodate the different frequency modulation ranges Δf_max. This advantageously allows the amplitude of the FM signal to remain close to its maximum limit, which minimizes added noise.

A detailed view of the VCO 710 is shown in FIG. 10a. The VCO 710 oscillates at a frequency $f_{\mathrm{osc}}=\frac{1}{2\pi \sqrt{\left(L_1+L_2\right)C_{\mathrm{eq}}}},$ which is set by the resonance of the LC tank circuit shown in FIG. 10a, where C_eq is the equivalent shunt capacitance (comprised of capacitor C₁ and varactors C_2a-C_2b plus any parasitic capacitance). The equivalent capacitance C_eq may also include coarse-tuning capacitors (not shown) to subdivide the tuning range. The varactor C₂ (shown as C_2a and C_2b) allows the VCO 710, by way of the control signal v_ctrl, to be tuned to different radio frequencies.

The LC tank circuit shown in FIG. 10b includes an auxiliary port to support linear phase/frequency modulation. As illustrated in chart 1100 of FIG. 11, the LC tank circuit uses the capacitance of accumulation-mode MOSFET devices N3 and N4 to achieve linear behavior even though these devices display an abrupt response. The accumulation-mode MOSFET devices present a low capacitance C_min at applied gate-to-bulk voltages V_GB below the threshold voltage V_T while they display a high capacitance C_max at applied voltages above V_T. Capacitors C4a and C4b block the dc level present at the output of the VCO 710. Resistors Z1-Z2 provide some isolation between the gates of MOSFET devices N3 and N4.

The gate-to-bulk voltage VGB applied to each MOSFET device N3-N4 depends on the VCO's 710 output signal Asin ωt, the FM signal v_FM, and the common-mode voltage V_cm that exists at the connection of the back-to-back devices. The symmetric structure of the VCO 710 means that signals VLO+ and VLO− V1 and V2 are differential with V_LO+=A sin ωt & V_LO−=−A sin ωt, where A is the peak signal of each sinusoidal output and is the oscillation frequency. It follows then that V_C3=A sin ωt+v_FM−v_cm& V_C3=−a sin ωt+v_FM−v_cm,

which describe the gate-to-bulk voltages V_GB applied to MOSFET devices N₃ and N₄. The two MOSFET devices N₃ and N₄ connect back-to-back in the VCO 710, so their individual capacitances behave oppositely.

The modulation signal v_FM affects the MOSFET devices N3 and N4 as follows. The devices nominally present a capacitance equal to $C_{\mathrm{mid}}=C_{\mathrm{FM}}\left(v_{\mathrm{FM}}=0\right)=\frac{C_{\min }{C}_{\max }}{C_{\min }+C_{\max }}.$ As the FM signal v_FM moves positive, both MOSFET devices N₃ and N₄ reach their maximum capacitance values C_max, so that for a period of time of approximately $t=\frac{1}{\omega }{\sin }^{-1}\left(-\frac{v_{\mathrm{FM}}}{A}\right),$ the structure in FIG. 10b presents a capacitance equal to C_max/2. A similar response occurs as the FM signal moves negative, which results in the structure in FIG. 10b presenting a capacitance equal to C_min/2. It is worth noting that the structure in FIG. 10b linearizes the overall response of the accumulation-mode MOSFET devices N₃ and N₄ to yield the behavior shown in FIG. 12.

FIG. 13 depicts two auxiliary ports (VFM1 and VFM2) in the VCO 710 that each support a different frequency modulation range Δf_max. As shown in FIG. 13, the additional auxiliary port is formed by simply adding another branch of accumulation-mode MOSFET devices N5 and N6 to the resonant tank of the VCO 710.

As illustrated in FIG. 14, a simple switch network 1480 enables the FM signal to drive the multi-mode VCO 1410. One or more filters 1490 may be included to smooth the FM signal after it is scaled by α, and to attenuate any alias signals. Each mode of the VCO 1410 requires calibration to operate accurately. Since the VCO gain K_FM is constant in each of the modes, the calibration scales the FM signal by a, where different values for by α are applied for each mode. Ideally, the system illustrated in FIG. 14 produces similar FM signal amplitudes for the different modes, thus minimizing added noise. As a benefit of the present invention, the multi-mode VCO 1410 enables direct VCO modulation architecture to meet stringent phase noise and modulation accuracy requirements in vastly different modes.

Those skilled in the art can readily recognize that numerous variations and substitutions may be made in the invention, its use and its configuration to achieve substantially the same results as achieved by the embodiments described herein. Accordingly, there is no intention to limit the invention to the disclosed exemplary forms. Many variations, modifications and alternative constructions fall within the scope and spirit of the disclosed invention as expressed in the claims.

Claims

1. A phase-locked loop module, comprising: a multi-mode voltage-controlled oscillator for generating an output signal of a frequency determined at least in part by a control voltage, wherein the multi-mode voltage-controlled oscillator is characterized by a first frequency gain during operation in a first mode and a second frequency gain during operation in a second mode; a divider circuit for dividing the output signal to produce a frequency-divided signal; a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce at least one phase error signal; a charge pump circuit for producing a charge pump signal in response to the at least one phase error signal; and a loop filter which produces the control voltage in response to the charge pump signal.

2. The phase-locked loop module of claim 1, further including a switching network operative to send a first signal to a first input port of the multi-mode voltage-controlled oscillator during operation in the first mode and a second signal to a second input port of the multi-mode voltage-controlled oscillator during operation in the second mode.

3. The phase-locked loop module of claim 2, further including a differentiator device operative to apply a third signal to the divider circuit to counter the effect of the first signal and the second signal on the output signal of the multi-mode voltage-controlled oscillator.

4. The phase-locked loop module of claim 2, further including a differentiator device operative to produce the first signal and the second signal.

5. The phase-locked loop module of claim 4, wherein the differentiator device includes a gain multiplier that scales the first signal by a first value during operation in the first mode and the second signal by a second value during operation in the second mode.

6. A multi-mode voltage-controlled oscillator comprising: a first input port; a second input port; and a LC tank circuit, wherein the LC tank circuit is configured to operate in accordance with a first frequency gain in response to a first signal received at the first input port and in accordance with a second frequency gain in response to a second signal received at the second input port.

7. The multi-mode voltage-controlled oscillator of claim 6, wherein the LC tank circuit includes a first network connected to the first input port, wherein the first network includes a first plurality of elements selected to achieve the first frequency gain.

8. The multi-mode voltage-controlled oscillator of claim 7, wherein the LC tank circuit includes a second network connected to the second input port, wherein the second network includes a second plurality of elements selected to achieve the second frequency gain.

9. The multi-mode voltage-controlled oscillator of claim 8, wherein the multi-mode voltage-controlled oscillator is coupled to a differentiator device operative to produce the first signal and the second signal.

10. The multi-mode voltage-controlled oscillator of claim 9, wherein the differentiator device includes a multiplier that scales the first signal by a first value during operation in the first mode and the second signal by a second value during operation in the second mode.

11. A multi-mode modulation apparatus comprising: a phase-locked loop including a multi-mode voltage-controlled oscillator configured to realize a first frequency gain in response to a first control signal and a second frequency gain in response to a second control signal; and a switching network disposed to generate the first control signal during operation in a first mode and the second control signal during operation in a second mode.

12. The apparatus of claim 11 wherein the multi-mode voltage-controlled oscillator includes an LC tank circuit having a first input port and a second input port, the LC tank circuit being configured to operate in accordance with the first frequency gain in response to the first control signal received at the first input port and in accordance with the second frequency gain in response to the second control signal received at the second input port.

13. The apparatus of claim 12, wherein the LC tank circuit includes a first network connected to the first input port, wherein the first network includes a first plurality of elements selected to achieve the first frequency gain.

14. The apparatus of claim 13, wherein the LC tank circuit includes a second network connected to the second input port, wherein the second network includes a second plurality of elements selected to achieve the second frequency gain.