Patent Application
20240316724
A layer, a substrate, or a semiconductor wafer may be planarized using a polishing or planarizing technique such as chemical mechanical polishing/planarization (CMP). A CMP operation may include depositing a slurry (or polishing compound) onto a polishing pad. A semiconductor substrate may be mounted to and secured by a substrate carrier, which may rotate the semiconductor substrate as the semiconductor substrate is pressed against the polishing pad. The slurry and polishing pad act as an abrasive that polishes or planarizes one or more layers (e.g., metallization layers) of the semiconductor substrate as the semiconductor substrate is rotated. The polishing pad may also be rotated to ensure a continuous supply of slurry is applied to the polishing pad.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In some cases, a semiconductor substrate may include a roll-off profile at or/near a perimeter of the semiconductor substrate. The roll-off profile may prevent the semiconductor substrate from being non-bonded to another semiconductor substrate in a semiconductor substrate stacking process. During a chemical-mechanical planarization (CMP) operation, a polishing pad including same patterns in a central region and a perimeter region may fail to sufficiently maintain the roll-off profile within a threshold that prevents inner non-bond failures from occurring during or after the semiconductor substrate stacking process. For example, a perimeter region higher than a bonding pad in the central region of a semiconductor substrate prevents the bonding pad from contacting another semiconductor substrate stacking above.
Some implementations herein describe a CMP tool including a polishing pad. The CMP tool including the polishing pad may perform a polishing operation to a semiconductor substrate. The polishing operation may generate, along a perimeter of the semiconductor substrate, a roll-off profile that satisfies a threshold. The polishing pad includes two or more regions, where each region includes a different pad surface pattern. Each region including a different pad surface pattern may correspond to a different polishing rate. Techniques using the polishing pad having such zone and pattern surface pattern combinations allow for a focused and a controlled polishing of the semiconductor substrate, including along the perimeter of the semiconductor substrate to tightly control the roll-off profile.
In this way, the roll-off profile of the semiconductor substrate may be consistently formed to improve a yield related to a semiconductor substrate stacking process. Additionally, an amount or resources needed to fabricate a volume of stacked semiconductor substrates (e.g., semiconductor manufacturing tools, materials, power, and/or supporting computing resources, among other examples) may be reduced relative to techniques that include polishing the semiconductor substrate using a CMP tool including a polishing pad with a single pattern.
The CMP tool 100 includes a transfer chamber 104 in which semiconductor substrates are transferred to and from the processing chamber(s) 102. Moreover, semiconductor substrates are transferred between the transfer chamber 104 and one or more cleaning chambers 106 included in the CMP tool 100. A cleaning chamber 106 (also referred to as a CMP cleaning chamber or a post-CMP cleaning chamber) is a component of the CMP tool 100 that is configured to perform a post-CMP cleaning operation to clean or remove residual slurry and/or removed material from a semiconductor substrate that has undergone a CMP operation. In some implementations, the CMP tool 100 includes a plurality of cleaning chambers 106, and the CMP tool 100 is configured to process a semiconductor substrate through a plurality of sequential post-CMP cleaning operations in the plurality of cleaning chambers 106. As an example, the CMP tool 100 may process a semiconductor substrate in a first post-CMP cleaning operation in a cleaning chamber 106a, may process the semiconductor substrate in a second post-CMP cleaning operation in a cleaning chamber 106b, may process the semiconductor substrate in a third post-CMP cleaning operation in a cleaning chamber 106c, and so on.
A cleaning chamber 106 cleans a semiconductor substrate using a cleaning agent such as isopropyl alcohol (IPA), a chemical solution that includes a plurality of cleaning chemicals, and/or another type of cleaning agent. The CMP tool 100 includes one or more types of cleaning chambers 106. Each type of cleaning chamber 106 is configured to clean a semiconductor substrate using a different type of cleaning device. In some implementations, a cleaning chamber 106 includes a brush-type cleaning chamber. A brush-type cleaning chamber is a cleaning chamber that includes one or more cleaning brushes (or roller brushes) that are configured to spin or rotate to brush-clean a semiconductor substrate. In some implementations, a cleaning chamber 106 includes a pen-type cleaning chamber. A pen-type cleaning chamber is a cleaning chamber that includes a cleaning pen (or cleaning pencil) that is configured to provide fine-tuned and detailed cleaning of a semiconductor substrate.
In some implementations, the cleaning chambers 106 of the CMP tool 100 are arranged such that a semiconductor substrate is first processed in one or more brush-type cleaning chambers (e.g., to remove a large amount of removed material and residual slurry from the semiconductor substrate), and is then processed in a pen-type cleaning chamber (e.g., to provide detailed cleaning of structures and/or recesses in the semiconductor substrate). As an example, the cleaning chambers 106a and 106b may be configured as brush-type cleaning chambers, and cleaning chamber 106c may be configured as a pen-type cleaning chamber.
The CMP tool 100 includes a rinsing chamber 108 that is configured to rinse a semiconductor substrate after one or more post-CMP cleaning operations. The rinsing chamber 108 rinses a semiconductor substrate to remove residual cleaning agent from the semiconductor substrate. The rinsing chamber 108 is configured to use a rinsing agent, such as deionized water (DIW) or another type of rinsing agent, to rinse a semiconductor substrate. Semiconductor substrates are transferred to the rinsing chamber 108 from a cleaning chamber 106 directly or through the transfer chamber 104. In some implementations, a semiconductor substrate is processed in a drying operation in the rinsing chamber 108, in which the semiconductor substrate is dried to prevent oxidation and/or other types of contamination of the semiconductor substrate.
The CMP tool 100 includes a plurality of transport devices 110. The transport devices 110 include robot arms or other types of transport devices that are configured to transfer semiconductor substrates between the processing chamber(s) 102, the transfer chamber 104, the cleaning chamber(s) 106, and/or the rinsing chamber 108.
As described in greater connection with
Additionally, or alternatively, the series of operations includes rotating, concurrently, a polishing head holding a semiconductor substrate about a first axis and a platen holding a polishing pad having two or more pad surface patterns about a second axis, where the platen holding the polishing pad is below the substrate carrier, where rotating the polishing head about the first axis includes rotating the polishing head about a central axis of the polishing head using a first rotational vector, and where rotating the platen about the second axis includes rotating the platen about a central axis of the platen using a second rotational vector. The series of operations includes engaging the semiconductor substrate and the polishing pad. The series of operations includes polishing, concurrently, two or more regions of the semiconductor substrate using a polishing pad.
As indicated above,
The processing chamber 102 further includes a platen 202 and a polishing pad 204. The polishing pad 204 is mounted on the platen 202 and has a polishing surface 206. The platen 202 is further coupled to a drive shaft 208.
The conditioner 210 includes a conditioning disk 212 which can be pivoted via an arm 214. The arm 214 is electrically connected to the motor assembly 240 through a shaft 216. The arm 214 is driven by the shaft 216 to move, for example, in a swing motion over a range 218 in a polishing operation (e.g., a CMP operation). Therefore, the conditioning disk 212 travels along the swing motion to condition different portions of the polishing surface 206. The conditioning disk 212 may be configured to rotate about an axis to restore asperities to the polishing surface 206 as the polishing operation makes the polishing surface 206 smoother. That is, in order to retain the material removal qualities of the polishing pad 204, the conditioning disk 212 is used to maintain roughness on the polishing surface 206 that would otherwise be lost during the polishing operation. The conditioning disk 212 carries an abrasive pad that may include, for example, a diamond abrasive.
The semiconductor substrate carrier 220 includes a polishing head 222 for mounting and securing a semiconductor substrate 224. The semiconductor substrate 224 may be mounted and secured to the polishing head 222 by a vacuum force or another type of securing force. The semiconductor substrate 224 is mounted to the polishing head 222 such that a surface of the semiconductor substrate 224 (e.g., a polishing surface, a processing surface, an active surface, a device surface) that is to be processed is orientated to face the polishing surface 206. The polishing head 222 may also be pivoted via an arm 226. The arm 226 is electrically connected to the motor assembly 240 through a shaft 228. In some implementations, the arm 226 may also be driven by the shaft 228 to move in a swing motion during the polishing operation. The polishing head 222 is configured to rotate about an axis of the polishing head 222 (e.g., an axis that is approximately perpendicular to the polishing surface 206) in the polishing operation.
The slurry system 230 includes a slurry supply 232 which can be pivoted via an arm 234. The arm 234 is electrically connected to the motor assembly 240 through a shaft 236. In some implementations, the arm 234 may also be driven by the shaft 236 to move in a swing motion in the polishing operation. The slurry system 230 can provide slurry 238 which may include an abrasive compound and a fluid such as deionized water, or a liquid cleaner such as potassium hydroxide (KOH), onto the polishing surface 206 of the polishing pad 204 before wafer planarization occurs. In an example, a flow rate of the slurry 238 may be in a range of approximately 50 milliliters (ml)/minute to approximately 350 ml/minute. However, other values for the range are within the scope of the present disclosure.
In the polishing operation, the motor assembly 240 rotates the platen 202 and the polishing pad 204 via the drive shaft 208. The slurry system 230 dispenses the slurry 238 onto the polishing surface 206. As the polishing pad 204 rotates, the conditioning disk 212 is rotated about a disk axis of the conditioning disk 212 and is driven to swing horizontally above the polishing surface 206 such that the conditioning disk 212 can condition the polishing surface 206 of the polishing pad 204. In some implementations, the conditioning disk 212 iteratively conditions the inner portions and the outer portions of the polishing surface 206. The motor assembly 240 also rotates a semiconductor substrate 224, mounted and secured by the polishing head 222, through the arm 226 and the shaft 228. A down-force is controlled by the CMP controller 250 to move the active surface of the semiconductor substrate 224 onto the polishing surface 206. In this configuration, the conditioning disk 212 scratches or roughs up the polishing surface 206 of the polishing pad 204 continuously during the CMP process to promote consistent and/or uniform polishing. The combination of motions of the conditioner 210, the polishing head 222, and the slurry system 230 planarizes the active surface of the semiconductor substrate 224 until an endpoint for the CMP process is reached, which may include a particular time duration of the CMP process, a particular amount of material removed from the semiconductor substrate 224, or another endpoint.
In some implementations, the polishing surface 206 includes a plurality of groove segments and/or geometric patterns formed by the plurality of groove segments configured in a pad surface pattern region 242 of the polishing pad 204. During the CMP process, all or a portion of the plurality of groove segments and/or geometric patterns formed by the plurality of groove segments impede a trajectory of the slurry (hereinafter referred to as a slurry trajectory). Specifically, all or a portion of the plurality of groove segments and/or geometric patterns formed by the plurality of groove segments are configured to impede a radial flow of the slurry 238 from a center 244 of the polishing pad 204 (or from an area of the polishing pad 204 in which the slurry 238 is dispensed) to a polishing pad outer edge 246. Impeding the slurry trajectory promotes retention of the slurry 238 on the polishing surface 206 of the polishing pad 204. By impeding the slurry trajectory, a retention time or duration of time the slurry is present on the polishing pad is increased. Increasing the retention of the slurry results in a more predictable and controlled CMP process and reduces slurry waste.
In some implementations, the slurry 238 is dispensed onto the pad surface pattern region 242 of the polishing pad 204. The rotation of the polishing pad 204 creates forces that direct the slurry 238 toward the polishing pad outer edge 246. Patterns formed by the plurality of in the pad surface pattern region 242 of the polishing pad 204 alters the slurry trajectory across the polishing pad 204.
In some implementations, the CMP controller 250 adjusts one or more parameters associated with the polishing operation 254 using a machine learning model. The machine learning model may include and/or may be associated with one or more of a neural network model, a random forest model, a clustering model, or a regression model, among other examples. In some implementations, the CMP controller 250 uses the machine learning model by providing candidate parameters including a rotational vector related to the platen 202, a rotational vector related to the polishing head 222, a flow rate of the slurry 238, and/or a compressive force between the polishing pad 204 and the semiconductor substrate 224, among other examples, as input to the machine learning model. The CMP controller 250 may use machine learning model to determine a likelihood, probability, or confidence that a particular outcome (e.g., a roll-off profile at a perimeter region of the semiconductor substrate 224, among other examples) for a subsequent polishing operation will be achieved using the candidate parameters. In some implementations, the CMP controller 250 provides a target roll-off profile as input to the machine learning model, and the CMP controller 250 uses the machine learning model to determine or identify a particular combination of a rotational vector related to the platen 202, a rotational vector related to the polishing head 222, a flow rate of the slurry 238, and/or a compressive force between the polishing pad 204 and the semiconductor substrate 224, among other examples, that is likely to achieve the target roll-off profile.
The CMP controller 250 (or another system) may train, update, and/or refine the machine learning model to increase the accuracy of the outcomes and/or parameters determined using the machine learning model. The CMP controller 250 may train, update, and/or refine the machine learning model based on feedback and/or results from the subsequent polishing operation, as well as from historical or related polishing operations (e.g., from hundreds, thousands, or more historical or related polishing operations performed by the CMP tool 100.
As described in greater detail in connection with
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The groove 304, the unit 306, the pore 308, and/or the asperity 310 may include a quality such as a hardness related to a selected combination of materials. Additionally, or alternatively, the groove 304, the unit 306, the pore 308, and/or the asperity 310, may include another quality such as a dimension. For example, and in some implementations, a width D1 of the pore 308 and/or the asperity 310 is included in a range of approximately 0 microns (μm) to approximately 100 μm. Additionally, or alternatively, a width D2 of the unit 306 may be included in a range of approximately 1 millimeter (mm) to approximately 5 millimeters. Additionally, or alternatively, a length D3 of the groove 304 may be included in a range of approximately 0 mm to approximately 300 mm. However, other values and ranges for the width D1, the width D2, and the length D3 are within the scope of the present disclosure.
In some implementations, a difference in a quality of the pad surface pattern 302 (e.g., a hardness of a feature, a dimension of a feature, a feature density (e.g., pattern density), an area of the pad surface pattern 302, or a location of the pad surface pattern 302, among other examples) may correspond to a different polishing rate (e.g., a different rate of material removal in angstroms (Å) per minute, among other examples) at different portions of the semiconductor substrate 224. Additionally, or alternatively, a difference in a quality of the pad surface pattern 302 may correspond to a same polishing rate at different portions of the semiconductor substrate 224. Additionally, or alternatively, a polishing rate may be dependent on rotational vectors of the platen 202 (e.g., the polishing pad 204) and/or the polishing head 222 (e.g., the semiconductor substrate 224).
As indicated above,
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Additionally, or alternatively, gradient zone 502b may extend from the center of the polishing pad 204 a radial distance D8 that is included in a range of approximately 98.0 mm to approximately 102 mm (e.g., the gradient zone 502b is a ring-shaped zone having an inner radius included in a range of approximately 38.0 mm approximately 42.0 mm and an outer radius included in a range of approximately 98.0 mm to approximately 102.0 mm). In some implementations, the gradient zone 502b includes a pad surface pattern (e.g., the pad surface pattern 302) with one or more second qualities corresponding to a second polishing rate.
Additionally, or alternatively, gradient zone 502c may extend from the center of the polishing pad 204 a radial distance D9 that is included in a range of approximately 128.0 mm to approximately 132.0 mm (e.g., the gradient zone 502c is a ring-shaped zone having an inner radius included in a range of approximately 98.0 mm to approximately 102.0 mm and an outer radius included in a range of approximately 128.0 mm to approximately 132.0 mm). In some implementations, the gradient zone 502c includes a pad surface pattern (e.g., the pad surface pattern 302) with one or more third qualities corresponding to a third polishing rate.
Additionally, or alternatively, gradient zone 502d may extend from the center of the polishing pad 204 a radial distance D10 that is included in a range of approximately 143.0 mm to approximately 147.0 mm (e.g., the gradient zone 502d is a ring-shaped zone having an inner radius included in a range of approximately 128.0 mm to approximately 132.0 mm and an outer radius included in a range of approximately 143.0 mm to approximately 147.0 mm). In some implementations, the gradient zone 502d includes a pad surface pattern (e.g., the pad surface pattern 302) with one or more fourth qualities corresponding to a fourth polishing rate.
Additionally, or alternatively, gradient zone 502e may extend from the center of the polishing pad 204 a radial distance D11 that is included in a range of approximately 148.0 mm to approximately 152.0 mm (e.g., the gradient zone 502e is a ring-shaped zone having an inner radius included in a range of approximately 143.0 mm to approximately 147.0 mm and an outer radius included in a range of approximately 148.0 mm to approximately 152.0 mm). In some implementations, the gradient zone 502e includes a pad surface pattern (e.g., the pad surface pattern 302) with one or more fifth qualities corresponding to a fifth polishing rate. In some implementations, a perimeter region of the polishing pad 204 may correspond to, or include, the gradient zone 502c.
Turning to
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In some implementations the polishing pad 204 includes two or more regions including two or more pad surface patterns. For example, as shown in
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Additionally or alternatively and as part of the series of operations 604, the motor assembly 240 may initiate a rotation of the platen 202 (e.g., the polishing pad 204) about a central axis 610 of the platen 202. The rotation of the platen 202 may correspond to a rotational vector 612 including a rotational velocity in radians per second and a direction that is clockwise, among other examples. In some implementations, the rotation of the platen 202 by the motor assembly 240, including the rotational velocity and/or direction, is based on a signal received from the CMP controller 250.
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As part of the series of operations 614, the polishing operation may concurrently polish two or more portions of the semiconductor substrate 224. Additionally, or alternatively, polishing rates for the two or more of the semiconductor substrate 224 (e.g., a polishing rate for an edge portion of the semiconductor substrate 224 and a polishing rate for a central portion of the semiconductor substrate 224, among other examples) may vary. As shown in
In some implementations, and during the series of operations 614, one or more parameters associated with the polishing operation may be adjusted. For example, the CMP controller 250 may provide a signal to the motor assembly 240 to change a parameter (e.g., a rotational velocity, a rotational acceleration, and/or a rotational direction) related to the rotational vector 608 and/or the rotational vector 612. Additionally, or alternatively, the CMP controller 250 may provide a signal to the motor assembly 240 to change a vertical force related to the vertical motion 616 and/or the vertical motion 618. As described in connection with
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Based on the materials, a polishing pad including a combination of surface patterns (e.g., the polishing pad 204 including a combination of the pad surface pattern(s) 302 as described in connection with
Using machine learning techniques described in connection with
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The bus 810 may include one or more components that enable wired and/or wireless communication among the components of the device 800. The bus 810 may couple together two or more components of
The memory 830 may include volatile and/or nonvolatile memory. For example, the memory 830 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). The memory 830 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). The memory 830 may be a non-transitory computer-readable medium. The memory 830 may store information, one or more instructions, and/or software (e.g., one or more software applications) related to the operation of the device 800. In some implementations, the memory 830 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 820), such as via the bus 810. Communicative coupling between a processor 820 and a memory 830 may enable the processor 820 to read and/or process information stored in the memory 830 and/or to store information in the memory 830.
The input component 840 may enable the device 800 to receive input, such as user input and/or sensed input. For example, the input component 840 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. The output component 850 may enable the device 800 to provide output, such as via a display, a speaker, and/or a light-emitting diode. The communication component 860 may enable the device 800 to communicate with other devices via a wired connection and/or a wireless connection. For example, the communication component 860 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.
The device 800 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 830) may store a set of instructions (e.g., one or more instructions or code) for execution by the processor 820. The processor 820 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors 820, causes the one or more processors 820 and/or the device 800 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, the processor 820 may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.
The number and arrangement of components shown in
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Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, polishing the semiconductor substrate 224 using the polishing pad 204 includes polishing the first portion of the semiconductor substrate 224 at the first polishing rate using the first region and the second portion of the semiconductor substrate at the second polishing rate using the second region.
In a second implementation, alone or in combination with the first implementation, the first polishing rate and the second polishing rate are a different polishing rate.
In a third implementation, alone or in combination with one or more of the first and second implementations, the first set of properties includes a first pattern density, and where the second set of properties includes a second pattern density that is different from the first pattern density.
In a fourth implementation, alone or in combination with one or more of the first through third implementations, the first set of properties includes a first material, and where the second set of properties includes a second material that is different from the first material.
In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the first set of properties includes a first quality related to a first groove (e.g., a first case of the groove 304), unit (e.g., a first case of the unit 306), pore (e.g., a first case of the pore 308), or asperity (e.g., a first case of the asperity 310) included in the first pad surface pattern. In some implementations, the second set of properties includes a second quality related to a corresponding second groove (e.g., second case of the groove 304), unit (e.g., a second case of the unit 306), pore (e.g., a second case of the pore 308), or asperity (e.g., a second case of the asperity 310) included in the second pad surface pattern. In some implementations, the second quality is different than the first quality.
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Process 1000 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, process 1000 includes determining, by a controller (e.g., the CMP controller 250) using a machine learning model, an adjustment to a setting controlling the first rotational vector (e.g., the rotational vector 608) or the second rotational vector (e.g., the rotational vector 612) based on a property of at least one of the two or more pad surface patterns (e.g., the pad surface patterns 302a and 302b).
In a second implementation, alone or in combination with the first implementation, process 1000 includes determining, by a controller (e.g., the CMP controller 250) using a machine learning model, an adjustment to a setting controlling a flow rate of a slurry 238 based on a property of at least one of the two or more pad surface patterns (e.g., the pad surface patterns 302a and 302b).
In a third implementation, alone or in combination with one or more of the first and second implementations, process 1000 includes determining, by a controller (e.g., the CMP controller 250) using a machine learning model, an adjustment to a setting controlling a compressive force (e.g., a vertical force related to the vertical motion 616 and/or the vertical motion 618) that engages the semiconductor substrate 224 to the polishing pad 204 based on a property of at least one of the two or more pad surface patterns (e.g., the pad surface patterns 302a and 302b).
In a fourth implementation, alone or in combination with one or more of the first through third implementations, concurrently polishing the two or more regions of the semiconductor substrate includes polishing an edge region 504 of the semiconductor substrate 224 to control a roll-off profile 700 of the edge portion.
In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the semiconductor substrate 224 corresponds to a first semiconductor substrate, the two or more portions correspond to two or more first portions further includes rotating, concurrently, the polishing head 222 holding a second semiconductor substrate about the first axis and the platen 202 holding the polishing pad 204 having two or more pad surface patterns (e.g., the pad surface patterns 302a and 302b), about the second axis, where the platen 202 holding the polishing pad 204 is below the second semiconductor substrate, where rotating the polishing head 222 about the first axis includes rotating the polishing head 222 about the central axis (e.g., the central axis 606) of the polishing head 222 using a third rotational vector, where rotating the platen 202 about the second axis includes rotating the platen 202 about the central axis (e.g., the central axis 610) of the platen 202 using a fourth rotational vector, where the third rotational vector and/or the fourth rotational vector are based on the roll-off profile 700 of the edge portion (e.g., the outer portion 504a) of the first semiconductor substrate 224, and polishing, concurrently, two or more second portions (e.g., the portions 502a-502c) of the second semiconductor substrate using the polishing pad 204.
Although
Some implementations herein describe a CMP tool including a polishing pad. The CMP tool including the polishing pad may perform a polishing operation to a semiconductor substrate. The polishing operation may generate, along a perimeter of the semiconductor substrate, a roll-off profile that satisfies a threshold. The polishing pad includes two or more regions, where each region includes a different pad surface pattern. Each region including a different pad surface pattern may correspond to a different polishing rate. Techniques using the polishing pad having such zone and pad surface pattern combinations allow for a focused and a controlled polishing of the semiconductor substrate, including along the perimeter of the semiconductor substrate to tightly control the roll-off profile.
In this way, the roll-off profile of the semiconductor substrate may be consistently formed to improve a yield related to a semiconductor substrate stacking process. Additionally, an amount or resources needed to fabricate a volume of stacked semiconductor substrates (e.g., semiconductor manufacturing tools, materials, power, and/or supporting computing resources, among other examples) may be reduced relative to techniques that include polishing the semiconductor substrate using a CMP tool including a polishing pad with a single pattern.
As described in greater detail above, some implementations described herein provide a method. The method includes receiving a semiconductor substrate onto a polishing head over a polishing pad that includes a first region and a second region, where the first region includes a first set of properties related to a pad surface pattern, where the first set of properties corresponds to a first polishing rate for a first portion of a semiconductor substrate during a polishing operation using the polishing pad, where the second region includes a second set of properties related to the pad surface pattern, where the second set of properties corresponds to a second polishing rate for a second portion of the semiconductor substrate during the polishing operation, and where the second set of properties is different from the first set of properties. The method includes polishing the semiconductor substrate using the polishing pad.
As described in greater detail above, some implementations described herein provide a method. The method includes rotating, concurrently, a polishing head holding a semiconductor substrate about a first axis and a platen holding a polishing pad having two or more pad surface patterns about a second axis, where the platen holding the polishing pad is below the substrate carrier, where rotating the polishing head about the first axis includes rotating the polishing head about a central axis of the polishing head using a first rotational vector, and where rotating the platen about the second axis includes rotating the platen about a central axis of the platen using a second rotational vector. The method includes engaging the semiconductor substrate and the polishing pad. The method includes polishing, concurrently, two or more portions of the semiconductor substrate using a polishing pad.
As described in greater detail above, some implementations described herein provide a system. The system includes a platen. The system includes a polishing pad over the platen. The polishing pad includes a first pad surface pattern occupying a first region of the polishing pad, where the first pad surface pattern corresponds to a first polishing rate for a semiconductor substrate during a polishing operation using the polishing pad. The polishing pad includes a second pad surface pattern occupying a second region of the polishing pad, where the second pad surface pattern is different from the first pad surface pattern, and where the second pad surface pattern corresponds to a second polishing rate for the semiconductor substrate during the polishing operation using the polishing pad.
As used herein, “satisfying a threshold” may, depending on the context, refer to a value being greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.
As used herein, the term “and/or,” when used in connection with a plurality of items, is intended to cover each of the plurality of items alone and any and all combinations of the plurality of items. For example, “A and/or B” covers “A and B,” “A and not B,” and “B and not A.”
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
