MULTI-PHASE CLOCK GENERATOR

Abstract

Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram for explaining a general delay locked loop (DLL);

FIG. 2 is an operation timing diagram of the DLL in FIG. 1;

FIG. 3 is a block diagram showing a multi-phase clock generator according to an embodiment of the present invention;

FIG. 4 is an operation timing diagram of the multi-phase clock generator shown in FIG. 3;

FIG. 5 is a block diagram showing a phase detector shown in FIG. 3;

FIG. 6 shows an output of a phase detector 370 when a delay time difference between a third clock signal Clock_0 and a fourth clock signal Clock_90 is 0.2T;

FIG. 7 shows an output of a phase detector 370 when a delay time difference between a third clock signal Clock_0 and a fourth clock signal Clock_90 is 0.25T;

FIG. 8 is a circuit diagram of an integrator shown in FIG. 5;

FIG. 9 is an operation time diagram of the integrator shown in FIG. 8; and

FIG. 10 is a result of a computer simulation of the multi-phase clock generator shown in FIG. 3.

Claims

1. A multi-phase clock generator comprising: a first delay line generating a first clock signal by delaying an input clock for a first delay time;a second delay line generating a second clock signal by delaying the input clock for a second delay time in response to a control signal;a phase detector detecting a phase difference between the first and second clock signals; andan up/down counter generating the control signal in response to an output of the phase detector.

2. The multi-phase clock generator of claim 1, wherein the first delay time is a fixed value and the second delay time varies according to the control signal.

3. The multi-phase clock generator of claim 1, wherein the first delay line comprises a first delay line block for outputting the first clock signal by delaying the input clock for the first delay time; andwherein the second delay line comprises a second delay line block for outputting the second clock signal by delaying the input clock for the second delay time in response to the control signal.

4. The multi-phase clock generator of claim 3, wherein the first delay line further comprises a first duty corrector block for correcting a duty of the first clock signal; andwherein the second delay line further comprises a second duty corrector block for correcting a duty of the second clock signal.

5. The multi-phase clock generator of claim 4, wherein the first delay line further comprises a first clock buffer clock for buffering the first clock signal; andwherein the second delay line further comprises a second clock buffer block for buffering the second clock signal.

6. The multi-phase clock generator of claim 1, wherein the phase detector comprises: a first NAND gate receiving the first clock signal and an inverted second clock signal;a second NAND gate receiving the second clock signal and a third clock signal;a first single-to-differential converter converting an output of the first NAND gate into first differential signals A and /A;a second single-to-differential converter converting an output of the second NAND gate into second differential signals B and /B;a first integrator performing an integration on the first differential signals in response to a control clock having a period that is two times a period of the differential signals;a second integrator performing an integration on the second differential signals in response to the control clock; anda comparator comparing outputs of the first and the second integrators,wherein the third clock signal is a signal obtained by converting a phase of the first clock signal, andwherein the control clock has a period that is two times the period of the differential signals.

7. The multi-phase clock generator of claim 6, wherein each of the first and second integrators comprises: a power source supply supplying a power source voltage in response to a bias signal;a first transmitter which is connected to the power source supply and transmits the power source voltage supplied from the power source supply to first and second nodes NA and NB in response to a differential signal Vin and a complementary differential signal /Vin;a discharge unit discharging voltage levels of the first and second nodes to a ground voltage in response to the control clock; anda second transmitter transmitting the voltage levels of the first and second nodes to the comparator in response to an inverted control clock that is obtained by inverting a phase of the control clock.

8. The multi-phase clock generator of claim 1, wherein the phase difference between the first and second clock signals is 90°.