The present invention relates to electronic circuits, and more particularly, to multi-phase interpolators and related methods.
A digital periodic clock signal is often used to sample a data signal that is transmitted to an integrated circuit from an external source. Different techniques can be used to align the rising and falling edges of the clock signal with respect to a sampling window of the data signal so that the data signal can be sampled accurately. As the clock signal frequency and the data rate increase, the sampling window decreases, and the sampling timing is more constrained. A phase interpolator circuit is an example of a circuit that can be used to generate a desired phase shift in a high frequency sampling clock signal.
A phase interpolator circuit can generate any one of a number of different phases in a periodic output signal in response to periodic input signals. A phase interpolator circuit can generate a sinusoidal output voltage signal VOUT that is a weighted sum of two sinusoidal voltage input signals, as shown in equations (1)-(3).
VOUT=(α×sin(ωt))+(β×cos(ωt))=c×sin(ωt+θ) (1)
c=√{square root over (α2+β2)} (2)
θ=arctan(β/α) (3)
The phase interpolator can generate a phase shift θ in VOUT between 0° and 360° relative to an input clock signal. A desired phase shift in VOUT can be generated by setting the values of the control codes α and β as a weighted summation of two variable current sources, such as current sources 51-52.
In the system of
The four selected clock signals CLKA, CLKB, CLKC, and CLKD determine which one of 8 different 45° wide regions RG0-RG7 between 0° and 360° the phase shift in OUT0 occurs in.
Control block 10 includes an 8-bit shift register that controls the weight current ratios of current sources 51-52 and a 3-bit counter that selects the region RG0-RG7 that the phase of OUT0 is generated in. The currents through current sources 51-52 are varied to change the phase shift of OUT0 within the selected region RG0-RG7.
According to some embodiments, a phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.
According to other embodiments, a phase interpolator circuit includes first and second transistors that are coupled to form a first differential pair and third and fourth transistors that are coupled to form a second differential pair. A first switch circuit is coupled to the first transistor and to a load circuit. A second switch circuit is coupled between the first switch circuit and the third transistor. A third switch circuit is coupled to the second transistor and to a load circuit. A fourth switch circuit is coupled between the third switch circuit and the fourth transistor. A fifth switch circuit is coupled to the first transistor and to a load circuit. A sixth switch circuit is coupled between the fifth switch circuit and the third transistor. A seventh switch circuit is coupled to the second transistor and a load circuit. An eighth switch circuit is coupled between the seventh switch circuit and the fourth transistor.
Various objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings.
Slew rate circuits 201-202 convert clock signals CLK0, CLK45, CLK90, CLK135, CLK180, CLK225, CLK270, and CLK315 into 8 periodic sinusoidal voltage waveforms S0, S45, S90, S135, S180, S225, S270, and S315. Signals S0, S45, S90, 5135, S180, S225, S270, and S315 have relative phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Slew rate circuit 201 converts clock signals CLK0, CLK90, CLK180, and CLK270 into voltage signals S0, S90, S180, and S270, respectively. Slew rate circuit 202 converts clock signals CLK45, CLK135, CLK225, and CLK315 into voltage signals S45, S135, S225, and S315, respectively. Voltage signals S0, S45, S90, S135, S180, S225, S270, and S315 are more sinusoidal in shape than the 8 input clock signals.
Sinusoidal voltage signals S0 and S180 are transmitted to inputs of multiplier circuit 203. Sinusoidal voltage signals S90 and S270 are transmitted to inputs of multiplier circuit 205. Sinusoidal voltage signals S45 and S225 are transmitted to inputs of multiplier circuit 204. Sinusoidal voltage signals S135 and S315 are transmitted to inputs of multiplier circuit 206.
Multiplier circuits 203-206 generate 8 sinusoidal single-ended output voltage signals VOP0, VON0, VOP0_NXT, VON0_NXT, VOP90, VON90, VOP90_NXT, and VON90_NXT at 8 outputs of phase interpolator 200. The 8 output voltage signals VOP0, VON0, VOP0_NXT, VON0_NXT, VOP90, VON90, VOP90_NXT, and VON90_NXT have selected phase shifts relative to clock signal CLK0/CLK180. The 8 output voltage signals form 4 differential sinusoidal output voltage signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT. Each of the differential sinusoidal output voltage signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT is generated in response to 4 of the 8 sinusoidal voltage waveforms S0, S45, S90, S135, S180, S225, S270, and S315.
The phase of signal VOP0/VON0 is 90° ahead of the phase of signal VOP90/VON90. The phase of signal VOP0_NXT/VON0_NXT is 90° ahead of the phase of signal VOP90_NXT/VON90_NXT. The phase of signal VOP0_NXT/VON0_NXT is 360°/64 behind the phase of signal VOP0/VON0. The phase of signal VOP90_NXT/VON90_NXT is 360°/64 behind the phase of signal VOP90/VON90. The phases of signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT are between 0° and 360° relative to the phase of CLK0/CLK180.
Control circuit block 210 generates digital control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B that control the current through multiplier circuits 203-206. Control signals C0B-C6B are the logical inverses (i.e., complements) of control signals C0-C6, respectively. Control signals D0B-D6B are the logical inverses (i.e., complements) of control signals D0-D6, respectively. Control signals C0-C6 and D0-D6 are transmitted to multiplier circuits 203 and 205, and control signals C0B-C6B and D0B-D6B are transmitted to multiplier circuits 204 and 206. Control circuit block 210 changes the currents through multiplier circuits 203-206 by varying the logic states of control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B. Control circuit block 210 varies the phase shifts of signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT relative to CLK0/CLK180 by changing the current through multiplier circuits 203-206. Control circuit block 210 can include, for example, a state machine, a decoder circuit, or a counter circuit.
Control circuit 210 also generates 8 digital switch control signals R0-R7. Switch control signals R0-R7 control the conductive states of switch circuits in multiplier circuits 203-206. Switch control signals R0-R7 are transmitted to multiplier circuits 203-206.
The logic states of control signals C0-C6, C0B-C6B, D0-D6, D0B-D6B, and R0-R7 determine the phase shifts between output voltage signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT and input clock signal CLK0/CLK180. Control circuit block 210 changes the logic states of one or more of control signals C0-C6, D0-D6, or R0-R7 to vary the phase shifts between CLK0/CLK180 and signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT. Phase interpolator 200 can generate 64 different phase shifts from 0° and 360° between CLK0/CLK180 and each of the differential output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT.
Load circuit 208 provides a resistive load for slew rate circuits 201-202 and for multiplier circuits 203-206. Load circuit 208 has 8 resistors. Each of the 8 resistors is coupled between a different one of the output terminals of phase interpolator 200 at VOP0, VON0, VOP0_NXT, VON0_NXT, VOP90, VON90, VOP90_NXT, and VON90_NXT and a supply voltage VCC. The resistors in load circuit 208 can be, for example, passive resistors or field-effect transistors that are configured to have constant drain-to-source resistance values.
Multiplier circuits 203-206 include 8 differential pairs of transistors formed by transistors 301-302, transistors 303-304, transistors 305-306, transistors 307-308, transistors 309-310, transistors 311-312, transistors 313-314, and transistors 315-316. Each of the 8 output terminals of multiplier circuits 203-206 that provides one of the output signals VOP0, VON0, VOP0_NXT, VON0_NXT, VOP90, VON90, VOP90_NXT, and VON90_NXT is coupled to an active or passive load resistor in load circuit 208 shown in
The logic states of switch control signals R0-R7 and current control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B determine the phase shifts between CLK0/CLK180 and the output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT.
The phase shifts between CLK0/CLK180 and VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT can be represented as angles in the rotator diagram of
Digital switch control signals R0-R7 control the conductive states of switch circuits 321-384, as shown in
At any one time, only 3 of the switch control signals R0-R7 are in logic high states, and the remaining 5 switch control signals R0-R7 are in logic low states. The 3 switch control signals R0-R7 that are in logic high states cause switch circuits 321-384 to couple each of the differential pairs of transistors in multiplier circuits 203-206 to only two of the outputs of phase interpolator 200 that generate VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT. The remaining 5 switch control signals R0-R7 that are in logic low states cause switch circuits 321-384 to decouple each of the differential pairs of transistors from the other six outputs of phase interpolator 200.
The three switch control signals R0-R7 that are in logic high states select the region of operation for the phases of VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT. For example, when switch control signals R0, R1, and R7 are in logic high states, and switch control signals R2-R6 are in logic low states, switches 321, 325, 329, 333, 337, 341, 345, 349, 353, 357, 361, 365, 369, 373, 377, and 381 are closed (i.e., conduct current), and the remaining switches in multipliers 203-206 are open (i.e., in non-conductive states). Differential pairs 301-302 and 305-306 generate differential output voltage VOP0/VON0 in response to sinusoidal input signals S0, S45, S180 and S225. Differential pairs 303-304 and 307-308 generate differential output voltage VOP0_NXT/VON0_NXT in response to sinusoidal input signals S0, S45, S180 and S225. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG0 between 0° and 45°.
Also, when control signals R0, R1, and R7 are high, differential pairs 309-310 and 313-314 generate differential output voltage VOP90/VON90 in response to sinusoidal input signals S90, S135, S270, and S315. Differential pairs 311-312 and 315-316 generate differential output voltage VOP90_NXT/VON90_NXT in response to sinusoidal input signals S90, S135, S270, and S315. Phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT within region RG2 between 90° and 135°.
When switch control signals R0, R1, and R2 are in logic high states, and switch control signals R3-R7 are in logic low states, switches 322, 326, 330, 334, 337, 341, 345, 349, 354, 358, 362, 366, 369, 373, 377, and 381 are closed, and the remaining switches in multipliers 203-206 are open. Differential pairs 301-302 and 313-314 generate differential output voltage VOP90/VON90, differential pairs 303-304 and 315-316 generate VOP90_NXT/VON90_NXT, differential pairs 305-306 and 309-310 generate differential output voltage VOP0/VON0, and differential pairs 307-308 and 311-312 generate differential output voltage VOP0_NXT/VON0_NXT. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG1 between 45° and 90°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT within region RG3 between 135° and 180°.
When switch control signals R1, R2, and R3 are in logic high states, and switch control signals R0 and R4-R7 are in logic low states, switches 322, 326, 330, 334, 338, 342, 346, 350, 354, 358, 362, 366, 370, 374, 378, and 382 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG2 between 90° and 135°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG4 between 180° and 225°.
When switch control signals R2, R3, and R4 are in logic high states, and switch control signals R0-R1 and R5-R7 are in logic low states, switches 323, 327, 331, 335, 338, 342, 346, 350, 355, 359, 363, 367, 370, 374, 378, and 382 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG3 between 135° and 180°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG5 between 225° and 270°.
When switch control signals R3, R4, and R5 are in logic high states, and switch control signals R0-R2 and R6-R7 are in logic low states, switches 323, 327, 331, 335, 339, 343, 347, 351, 355, 359, 363, 367, 371, 375, 379, and 383 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG4 between 180° and 225°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG6 between 270° and 315°.
When switch control signals R4, R5, and R6 are in logic high states, and switch control signals R0-R3 and R7 are in logic low states, switches 324, 328, 332, 336, 339, 343, 347, 351, 356, 360, 364, 368, 371, 375, 379, and 383 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG5 between 225° and 270°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG7 between 315° and 0°.
When switch control signals R5, R6, and R7 are in logic high states, and switch control signals R0-R4 are in logic low states, switches 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, and 384 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG6 between 270° and 315°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG0 between 0° and 45°.
When switch control signals R6, R7, and R0 are in logic high states, and switch control signals R1-R5 are in logic low states, switches 321, 325, 329, 333, 340, 344, 348, 352, 353, 357, 361, 365, 372, 376, 380, and 384 are closed, and the remaining switches in multipliers 203-206 are open. Phase interpolator 200 generates phase shifts in VOP0/VON0 and VOP0_NXT/VON0_NXT within region RG7 between 315° and 0°, and phase interpolator 200 generates phase shifts in VOP90/VON90 and VOP90_NXT/VON90_NXT in region RG1 between 45° and 90°.
Periodic input signals S0, S45, S90, S135, S180, S225, S270, and S315 are concurrently provided to the gates of transistors 301-316 at all times during the operation of phase interpolator 200, as shown in
The logic states of digital control signals C0-C6 determine the current through variable current sources 391B and 395B. The logic states of digital control signals C0B-C6B determine the current through variable current sources 393B and 397B. The logic states of digital control signals D0-D6 determine the current through variable current sources 392B and 396B. The logic states of digital control signals D0B-D6B determine the current through variable current sources 394B and 398B.
Each of the 8 variable current sources 391B-398B generates 8 different current values. Phase interpolator 200 generates 8 different phases in each of the output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT within each of the 8 regions RG0-RG7 by varying the currents through variable current sources 391B-398B between their 8 different current values and by varying the logic states of R0-R7. For example, the 8 current values of the variable current sources can generate phase 1, phase 2, phase 3, phase 4, phase 5, phase 6, phase 7, and phase 8 in VOP0/VON0 and VOP0_NXT/VON0_NXT between 0° and 45° within region RG0, as shown in
Phase interpolator 200 generates 64 unique phases in each of its output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT between 0° and 360° by varying the logic states of control signals R0-R7, C0-C6, D0-D6, C0B-C6B, and D0B-D6B. The current values generated by variable current sources 391B-398B are varied by changing the logic states of control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B to generate different phase shifts in output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT within each region.
In one embodiment, control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B cause the phase of VOP0_NXT/VON0_NXT to be 5.625° (i.e., 360°/64) more than the phase of VOP0/VON0. Also, in this embodiment, control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B cause the phase of VOP90_NXT/VON90_NXT to be 5.625° (i.e., 360°/64) more than the phase of VOP90/VON90.
When phase interpolator 200 transitions from one of the regions RG0-RG7 to another one of the regions, current control signals C0-C6, D0-D6, C0B-C6B, and D0B-D6B cause the currents through variable current sources 391B-398B to remain constant.
In a particular embodiment of
The logic state of each of the control signals C0-C6 determines whether one of the 7 current sources in each of variable current sources 391B and 395B is coupled to or decoupled from the corresponding differential pair of transistors 301/302 or 309/310. The logic state of each of the control signals C0B-C6B determines whether one of the 7 current sources in each of variable current sources 393B and 397B is coupled to or decoupled from the corresponding differential pair of transistors 305/306 or 313-314. The logic state of each of the control signals D0-D6 determines whether one of the 7 current sources in each of variable current sources 392B and 396B is coupled to or decoupled from the corresponding differential pair of transistors 303/304 or 311/312. The logic state of each of the control signals D0B-D6B determines whether one of the 7 current sources in each of variable current sources 394B and 398B is coupled to or decoupled from the corresponding differential pair of transistors 307/308 or 315/316.
As mentioned above, the logic state of each signal C0B-C6B is the inverse of the logic state of each signal C0-C6, respectively, and the logic state of each signal D0B-D6B is the inverse of the logic state of each signal D0-D6, respectively. Thus, if C is the maximum current generated by each variable current source 391B-398B, and variable current sources 391B and 395B are each programmed to generate a current of D, then variable current sources 393B and 397B each generate a current of C-D. If variable current sources 392B and 396B are each programmed to generate a current of F, then variable current sources 394B and 398B each generate a current of C-F.
Further details of a variable current source that can be used to implement each of the variable current sources 391B-398B in phase interpolator 200 is shown in and described with respect to FIG. 5 of commonly-assigned U.S. patent application Ser. No. 12/537,634, by Ho et al., filed Aug. 7, 2009, which is incorporated by reference herein in its entirety. Each of the constant current sources 391A, 392A, 393A, 394A, 395A, 396A, 397A, and 398A in
This embodiment improves the linearity of phase interpolator 200 at low frequency operation. This embodiment also causes the angles between adjacent phases in each of the output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, and VOP90_NXT/VON90_NXT to be closer to the same value across each region RG0-RG7 and between regions RG0-RG7.
The transfer function of phase interpolator 200 is represented by the equations below in the embodiment in which variable current sources 391B-398B in
VOUT=ƒ(α)×sin(ωt)+ƒ(β)×cos(ωt)=c(α,β)×sin(ωt+θ) (4)
θ=arctan(ƒ(β)/ƒ(α)) (5)
ƒ(β)/ƒ(α)=tan(θ)=ƒ(ƒ)=Δ (6)
In equation (4), VOUT equals one of the output signals VOP0/VON0, VOP0_NXT/VON0_NXT, VOP90/VON90, or VOP90_NXT/VON90_NXT of phase interpolator 200. In equation (5), arctan refers to the arctangent function, which is the inverse of the tangent function. In equation (6) tan refers to the tangent function. The target phase for VOUT can be obtained by controlling the two coefficients of equation (4) complementarily, as shown in equation (7).
ƒ(β)+ƒ(α)=1 (7)
Equations (8) and (9) below are obtained from equations (6) and (7), where cot refers to the cotangent function. In equations (4)-(9), 0≦ƒ(β)≦1, and 0≦θ≦π/4.
Multiplier circuit 480 shown in
The upper terminal of each of the switch circuits 421-452 shown in
Multiplier circuits 480 and 490 generate two differential output voltage signals VOP0/VON0 and VOP90/VON90. The conductive wires shown in
The logic states of the switch control signals R0-R7 and the current control signals C0-C6 and C0B-C6B determine the relative phases of output signals VOP0/VON0 and VOP90/VON90. Multiplier circuits 480 and 490 generate phases in output signals VOP0/VON0 and VOP90/VON90 in 8 regions RG0-RG7 within the rotator diagram shown in
The conductive state of each of the switch circuits 421-452 is controlled by two of the switch control signals R0-R7. When both of the switch control signals R0-R7 that control a particular one of the switch circuits 421-452 are in logic high states, the switch circuit controlled by those two switch control signals is closed. When at least one of the switch control signals R0-R7 that controls a particular one of the switch circuits 421-452 is in a logic low state, that switch circuit is open. Thus, an AND logic Boolean function is applied to the switch control signals that control switches 421-452.
The conductive states of switch circuits 461-468 are controlled by 8 switch control signals G1-G8, respectively, as shown in
When switch control signals R7 and R0-R1 are in logic high states, and switch control signals R2-R6 are in logic low states, switches 422, 424, 430, 432, 437, 439, 445, 447, 461, 463, 465, and 467 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG0 between 0° and 45°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG2 between 90° and 135°.
When switch control signals R0-R2 are in logic high states, and switch control signals R3-R7 are in logic low states, switches 425, 427, 430, 432, 438, 440, 445, 447, 462, 463, 465, and 467 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG1 between 45° and 90°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG3 between 135° and 180°.
When switch control signals R1-R3 are in logic high states, and switch control signals R0 and R4-R7 are in logic low states, switches 425, 427, 433, 435, 438, 440, 446, 448, 462, 464, 465, and 467 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG2 between 90° and 135°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG4 between 180° and 225°.
When switch control signals R2-R4 are in logic high states, and switch control signals R0-R1 and R5-R7 are in logic low states, switches 426, 428, 433, 435, 441, 443, 446, 448, 462, 464, 466, and 467 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG3 between 135° and 180°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG5 between 225° and 270°.
When switch control signals R3-R5 are in logic high states, and switch control signals R0-R2 and R6-R7 are in logic low states, switches 426, 428, 434, 436, 441, 443, 449, 451, 462, 464, 466, and 468 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG4 between 180° and 225°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG6 between 270° and 315°.
When switch control signals R4-R6 are in logic high states, and switch control signals R0-R3 and R7 are in logic low states, switches 421, 423, 434, 436, 442, 444, 449, 451, 461, 464, 466, and 468 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG5 between 225° and 270°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG7 between 315° and 0°.
When switch control signals R5-R7 are in logic high states, and switch control signals R0-R4 are in logic low states, switches 421, 423, 429, 431, 442, 444, 450, 452, 461, 463, 466, and 468 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG6 between 270° and 315°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG0 between 0° and 45°.
When switch control signals R0 and R6-R7 are in logic high states, and switch control signals R1-R5 are in logic low states, switches 422, 424, 429, 431, 437, 439, 450, 452, 461, 463, 465, and 468 are closed, and the remaining switches in multiplier circuits 480 and 490 are open. Multiplier circuits 480 and 490 generate phase shifts in VOP0/VON0 in region RG7 between 315° and 0°, and multiplier circuits 480 and 490 generate phase shifts in VOP90/VON90 in region RG1 between 45° and 90°.
The logic states of digital control signals C0-C6 determine the current through variable current sources 471B and 473B. The logic states of digital control signals C0B-C6B determine the current through variable current sources 472B and 474B. The logic state of each current control signal C0B-C6B is the inverse of the logic state of each current control signal C0-C6, respectively.
Variable current sources 471B-474B each generate 8 different current values. Multiplier circuits 480 and 490 generate 8 different phases in each of the output signals VOP0/VON0 and VOP90/VON90 within each of the 8 regions RG0-RG7 by varying the currents through variable current source 471B-474B and by varying the logic states of control signals R0-R7 and G1-G8. Multiplier circuits 480 and 490 generate 64 unique phases in each of the output signals VOP0/VON0 and VOP90/VON90 between 0° and 360° by varying the logic states of control signals R0-R7, G1-G8, C0-C6, and C0B-C6B.
The current values generated by variable current sources 471B-474B are varied by changing the logic states of control signals C0-C6 and C0B-C6B to generate different phase shifts in output signals VOP0/VON0 and VOP90/VON90. In one embodiment of
According to other embodiments, multiplier circuits 480 and 490 can be modified to generate output signals VOP0/VON0 and VOP0_NXT/VON0_NXT, or VOP90/VON90 and VOP90_NXT/VON90_NXT, or VOP0/VON0 and VOP90_NXT/VON90, or VOP0_NXT/VON0_NXT and VOP90/VON90 by connecting switch circuits 421-452 as shown in
FPGA 500 includes a two-dimensional array of programmable logic array blocks (or LABs) 502 that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs 502 include multiple (e.g., 10) logic elements (or LEs).
An LE is a programmable logic circuit block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.
FPGA 500 also includes a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks 504, blocks 506, and block 508. These memory blocks can also include shift registers and first-in-first-out (FIFO) buffers.
FPGA 500 further includes digital signal processing (DSP) blocks 510 that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs) 512 located, in this example, around the periphery of the chip, support numerous single-ended and differential input/output standards. IOEs 512 include input and output buffers that are coupled to pads of the integrated circuit. The pads are external terminals of the FPGA die that can be used to route, for example, input signals, output signals, and supply voltages between the FPGA and one or more external devices. It is to be understood that FPGA 500 is described herein for illustrative purposes only and that the present invention can be implemented in many different types of integrated circuits.
The present invention can also be implemented in a system that has an FPGA as one of several components.
System 600 includes a processing unit 602, a memory unit 604, and an input/output (I/O) unit 606 interconnected together by one or more buses. According to this exemplary embodiment, an FPGA 608 is embedded in processing unit 602. FPGA 608 can serve many different purposes within the system of
Processing unit 602 can direct data to an appropriate system component for processing or storage, execute a program stored in memory 604, receive and transmit data via I/O unit 606, or other similar functions. Processing unit 602 can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU.
For example, instead of a CPU, one or more FPGAs 608 can control the logical operations of the system. As another example, FPGA 608 acts as a reconfigurable processor that can be reprogrammed as needed to handle a particular computing task. Alternatively, FPGA 608 can itself include an embedded microprocessor. Memory unit 604 can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means.
The foregoing description of the exemplary embodiments of the present invention has been presented for the purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the present invention to the examples disclosed herein. In some instances, features of the present invention can be employed without a corresponding use of other features as set forth. Many modifications, substitutions, and variations are possible in light of the above teachings, without departing from the scope of the present invention.
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61255231 | Oct 2009 | US |