Multi-project system-on-chip and its method

Abstract

A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

Description

BRIEF DESCRIPTION OF THE CURRENT INVENTION

FIG. 1 shows the illustration of chip area for the individual realization of N SoC projects and the realization of N SoC projects using MP-SoC concept;

FIG. 2 is the overall design process flow of the current invention;

FIG. 3 is the design process flow of system architecture of one embodiment of the current invention;

FIG. 4 is the IP block design process flow of the embodiment in FIG. 3;

FIG. 5 is the logic layer design process flow of the embodiment in FIG. 3;

FIG. 6 is the solid layer design process flow of the embodiment in FIG. 3;

FIG. 7 is the system block diagram of the test chip designed from the embodiment of FIG. 3;

FIG. 8 is the system memory mapping of the test chip of FIG. 7;

FIG. 9 is the isolation mechanism of test chip of FIG. 7;

FIG. 10 is the practical implementation bench of the embodiment of FIG. 3;

FIG. 11 is the verification environment of the embodiment of FIG. 3;

FIG. 12 is the photo of test chip of FIG. 7;

FIG. 13 is the photo of test chip of ATE test diagram 7; and

FIG. 14 is the photo of test chip of test diagram 7 of experimental board.

Symbol Description of Main Components

10 System-on-chip project

12 Special IP zone

14 Share zone

20 build test environment plan

22 development system architecture

220 IP spec study

222 IP requirement

224 System memory mapping

226 Arbitration mechanism

228 Isolation mechanism

230 MP-SoC Hardware Description Language Bench

24 System spec

26 IP spec

28 Implementation bench

30 Verification environment

302 Assembler language

304 C language

306 Assembler

308 Complier

310 Object file

312 Linker

314 Executable file

316 Format conversion tool

318 ROM or Flash file format

32 IP design

320 Special IP functional requirement

322 Special IP RTL identification

324 Special IP RTL coding

326 Special IP RTL simulation

328 Add packaging circuit

330 Special IP+ packaging circuit RTL

332 System RTL simulation (Single IP)

334 IP design constraint writing

336 IP design limitation

338 Logic synthesis

34 Special IP

340 IP pre-layout gate-level netlist

342 System gate simulation (Single IP)

344 System integration

36 Logic layer design

360 System RTL simulation (For all IP)

362 System design constraints

364 Logic synthesis

366 System pre-layout gate-level netlist

368 Timing analysis

370 Timing report and SDF file

372 System gate simulation (For all IP)

38 Netlist

40 Solid layer design

400 P&R

402 Chip post-layout gate-level netlist

404 Layout drawing

406 RC extraction

408 Interconnect RC

410 Timing analysis

412 Timing report and SDF file

414 System gate-level simulation (For all IP)

416 Solid verification

42 Completed layout drawing

44 Test chip

4410 ARM922T core processor

4412 Synergistic processor

4414 External memory interface

4416 Packaging circuit

4418 Reset controller

4420 Test interface controller

4422 ME processing core

4424 MuxM2S

4426 MuxS2M

4428 ATP1

4430 ATP2

4432 AHB

4434 APB bridge

4436 A7 RISC processor

4438 SDCTIV processing core

4440 IMDCT processing core

4442 Arbitrator

4444 Decoder

4446 Internal memory

4448 AES processing core

4450 DWT processing core

4452 APB

4454 Interrupt controller

4456 Re-map/pause controller

4458 Counter

4460 MuxP2B

4462 External bus

4464 External memory

4468 Terminal simulation module

4470 Test interface driver

4472 External memory

64 2-to-1 multiplexer

68 Empty block

70 Carrier board

72 Experimental board

Claims

1. A multi-projects system-on-chip bench to be shared among multiple system-on-chip projects, comprising of: multiple silicon intellectual property blocks to be used by those system-on-chip projects as special silicon intellectual property;a bus architecture connected to those silicon intellectual property blocks so to transfer those silicon intellectual property blocks data;a shared processor connected to the bus architecture to be shared by those silicon intellectual property blocks; andan internal memory connected to the bus architecture so as to store data from those silicon intellectual property blocks, the shared processor and the bus architecture.

2. The multi-projects system-on-chip bench of claim 1 wherein it further comprising of an external interface to be connected to external device.

3. The multi-projects system-on-chip bench of claim 2 wherein the external device comprising of an external memory, a terminal simulation module and a test interface driver.

4. The multi-projects system-on-chip bench of claim 3 wherein the external memory comprising of flash, SDRAM, read-only memory and static RAM memory.

5. The multi-projects system-on-chip bench of claim 1 wherein the bus architecture comprising of system bus and peripheral bus connected respectively to system device and peripheral component.

6. The multi-projects system-on-chip bench of claim 1 wherein the bus architecture uses chip bus standards of AMBA, OPB, PLB, PIbus, PIbus2, Mbus or PalmBus.

7. The multi-projects system-on-chip bench of claim 5 wherein the system device comprising of core processor, internal memory and test interface controller module.

8. The multi-projects system-on-chip bench of claim 5 wherein the peripheral device includes counter, interrupt controller, re-map/pause controller.

9. The multi-projects system-on-chip bench of claim 1 wherein it further comprising of isolation mechanism and arbitration mechanism.

10. The multi-projects system-on-chip bench of claim 9 wherein the isolation mechanism uses multiple-to-one multiplexer.

11. The multi-projects system-on-chip bench of claim 9 wherein the arbitration mechanism includes Fixed, Round Robin, Lottery and TDM.

12. The multi-projects system-on-chip bench of claim 1 wherein the shared processor further comprising of a synergistic processor.

13. The multi-projects system-on-chip bench of claim 1 wherein the bench is a plug-and-play bench.

14. A method for designing multi-projects system-on-chip bench wherein the bench integrates multiple system-on-chip projects, it comprises of multiple silicon intellectual property blocks to be installed with special intellectual properties by those system-on-chip projects, the method comprising of the following steps: building test environment plan;developing system architecture and defining the hardware component and interface on the bench;designing an implementation bench according to the system architecture;making a verification environment according to the system architecture;planning system spec and silicon intellectual property spec according to the test environment plan and the system architecture;designing those special silicon intellectual property according to the system spec and the silicon intellectual property spec;integrating those special silicon intellectual property into the implementation bench:performing logic level design according to the integrated implementation bench for the special silicon intellectual property and generating a netlist; andperforming solid level design according to the logic level design and generating the multi-projects system-on-chip bench.

15. The method of claim 14 wherein it further comprising of the use of the test environment to test the special silicon intellectual property so as to ensure that each special silicon intellectual property can operate properly on the implementation bench.

16. The method of claim 14 wherein the development system architecture includes the following steps: studying the system requirements of those special silicon intellectual properties;building a system memory mapping according to the system requirements;planning arbitration mechanism according the system requirements; andplanning isolation mechanism according to the system requirements.

17. The method of claim 16 wherein the steps for studying the system requirements of those special silicon intellectual properties comprising of studying the needed memory space, the internal memory size and the lead count for the operation of each special silicon intellectual property.

18. The method of claim 16 wherein the steps of designing those special silicon intellectual properties are: performing individual Register Transfer Level design and generating Register Transfer Level code for the special silicon intellectual property and performing Register Transfer Level simulation for the special silicon intellectual property according to the functional requirement of the special silicon intellectual property;adding packaging circuit to the Register Transfer Level program code of the special silicon intellectual property and generating silicon intellectual property design constraints for the special silicon intellectual property according to the special silicon intellectual property spec;performing logic synthesis according to the silicon intellectual property design constraints and the Register Transfer Level program code of special silicon intellectual property which has been added with the packaging circuit so as to generate the pre-layout gate-level netlist of the special silicon intellectual property;performing system integration according to the Register Transfer Level program code of the special silicon intellectual property which has been added with packaging circuit, the silicon intellectual property design constraints and the pre-layout gate-level netlist of the silicon intellectual property.

19. The method of claim 18 wherein the steps of performing logic level design and generating a netlist comprising of: performing system Register Transfer Level simulation according to the implementation bench which integrates those special silicon intellectual properties and generating system design constraints;performing logic synthesis according to the silicon intellectual property design constraints of those special silicon intellectual properties, plus the Register Transfer Level program code of the special silicon intellectual property which has been added with packaging circuit and the silicon intellectual property pre-layout gate-level netlist of those silicon intellectual properties and generating system pre-layout gate-level netlist;performing timing analysis of pre-layout gate-level netlist of the system so as to obtain timing report and standard delay format file; andperforming system gate-level simulation by integrating the timing report and the standard delay format file into the verification environment.