1. Background of the Current Invention
This invention relates to a Multi-Project System-on-Chip (MP-SoC) bench.
2. Prior Art
Under the influence of advanced Integrated Circuited (IC) manufacturing and the automation technology of electronic design, the design technology of System-on-Chip becomes more and more practical, SoC can integrate a complete system on a single chip; meanwhile, it has much lower power, lower cost and higher speed than that of the conventional design. Among all the current SoC design researches, bench type system-on-chip design method is the most frequently used design method, bench is like the framework of a building, it is composed by overall allocation and the software and hardware Silicon Intellectual Property (IP) block interconnected on the chip. Based on the basis of good definition and well recognized system bench, the designer only needs to focus on the functional characteristics and the writing of embedded software of special silicon intellectual property block, therefore, even a small scale design team can design a complete system-on-chip.
Although it is very useful for the researchers of academic system-on-chip to use bench type system-on-chip design method, however, due to high production cost, the design plan of academic system-on-chip is very difficult to have chance for the implementation of silicon prototype. The system-on-chip designed in academy usually occupies very large chip area, most of the devices in such system-on-chip, for example, microprocessor, internal memory, bus architecture and output/input port, etc. are all designed by third person, therefore, under the consideration of limited budget, such system-on-chip has very low chance of implementation, only Virtual Prototyping verification or Rapid Prototyping verification can be used to verify SoC, for example, Seamless CVE software of Mentor Graphics and ConvergenSC software of CoWare, wherein virtual prototyping verification of system-on-chip is performed through the providing of software and hardware co-verification environment, moreover, for products such as Virtex II of Xilinx, Nios II of Altera and System Explorer MP4CF of Aptix, the prototype physical implementation of system-on-chip is performed through the providing of FPGA hardware development system which comprises of embedded processor, however, such two verification methods eventually can not provide real SoC verification. In order to meet the strong demand of the implementation of SoC, Multi-Project Chip (MPC) service is thus adopted by many organizations such as: National Applied Research Laboratories, National Chip Implementation Center (CIC) in Taiwan, CMP in France, IDEC in Korea, the idea is executed through the concept of the share of photo mask so that the photo mask and chip manufacturing cost is reduced, however, MPC service still can not reach the reduction in silicon area for the realization of single system-on-chip.
Therefore, a multi-project system-on-chip bench which integrates multiple SoC projects in order to reduce the silicon area and average cost of each SoC project is thus desired.
One purpose of the current invention is to propose a MP-SoC bench so that devices such as: microprocessor, bus can be used by multiple system-on-chip projects.
Another purpose of the current invention is to integrate multiple system-on-chip projects into a MP-SoC so that the average cost of each system-on-chip can be reduced.
Yet another purpose of the current invention is to provide a design method for MP-SoC.
According to the current invention, a MP-SoC bench (including microprocessor, chip bus architecture, memory, peripheral devices and output/input port, etc.) is shared among many SoC projects, therefore, the silicon area and manufacturing cost of single SoC project can be obviously reduced. In addition, this invention further proposes a design method for MP-SoC bench in order to help the designer to manage current data and install verification environment effectively in each design process flow level.
Since it will needs some additional chip area for the real integration of N special IP zone 12, therefore, the following formula is used to further explain it:
Assume there is a total of N SoC projects, Atotal means the total area needed to realize individually N SoC projects; Ashared means the shared device area in each SoC project, that is, the future available area on the bench; AIP,I means the special IP area of ith SoC project; Aoverhead1,I means the additional area needed to integrate the special IP of ith SoC project into individual SoC. Based on the above assumption, the area Atotal needed to realize individually N SoC projects is
If MP-SoC concept is used to design these N SoC projects, through the shared SoC bench area (Ashared), the entire chip cost will be reduced by about (N−1)×Ashared area units, however, the additional area needed Aoverhead2,I to integrate the special IP of ith SoC project will need to be taken into account, therefore, we can obtain the MP-SoC area needed AMP-SoC by using MP-SoC concept to realize N SoC projects, this is as in formula 2, the saved area Asaving is as shown in formula 3
Therefore, the rate of area saved Rsaving is
Aoverhead,I is the difference between Aoverhead2,I and Aoverhead1,i, we can know from formula 4 that the larger the N value, the more the chip area saved. For example, put the assumption in
When there are 8 SoC projects to be integrated, that is, N=8, according to formula 5, we can obtain area saving rate of 66%. We know from the above description that the share of a bench through MP-SoC concept, the average cost of each SoC project can be greatly reduced.
Since each MP-SoC system needs to integrate multiple SoC projects and each SoC project further comprising of individual software and hardware, the design and verification work of MP-SoC system is thus more difficult and time-consuming than that of normal SoC design, therefore, how to integrate and manage the automation software tool of electronic design to be used for the design of MP-SoC system and how to build a complete and easy-to-use MP-SoC design and verification environment and process flow has become the top priority task. In order to let user to add, delete, revise and verify the feasibility of software and hardware fast and easily, bench type SoC design is adopted in the current invention, however, if the conventional bench type SoC design method is adopted directly to realize MP-SoC system, there are still many difficulties in verification and integration, thus, in order to solve these issues, this invention integrates automation software tool of electronic design and develops MP-SoC design process flow as in
According to the process flow in
After the completion of logic level design 36 of the current embodiment is completed, enter the physical level design 40 process flow as in
After the above process flows, a test chip 44 is designed in the current embodiment, its system block diagram is as shown in
In order to meet low cost design consideration, test chip 44 adopts shared memory architecture in order to reduce the cost occupied by the memory,
Since test chip 44 integrates several special IP, appropriate isolation and arbitration mechanism are thus needed so that each special IP will not affect each other which in turn might lower the system performance, the first thing that needs to be considered is the abnormal need from the Master device of bus. Please refer to
The implementation bench of the current embodiment is as shown in
In the test chip aspect, two methods are used to test in the current embodiment, the first test uses Agilent 93000 ATE, this test method is to input the acquired test vector of simulation process to the chip and compare the simulation result at the output leads.
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