Patent Application
20250140177
The present disclosure relates to a display and more specifically to a display having pixels that each include a group of subpixels configured to radiate light in various colors.
A display may project information in a range of colors by transmitting component colors, such as red, green, and blue, in different proportions at each pixel. To accomplish this color display, each pixel may include a group of subpixels, each including a light emitting diode configured to radiate light in one of the component colors. The light emitting diodes for each subpixel may be made very small so that high-resolution displays may be fabricated for mobile applications (e.g., smart watches, augmented reality glasses/visors, etc.) in which the area of the display is relatively small. For these mobile applications, the power consumed by the display is an important consideration.
The present disclosure describes a subpixel group that can be used in a high-resolution display. Multiple power rails tuned for each light emitting diode may increase the efficiency of the subpixel group, while the use of a well rail for transistors in the subpixel group may decrease its physical area.
In some aspects, the techniques described herein relate to a subpixel group for a display including: a plurality of power rails configured to supply rail voltages to a plurality of light emitting diodes; a plurality of drive transistors, each drive transistor coupled in series between a power rail and a light emitting diode; and a well rail coupled to a body terminal of each drive transistor, the well rail configured to supply a bulk voltage to the body terminal of each drive transistor, the bulk voltage being greater than the rail voltages supplied by the plurality of power rails.
In some aspects, the techniques described herein relate to a display including: a plurality of subpixel groups, each subpixel in each subpixel group including: a current-source transistor; a light emitting diode; and a drive transistor coupled between the current-source transistor and the light emitting diode; a plurality of power rails, each power rail configured to supply a rail voltage to one subpixel in each subpixel group, wherein not all rail voltages supplied by the plurality of power rails are equal; and a well rail configured to supply a bulk voltage to each drive transistor of each subpixel, the bulk voltage being higher than any rail voltage supply by the plurality of power rails.
In some aspects, the techniques described herein relate to a method for controlling a subpixel group for a display, the method including: coupling subpixels in the subpixel group to respective power rails; configuring the respective power rails to supply rail voltages corresponding to light emitting diodes of the subpixel group; controlling drive transistors to conduct drive currents to illuminate the light emitting diodes, each drive transistor coupled between a power rail and a light emitting diode of a subpixel, coupling body terminals of each drive transistor to a well rail for the subpixel group; and configuring the well rail to supply a bulk voltage to the body terminals, the bulk voltage being greater than the rail voltages supplied by the respective power rails.
The foregoing illustrative summary, as well as other exemplary objectives and/or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.
The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.
A display may include millions of light emitting diodes (LEDs), each having dimensions that are a few micrometers (i.e., micro-LEDs). Each pixel in the display may be a group of subpixels (i.e., subpixel group), and the subpixels may be configured to radiate light in different colors (i.e., color channels). The intensities of the color channels may be adjusted relative to one another to generate different colors to an observer. A high resolution (e.g., 8K resolution) display can control thousands of pixels (i.e., subpixel groups) to generate binary images (i.e., bit planes) in rapid succession to render grayscale levels for each color channel. One technical problem with these displays is the cumulative power consumed to render high-resolution images/video may be too high for some battery-operated devices (e.g., head-mounted device). These battery-operated devices may also require the display to have small dimensions (e.g., less than a centimeter). Another technical problem with these displays is maintaining these small dimensions when power-saving features are added. The disclosed display includes a backplane that addresses both of these technical problems so that the disclosed display can be relatively small and consume relatively low power. One technical effect of this solution is a longer operating life for battery-operated devices using the disclosed display.
Each subpixel 101 includes a light emitting diode (LED 102) and a memory cell 103. The memory cell 103 can be configured to store a 1-bit binary value (i.e., 1, 0) and the ON/OFF condition of the LED 102 can correspond to the binary value. In a possible implementation, the memory cell 103 is a static random access memory cell (i.e., SRAM cell).
Control of the LED 102 can be carried out by a write operation to the memory cell 103. After the write operation, the memory cell 103 cell may maintain the LED 102 in the ON condition or the OFF condition with very little power consumed. A write operation may include transmitting a word line signal, which couples the memory cells of a row of pixels to respective bit lines. The write operation may further include transmitting the binary information required for each subpixel in the (activated) row to respective bit lines. In this way, an image may be rendered row-by-row.
The display 100 can include a current source 121 powered by a power supply 111 configured to supply current to illuminate the LEDs of the pixels in the ON condition. The display 100 can further include a controller 130. The controller may receive an image and may be configured (e.g., software instructions) to provide the timing and signals necessary to render the image on the array 150. The display 100 further includes a word line decoder 110 that can include logic and routing circuitry configured to convey the word line signals from the controller 130 to the proper rows of the array 150. The display 100 may further include a word line driver 116 that includes amplifiers for each word line configured to amplify and buffer the word line signals. The display 100 further includes a bit line decoder 120 that can include logic, routing, and possibly buffering circuitry configured to convey the bit line signals from the controller 130 to the proper columns of the array 150. The display 100 may further include a bit line driver 126 that includes amplifiers for each bit line configured to amplify and buffer the bit line signals.
The red subpixel includes a first LED (e.g., red LED 231) configured to radiate light (e.g., red light) when coupled to a first current source 211 by a first switch 221 (e.g., first transistor). The first switch 221 is controlled by a state of a first SRAM 251. The first current source 211 is configured to supply a first drive current (i.e., red drive current (ID_R)) at a level specific to (i.e., set for) the red LED 231. For example, the level of the red drive current may be based on brightness and/or a wavelength of the red light emitted by the red LED 231. The red subpixel is powered by a first power rail 201. A first rail voltage (VLED_R) of the first power rail 201 is specific to (i.e., set for) the red LED 231. For example, the first rail voltage (VLED_R) may be at least a first forward voltage (VR) of the red LED 231 when the red LED 231 is in the ON condition (i.e., illuminated).
From
The green subpixel includes a second LED (e.g., green LED 232) configured to radiate light (e.g., green light) when coupled to a second current source 212 by a second switch 222 (e.g., second transistor). The second switch 222 is controlled by a state of a second SRAM 252. The second current source 212 is configured to supply a second drive current (i.e., green drive current (ID_G)) at a level specific to (i.e., set for) the green LED 232. For example, the level of the green drive current may be based on brightness and/or a wavelength of the green light emitted by the green LED 232. The green subpixel is powered by a second power rail 202. A second rail voltage (VLED_G) of the second power rail 202 is specific to (i.e., set for) the green LED 232. For example, the second rail voltage (VLED_G) may be at least a second forward voltage (VG) of the green LED 232 when the green LED 232 is in the ON condition (i.e., illuminated).
The blue subpixel includes a third LED (e.g., blue LED 233) configured to radiate light (e.g., blue light) when coupled to a third current source 213 by a third switch 223 (e.g., third transistor). The third switch 223 is controlled by a state of a third SRAM 253. The third current source 213 is configured to supply a third drive current (i.e., blue drive current (ID_B)) at a level specific to (i.e., set for) the blue LED 233. For example, the level of the blue drive current may be based on brightness and/or a wavelength of the blue light emitted by the blue LED 233. The blue subpixel is powered by a third power rail 203. A third rail voltage (VLED_B) of the third power rail 203 is specific to (i.e., set for) the blue LED 233. For example, the third rail voltage (VLED_B) may be at least a third forward voltage (VB) of the blue LED 233 when the blue LED 233 is in the ON condition (i.e., illuminated).
Each LED may be a micro-LED having a different forward voltage. For example, the first forward voltage (VR) of the red LED 231 may not equal either the second forward voltage (VG) of the second LED (i.e., green LED 232) or the third forward voltage (VB) of the third LED (i.e., blue LED 233). In a possible implementation, the first forward voltage (VR) is less than the second forward voltage (VG), and the third forward voltage (VB). In another possible implementation, the second forward voltage (VG) is equal to the third forward voltage (VB) but not equal to the first forward voltage (VR). In another possible implementation, each forward voltage is different (e.g., VR≠VG≠VB). Accordingly, for the subpixel group to operate most efficiently, each subpixel can have a dedicated power rail. As shown, the red subpixel is powered by the first power rail 201, the green subpixel is powered by the second power rail 202, and the blue subpixel is powered by the third power rail 203. The rail voltages of each of the power rails may be different and each may be relative to a common lower rail (i.e., a common cathode rail (CCR 254)).
The subpixel 300 further includes a series connection including a drive transistor 320 coupled between the current-source transistor 322 and the light emitting diode 344. As shown, the drive transistor 320 can be a PMOS transistor. A source terminal of the drive transistor 320 is coupled to a drain terminal of the current-source transistor 322 and a drain terminal of the drive transistor 320 is coupled to an anode of the light emitting diode 344.
The series connection receives a rail voltage (VLED) supplied by a power rail 301, and the drive current (ID) flows through the light emitting diode 344 to a CCR 333 (e.g., ground) when the drive transistor 320 is configured in an ON condition (i.e., conducting). The drive transistor 320 can be configured ON or OFF by a SRAM cell 310 coupled (at an output) to a gate terminal (G) of the drive transistor 320.
The SRAM cell 310 may be powered by power rails that are the same or different as the series connection. As shown, the SRAM cell 310 includes a latch circuit 315 configured to output an upper rail voltage 311 (VDD) in a first state and a lower rail voltage 312 (VSS) in a second state. A gate terminal (G) of the drive transistor 320 can receive the voltage corresponding to the state of the latch circuit and turn ON (i.e., conduct) or OFF (i.e., not conduct) in response. Being p-type, the drive transistor 320 may be OFF when the latch circuit 315 is in the first state 390 and the drive transistor 320 may be ON when the latch circuit 315 is in the second state 391.
The state of the latch circuit 315 can be controlled by bit line signals (BL+, BL−) transmitted over a bit line 317 to the subpixel 300. The bit lines may be coupled to the latch circuit 315 by switches controlled by a word line signal transmitted over a word line 314 to the subpixel 300.
The current-source transistor 322 and the drive transistor 320 include body terminals (B), which are coupled to a common well in a substate in which the p-type transistors are fabricated. As will be discussed, the common well is shared by the transistors so that they can be fabricated closer together than if they each had their own well. A bulk voltage (VB) may be supplied to the body terminals by a well rail 302. To ensure proper operation, the bulk voltage (VB) should be at least equal to the rail voltage (VLED) when the transistors share a common well.
The body terminal 413 of the current-source transistor 322 is coupled directly to the common well 410. As a result, a bulk voltage (VB) applied to the body terminal 413 is transmitted to the common well 410. The body terminal 423 of the drive transistor 320 is also coupled directly to the common well 410. As a result, if a voltage other than the bulk voltage were applied to the body terminal 423, then a current would be generated in the common well 410. To prevent this current from disrupting operation and/or causing damage, the body terminals are coupled together to the well rail 302.
Returning to
As shown in
Using a power rail for each subpixel allows for the rail voltage supplied by the power rails to be the same (i.e., equal) or different (i.e., not equal). As a result, each power rail may have a rail voltage that corresponds to (e.g., is offset by a fixed amount above) the forward voltage of the LED of the subpixel. The customized rail voltage for each subpixel prevents using a higher voltage than necessary to power the subpixel, which could waste power. In other words, the rail voltage supplied by the power rails can reduce the power consumed by each subpixel group 600. In a possible implementation, the power rails are coupled to (i.e., shared by) the subpixel groups of a display so that subpixels of a common type (e.g., red, green, blue) are supplied with the same rail voltage. In this case, the rail voltage may be at a level that also accommodates variations in the forward voltage of the subpixels.
The subpixel group 600 further includes a well rail 670 coupled to a body terminal of each transistor of the subpixel group 600. The well rail 670 is configured to supply a bulk voltage to the transistors (e.g., drive transistors, current-source transistors) of the subpixel group 600. The bulk voltage can be made greater than the rail voltages of the subpixels so that the transistors may be fabricated closer together on a substrate, thereby minimizing the physical dimensions (e.g., area) of the subpixel. In a possible implementation, the subpixel separation (i.e., pitch) is less than 5 microns. In a possible implementation, the bulk voltage is greater than or equal to the maximum rail voltage of the power rails. Connecting the body terminals allows the transistors (e.g., p-type transistors) to be fabricated within a common well (e.g., n-type common well) of a substrate. The bulk voltage being greater than the rail voltages prevents a body diode within a common well of the substrate from being forward biased. In a possible implementation, the well rail is coupled to (i.e., shared by) the subpixel groups of a display so that the transistors of the subpixels receive the same bulk voltage. In this case, the bulk voltage may be at a level that also accommodates variations in the rail voltages.
The subpixel group 600 further includes a plurality of current sources. Each subpixel may include a current source configured to generate a drive current corresponding to the LED of the subpixel. The drive currents for the subpixel in a subpixel group 600 can be the same or different. The customized drive current for each subpixel can prevent artifacts, such as color shifts, in the light generated by each subpixel.
Each current source of the subpixel group 600 includes a current-source transistor biased by a power rail and a bias control. The first current-source transistor 611 is coupled at a source terminal to the first power rail 601 and is coupled at a gate terminal to a first bias control 661. The first bias control 661 is configured to supply a first bias voltage relative to the first rail voltage so that the first current-source transistor 611 can conduct a first drive current. The second current-source transistor 612 is coupled at a source terminal to the second power rail 602 and is coupled at a gate terminal to a second bias control 662. The second bias control 662 is configured to supply a second bias voltage relative to the second rail voltage so that the second current-source transistor 612 can conduct a second drive current. The third bias control 663 is configured to supply a third bias voltage relative to the third rail voltage so that the third current-source transistor 613 can conduct a third drive current. In a possible implementation, the bias controls are coupled to (i.e., shared by) the subpixel groups of a display so that the current-source transistors of a particular subpixel (e.g., red, green, blue) receive the same bias voltage. In this case, the bias voltage may be at a level that accommodates transistor variations due to process or temperature.
The subpixel group further includes a plurality of SRAM cells and a plurality of drive transistors. A state of the SRAM cell may control a drive transistor of a subpixel to be in an ON condition to conduct the drive current or in an OFF condition to block the drive current. In the ON condition, the drive transistor has approximately a zero voltage drop (i.e., short circuit). As shown, the subpixel group 600 includes a first drive transistor 621. The first drive transistor 621 is a PMOS transistor that (i) coupled at a source terminal to the drain terminal of the first current-source transistor 611, (ii) coupled at a gate terminal to a first SRAM 651, and (iii) coupled at a drain terminal to an anode of a first LED 631 (e.g., red micro-LED). The subpixel group 600 further includes a second drive transistor 622. The second drive transistor 622 is a PMOS transistor that (i) coupled at a source terminal to the drain terminal of the second current-source transistor 612, (ii) coupled at a gate terminal to a second SRAM 652, and (iii) coupled at a drain terminal to an anode of a second LED 632 (e.g., green micro-LED). The subpixel group 600 further includes a third drive transistor 623. The third drive transistor 623 is a PMOS transistor that (i) coupled at a source terminal to the drain terminal of the third current-source transistor 613, (ii) coupled at a gate terminal to a third SRAM 653, and (iii) coupled at a drain terminal to an anode of a third LED 633 (e.g., blue micro-LED). In other words, the current-source transistor, the drive transistor and the LED of each subpixel are connected in series (i.e., form a series connection). The cathodes terminals of the first LED 631, second LED 632, and third LED 633 can be connected together and coupled to a common cathode rail 671, which can be a ground voltage (i.e., ground) of the display. In other words, all of the power rails may be relative to the common cathode rail 671.
In the specification and/or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and/or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from “about” one particular value, and/or to “about” another particular value. When such a range is expressed, an aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.
It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
This application claims the benefit of U.S. Provisional Application No. 63/594,769, filed on Oct. 31, 2023, and U.S. Provisional Application No. 63/559,513, filed on Feb. 29, 2024, the disclosures of which are incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 63594769 | Oct 2023 | US | |
| 63559513 | Feb 2024 | US |
