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5081429 | Atriss et al. | Jan 1992 | |
5105169 | Yamazaki et al. | Apr 1992 | |
5121086 | Srivastava | Jun 1992 | |
5136260 | Yousefi-Elezei | Aug 1992 | |
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Number | Date | Country |
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96424 | Mar 1992 | JPX |
Entry |
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Kurt M. Ware et al.; A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors; Dec. 1989; pp. 1560-1568. |
A Low Jitter 5 Mhz to 180 Mhz Clock Synthesizer for Video Graphics; Reza Shariatdougst et al.; IEEE 1992 Custom Integrated Circuits Conference; Mar. 5, 1992; pp. 24.2.1-24.2.5. |
Deog-Kyoon Jeong et al.; Design of PLL-Based Clock Generation; Apr. 1987; pp. 255-261. |