MULTI-RATE DEM WITH MISMATCH NOISE CANCELLATION FOR DIGITALLY-CONTROLLED OSCILLATORS

Abstract
A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.
Description
FIELD

A field of the invention is frequency synthesis. Example applications of the invention are in clock generation, in wired and in wireless communications. A particular application of the invention is in wireless transceivers for the generation of radio frequency (RF) local oscillator signals used to up-convert and down-convert transmitted and received RF signals.


LIST OF ABBREVIATIONS

The following abbreviations are used in the description and are provided here for ease of reference.


CMOS Complementary Metal Oxide Semiconductor


DCO Digitally Controlled Oscillator


DEM Dynamic Element Matching


DLF Digital Loop Filter


FCE Frequency Control Element


IC Integrated Circuit


LC-Based Inductor-Capacitor Based


MNC Mismatch-Noise Cancellation


PEDC Phase-error-to-digital converter


PLL Phase Locked Loop


PSD Power Spectral Density


RF Radio Frequency


SB Digital Switching Block


BACKGROUND

Evolving wireless communication standards place increasingly stringent performance requirements on the frequency synthesizers that generate RF local oscillator signals for up and down conversion in wireless transceivers. Conventional analog fractional-N PLLs with digital delta-sigma (As) modulation are the current standard for such frequency synthesizers because of their excellent noise and spurious tone performance. See, e.g., T. A. Riley, M. A. Copeland, T. A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. Unfortunately, they require high-performance analog charge pumps and large-area analog filters, so the trends of CMOS technology scaling and increasingly dense system-on-chip integration have created an inhospitable environment for them.


Digital fractional-N PLLs have been developed over the last decade to address this problem. See, e.g., C. Hsu, M. Z. Straayer, M. H. Perrott, “A Low-Noise, Wide-BW 3.6 GHz Digital AS Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE International Solid-State Circuits Conference, pp. 340-341, February 2008. They avoid large analog loop filters and can tolerate device leakage and low supply voltages which makes them better-suited to highly-scaled CMOS technology than analog PLLs. They are increasingly used in place of analog PLLs as frequency synthesizers. To date, analog PLLs have the best phase error performance, but digital PLLs have the lowest circuit area and are more compatible with highly-scaled CMOS IC technology. Thus, reducing phase error in digital PLLs has been the subject of intensive research and development for over a decade.


A continuing problem in digital PLLs concerns frequency control element (FCE) mismatches. Such FCE mismatches remain a significant source of phase error in high-performance digital PLLs. See, C. Weltin-Wu, E. Familier, and I. Galton, “A linearized model for the design of fractional-N digital PLLs based on dual-mode ring oscillator FDCs,” IEEETrans.Circuits Syst. I, Reg.Papers, vol. 62, no. 8, pp. 2013-2023, August 2015. Prior attempts to address the FCE mismatch problem use an offline calibration technique that requires several minutes to complete. See, O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar, and I. Bashir, “Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator,” in Proc. IEEE Dallas Circuits Syst. Workshop, October 2010, pp. 17-18; O. Eliezer, B. Staszewski, and S. Vemulapalli, “Digitally controlled oscillator in a 65 nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., June 2011, pp. 5-7.


A digitally controlled oscillator (DCO) is an oscillator whose frequency is controlled by one or more FCEs, each of which is controlled by a 1-bit digital sequence. For instance, each FCE in an LC-based DCO contributes to the DCO's tank a capacitance that takes on one of two values depending on the state of the FCE's input bit. Changing the FCE's input bit increases or decreases the DCO frequency by a fixed frequency step.


The instantaneous frequency of a DCO is given by a fixed offset frequency plus ftune(t), where:












f
tune



(
t
)


=




i
=
1


N
FCE





f
i



(
t
)




,




(
1
)







NFCE is the number of FCEs in the DCO, and fi(t) is the contribution of the ith FCE to the DCO frequency. Ideally,






f
i(t)=(bi[mt]−½)Δi  (2)


where bi[m] is the FCE's input bit value (either 0 or 1) over the mth clock interval, mt=└fFCEt┘, fFCE is the clock-rate of the input bit, and Δi is the FCE's frequency step size.


The DCO's input sequence, d[n], represents the ideal value of ftune(t) over the nth clock interval. For example, suppose d[n] is represented as a 16-bit two's complement code where the least significant bit (LSB) represents a DCO frequency step of Δ (e.g., Δ=100 Hz). Then











d


[
n
]


=


(



-

2
15





d
15



[
n
]



+




i
=
0

14




2
i




d
i



[
n
]





)


Δ


,




(
3
)







where di[n], for each i=0, 1, . . . , 15, is the value of the ith bit of the code (either 0 or 1) over the nth clock interval.


Ideally, ftune(t)=d[nt], where nt=└fint┘ and fin is the clock-rate of the DCO input. Equations (1)-(3) with fFCE=fin imply that this can be achieved with a bank of 16 FCEs, where the ith FCE's frequency step size is Δi=2i−1Δ, bi[n]=di−1[n] for i=1, 2, . . . , 15, and b16[n]=1−d15[n].


Unfortunately, in PLL applications that require low phase noise, such as local oscillator synthesis for cellular telephone transceivers, DCOs with minimum frequency steps of tens of Hz are required, but most existing FCEs have minimum frequency steps of tens of kHz or more. A common solution to this problem is described next for an example case in which ftune(t) needs to be controlled in steps of Δ, yet the smallest realizable FCE frequency step size is Δmin=28Δ. In this case, the 8 LSBs of d[n] are said to represent the fractional part of d[n] because they cause DCO frequency steps that are fractions of Δmin, and the 8 most significant bits (MSBs) of d[n] are said to represent the integer part of d[n] because they cause DCO frequency steps that are multiples of Δmin.


The basic approach utilizes two FCE banks: an integer FCE bank controlled by the integer part of d[n], and a fractional FCE bank controlled by the output of an oversampling digital ΔΣ modulator driven by the fractional part of d[n] [Error! Bookmark not defined.]. The ΔΣ modulator's highpass-shaped quantization noise is lowpass filtered by the DCO, so provided the oversampling rate is sufficiently high, it negligibly contributes to the DCO's phase error.



FIG. 1 shows a specific example in the context of an LC-based DCO, where pt=└ffastt┘, ffast>>fit, and dI[nt] and dF[nt] are the integer and fractional parts of d[nt], respectively. The ffast-clk signal is such that pt changes synchronously with nt, so that nt can be written as a function of pt, i.e.,






n
t
=g(pt).  (4)


In this example g(pt)=└(fin/ffast)pt┘, where ffast/fin is an integer much greater than 1.


It follows from (3) that d[nt]=dI[nt]+dF[nt], where











d
I



[

n
t

]


=


(



-

2
15





d
15



[

n
t

]



+




i
=
8

14




2
i




d
i



[

n
t

]





)


Δ





(
5
)





and












d
F



[

n
t

]


=

Δ





i
=
0

7




2
i





d
i



[

n
t

]


.








(
6
)







As shown in FIG. 1, dF[nt] is sampled at a rate of ffast by a second-order digital ΔΣ modulator. The ΔΣ modulator's output is a four-level sequence quantized to multiples of Δmin and can be written as






y
ΔΣ[pt]=dF[nt]+eΔΣ[pt],  (7)


where eΔΣ[pt] is second-order highpass-shaped quantization noise plus any dither used within the ΔΣ modulator. A thermometer encoder maps yΔΣ[pt] to a 4-bit thermometer code which drives a bank of four FCEs, each with a frequency step of Δmin. It follows from (1), (2) and (7) that the contribution of the fractional FCE bank to the DCO frequency, fF(t), is











f
F



(
t
)


=





i
=
1

4




f
i



(
t
)



=



d
F



[

n

t






]


+



e
ΔΣ



[

p
t

]


.







(
8
)







The integer FCE bank is directly driven by dI[nt]. Specifically, the ith FCE, for i=5, 6, . . . , 11, has input bi[nt]=di+3[nt] and frequency step size Δi=2i+3Δ, and the 12th FCE has input b12[nt]=1−d15[nt] and frequency step size Δ12=215Δ. It follows from (1), (2) and (5) that the contribution of the integer FCE bank to the DCO frequency, fI(t), is












f
I



(
t
)


=





i
=
5

12




f
i



(
t
)



=


d
I



[

n
t

]




,




(
9
)







where a constant additive term has been omitted.


The contribution of the two FCE banks to the DCO frequency is ftune(t)=fI(t)+fF(t), so (8) and (9) imply that






f
tune(t)=d[t]+eΔΣ[pt]  (10)


Accordingly, eΔΣ[pt] causes DCO frequency error. The DCO's phase error is the integral of its frequency error, so as mentioned above, a lowpass-filtered version of eΔΣ[pt] appears as a component of the DCO's phase error. Given that eΔΣ[pt] has a highpass-shaped spectrum that peaks at ffast/2, its contribution to the DCO's phase error can be made negligible relative to other sources of phase error if ffast is large enough.


The analysis above presumes that the FCEs are ideal. Unfortunately, non-ideal circuit behavior causes fi(t) to deviate from (2). For example, suppose for now that fi(t) is modeled as ideal except for a static gain error given by αi, i.e.






f
i(t)=(bi[mt]−½)αiΔi.  (11)


Ideally, αi=1 for i=1, 2, . . . , NFCE, but inevitable component mismatches introduced during fabrication cause αi to deviate from 1.


Repeating the analysis for the example in FIG. 1 with (11) in place of (2) gives






f
tune(t)=αFftune-ideal(t)+eF(t)+eI(t)+(αI−αF)dI[nt],   (12)


where ftune-ideal(t) is given by the right side of (10), αF and αI are the averages of αi for i=1, 2, 3, 4 and i=5, 6, . . . , 12, respectively,











e
F



(
t
)


=




i
=
1

4




(


α
i

-

α
F


)



(



b
i



[

p
t

]


-

1
/
2


)



Δ
min







(
13
)





and












e
I



(
t
)


=




i
=
5

12




(


α
i

-

α
I


)



(



b
i



[

n
t

]


-

1
/
2


)




Δ
i

.







(
14
)







where ftune-ideal(t) is given by the right side of (10), αF and αI are the averages of αi for i=1, 2, 3, 4 and i=5, 6, . . . , 12, respectively.


Hence, the FCE static gain errors introduce a gain factor, αF, and three additive error terms to ftune(t). The αF gain factor does not significantly degrade performance in typical PLLs. In contrast, as explained next, the three additive error terms in (12) tend to cause spurious tones and increase phase error in PLLs because they are nonlinear functions of d[nt].


The individual bits of d[n], i.e., di[n], for each i=0, 1, . . . , 15, each depend on d[n] but are restricted to values of 0 and 1. Hence, each di[n] is a nonlinear function of d[n]. Nevertheless, they can be combined as in (3) to yield d[n], which implies that multiplying d0[n], d1[n], . . . , d14[n], and d15[n] by 20, 21, . . . , 214, and 215, respectively, and adding the results causes the nonlinear components from the individual bits to cancel each other. Any deviation from a set of scale factors proportional to those mentioned above prevents full cancellation of the nonlinear components. It can be verified from (5), (13) and (14) that eF(t), eI(t), and (αI−αF)dI[nt] are each a function of a subset of the individual bits of d[nt], so they are nonlinear functions of d[nt].


A partial solution to this problem is to replace the thermometer encoder in FIG. 1 with a mismatch-shaping DEM encoder. See, I. Galton, “Why Dynamic-Element-Matching DACs Work,” IEEE Trans. Circuits Syst. Exp. Briefs, vol. 57, no. 2, pp. 69-74, March 2010. Doing so would cause eF(t) to be replaced by highpass-shaped noise that is free of nonlinear distortion and is uncorrelated with d[nt], so it would be suppressed by the DCO 102 like the ΔΣ quantization noise. Similarly, the integer FCE bank 104 could be modified to accommodate a mismatch-shaping DEM encoder clocked at a rate of fin, which would cause eI(t) to be replaced by shaped noise that is free of nonlinear distortion and is uncorrelated with d[nt]. However, fin □ ffast, less of the shaped noise would be suppressed by the DCO 102. Unfortunately, DEM as described above would not help prevent the last term in (12) from introducing nonlinear distortion because dI[nt] is a non-linear function of d[nt].


The last two terms in (12) increase the phase error in a PLL unless dI[nt] remains constant once the PLL is locked. See, C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015. In most published digital PLLs d[n] varies by much less than Δmin when the PLL is locked, and measured results are usually presented for PLL frequencies at which can dI[nt] does not change during the measurement interval. This renders the last two terms in (12) constant, so they do not contribute phase error. Unfortunately, this is not a viable option in practice because DCO center frequency drift caused by flicker noise, voltage and temperature variations, and pulling from external interference cause d[nt] to vary by far more than Δmin over time. For instance, measurement results indicate that the frequency of the DCO presented in [C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015] varies by about −200 kHz/° C., which corresponds to ˜7Δmin per degree Celsius. In practice, this causes the digital PLL's phase noise to increase drastically from time to time as d[nt] slowly drifts past integer multiples of Δmin. This issue is sometimes called “spectral breathing” because the phase noise spectrum, as viewed on laboratory measurement equipment, appears to swell up every now and then as if it is taking deep breaths. During these “breaths” the PLL's performance is extremely degraded. Furthermore, when the PLL is used to generate phase or frequency modulated signals, such as a GFSK signal for a Bluetooth transmitter, d[nt] typically varies by more than Δmin, so there are no periods between “breaths” during which the phase noise performance is good.


To address this problem, a single bank of FCEs driven by a ΔΣ modulator and a mismatch-shaping DEM encoder could be used, where the ΔΣ modulator oversamples d[nt] instead of just dF[nt]. The DEM encoder would cause any mismatches among the FCEs to contribute shaped noise instead of nonlinear distortion, and the oversampling would ensure that most of the noise is suppressed by the DCO. Unfortunately, high oversampling ratios would be required in practice, which makes this solution impractical because of the associated high-power consumption


SUMMARY OF THE INVENTION

A preferred embodiment is a digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC). The PLL includes a phase error to digital converter (PEDC) and a digital loop filter to suppress quantization noise of the PEDC and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 (Prior Art) is a schematic diagram of a frequency control technique for an LC-based DC);



FIG. 2 includes a set of example waveforms related to equations (15) and (16) to provide a visual representation of the effects of FCE mismatches on the DCO frequency;



FIG. 3 (Prior Art) is a block diagram of a mismatch-shaping segmented DEM encoder;



FIGS. 4A-4C (Prior Art) are block (4A & 4B) and schematic (4C) diagrams showing digital switching blocks of the FIG. 3 DEM encoder;



FIG. 5 is a block diagram of a preferred embodiment DCO with a multi-rate segmented DEM encoder that is a modification of the FIG. 3 encoder;



FIG. 6 is a block diagram of a preferred slow DEM encoder used in FIG. 5,



FIG. 7 is a functional diagram of a preferred embodiment second-order digital ΔΣ modulator used in FIG. 5;



FIG. 8 shows the fractional path of the multi-rate DEM encoder shown in FIG. 5 modified to accommodate MNC;



FIG. 9 (Prior Art) is a schematic diagram of a digital fractional-N PLL without MNC;



FIGS. 10A & 10B (Prior Art) respectively are a schematic diagram of a synchronization circuit used at DCO input in FIG. 9 and illustration of the clock signals within the DCO, pt, and nt=g(pt) for ffast=4. 5fref,



FIGS. 11A-11C are block diagrams that illustrate a preferred digital fractional-N PLL with the multi-rate DEM encoder and MNC;



FIG. 12 shows example frequency transients used in a simulation of the FIGS. 11A-11C digital fractional-N PLL;



FIGS. 13A-13C respectively show simulated phase noise of the FIGS. 11A-11C digital fractional-N PLL; with the multi-rate DEM technique disabled, with the multi-rate DEM technique enabled for two cases, and with the multi-rate DEM technique enabled and with the MNC technique disabled and enabled;



FIGS. 14A & 14B show the evolution of the MNC coefficient errors over time from the simulation used to generate the curves in FIG. 13C;



FIGS. 15A & 15B show the evolution of the MNC coefficient errors over time for 7·8·107 reference periods (3 seconds) for an example case in which Ka and Kb are initially set to 2−1 and 2−2, respectively, and then divided by two at the times indicated by the vertical dashed lines.





DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiment methods and digital oscillators provide multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) that work together to address FCE mismatches. The DEM and the MNC run during normal PLL operation, and the MNC typically converges in a few seconds from a cold start. A preferred DEM has been simulated and succeeds in reducing noise from the FCE mismatches. The MNC cancels DCO phase error arising from FCE mismatch error. Ideal MNC coefficient values are estimated, during PLL normal operation, as part of the feedback loop in a digital fractional-N PLL that incorporates the DCO.


The center frequency of a conventional digitally-controlled oscillator (DCO) drifts over time due to flicker noise, voltage and temperature variations, and pulling from external interference. Given that the DCO frequency is a non-linear function of the DCO's input signal, this causes the digital PLL's phase noise to increase drastically from time to time because the DCO's input signal slowly drifts to counteract the DCO's center frequency drift. This issue is called spectral breathing because the phase noise spectrum, as viewed on laboratory measurement equipment, appears to swell up every now and then as if it is taking deep breaths of air, during which the PLL's performance is extremely degraded. Moreover, when the PLL is used to generate phase or frequency modulated signals there are no periods between breaths during which the phase noise performance is good. Spectral breathing can drastically degrade a digital PLL's phase noise. Preferred embodiments address spectral breathing by making the relation between the DCO frequency and its input signal linear, which is done at the expense of initially adding more noise to the system. However, this added noise has properties that can be exploited to cancel it, so that the digital PLL's performance is no longer degraded when the DCO's input signal changes. Overall, the price is only a slightly higher power consumption.


Preferred embodiments provide a new multi-rate DEM technique and an MNC technique that work together within a PLL to solve the problems that arise from FCE mismatches are presented. As in FIG. 1, the preferred embodiment uses integer and fractional FCE banks. In the preferred embodiment, both FCE banks are driven by a multi-rate DEM encoder, which ensures that the error arising from FCE mismatches is free of nonlinear distortion. In addition, the multi-rate DEM encoder avoids high power consumption because most of its digital logic is clocked at a rate of fin instead of ffast. Although the hardware of preferred embodiments is different from that of the solution in which d[nt] is oversampled and a DEM encoder clocked at a high rate is used to control the FCEs, a pessimistic power consumption analysis indicates that the preferred techniques are at least five times more power-efficient. Much of the additive error is not oversampled, so instead of relying on the DCO to suppress it, the MNC technique adaptively measures the error and cancels it in real time.


Preferred embodiments of the invention will now be discussed with respect to the drawings and experiments used to demonstrate the invention. The drawings may include schematic and/or block representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows.


FCEs with Δimin are usually built by connecting nominally identical minimum-weight FCEs in parallel. Static mismatches among these FCEs are sources of error, but other non-idealities such as the non-instantaneous frequency transitions of realizable FCEs are also sources of error. Hence, a more comprehensive model than (11) for fi(t) is






f
i(t)=(bi[mt]−½)Δi+ei(t),  (15)


where ei(t) is error that models both the static mismatch and the non-ideal frequency transitions of the ith FCE. bi[m] is the FCE's input bit value (either 0 or 1) over the mth clock interval, as defined above in (2). FCEs are designed such that frequency transitions caused by input bit changes settle within a clock period, so ei(t) only depends on bi[mt−1] and bi[mt]. This can be modeled as











e
i



(
t
)


=

{






e

11

i


,






if







b
i



[


m
t

-
1

]



=
1

,



b
i



[

m
t

]


=
1

,








e

01

i




(
t
)


,






if







b
i



[


m
t

-
1

]



=
0

,



b
i



[

m
t

]


=
1

,







e

00

i


,






if







b
i



[


m
t

-
1

]



=
0

,



b
i



[

m
t

]


=
0

,








e

10

i




(
t
)


,






if







b
i



[


m
t

-
1

]



=
1

,



b
i



[

m
t

]


=
0





,






(
16
)







where e11i, e01i(t), e00i, and e10i(t) represent the error over each clock interval corresponding to the four different possibilities of the FCE's current and prior input bit values. The FCE model given by (15) and (16) is analogous to that of a non-return-to-zero (NRZ) 1-bit DAC. To prevent ei(t) from depending on bi[mt−1], return-to-zero (RZ) FCEs could be implemented by setting the FCEs to a signal-independent state for a fraction of each clock period, but this is not practical for PLLs because it would periodically slew the DCO frequency and thereby introduce excessive phase noise.



FIG. 2 shows example waveforms associated with (15) and (16). A consequence of the frequency transitions settling within a clock period is that when an FCE's input bit does not change between clock periods, neither does its contribution to the DCO frequency, so e00i and e11i are constant. In contrast, e01i(t) and e10i(t) are not constant because they represent deviations from the FCE's ideal instantaneous frequency transitions when its input bit changes. As shown in FIG. 2, the shape of each of these frequency transitions depends only on whether the corresponding FCE input changed from 0 to 1 or 1 to 0, and both e01i(t) and e10i(t) are 1/fFCE-periodic.


Experimental results indicate, at least for the LC-based DCOs presented in [C. Venerus and I. Galton, “A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer with a 2.8-3.5 GHz DCO,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 450-463, February 2015] and [C. Weltin-Wu, E. Familier, and I. Galton, “A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], that the frequency transition introduced by each FCE when its input bit changes from 0 to 1 and that when the input bit changes from 1 to 0 are antisymmetric to a high degree of accuracy, i.e., e11i−e01i(t)=−[e00i−e10i(t)]. Therefore, substituting (16) into (15), applying this observation, collecting terms and omitting constant additive terms yields.






f
i(t)=(bi[mt]−½)αi(ti+(bi[mt−1]−½)γi(t),  (17)





where





αi(t)=1+(e01i(t)−e00i)/Δiand γi(t)=e11i−e01i(t).  (18)


Given that αi(t) and γi(t) are functions of e01i(t) and e10i(t), which are 1/fFCE-periodic, they are also 1/fFCE-periodic.


Multi-Rate DEM

Single-Rate Segmented DEM


Suppose the DCO's input sequence is given by (3), and for now suppose that ΔΣ quantization is not necessary because FCEs with small-enough step sizes are available, i.e., Δmin=Δ. Even in this case, FCE mismatches are a problem because they cause nonlinear distortion. A conventional single-rate segmented DEM encoder can be used to prevent this problem. For example, the mismatch-shaping segmented DEM encoder shown in FIG. 3 can be used with 34 FCEs. See, K. L. Chan, N. Rakuljic, and I. Galton, “Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3383-3392, December 2008. The ith FCE has input bi[nt]=ci[nt] and frequency step size Δi=KiΔ, where






K
2i-1
=K
2i=2i−1 for i=1,2, . . . ,13, and






K
i=213 for i=27,28, . . . ,34.  (19)


The DEM encoder's input sequence, c[nt], is obtained from the DCO input sequence as






c[nt]=d[nt]/Δ+215+213−1  (20)


As shown in FIG. 3, the DEM encoder 300 consists of 33 digital switching blocks (SBs) 302, labeled Sk,r for k=1, 2, . . . , 16, and r=1, 2, . . . , 17, configured in a tree structure. The 13 shaded SBs are called segmenting SBs, whereas the other 20 SBs are called non-segmenting SBs. The functional details of the SBs are shown in FIGS. 4A-4C. The top and bottom outputs of each segmenting SB are ½(ck,r[nt]−1−sk,1[nt]) and 1+sk,1[nt], respectively, where ck,1[nt] is the SB input sequence, and sk,1[nt], called a switching sequence, is 0 when ck,1[nt] is odd and ±1 otherwise. Similarly, the top and bottom outputs of each non-segmenting SB are ½(ck,r[nt]−sk,r[nt]) and ½(ck,r[nt]+sk,r[nt]), respectively, where ck,r[nt] is the SB input sequence and sk,r[nt] is 0 when ck,r[nt] is even and ±1 otherwise.


Regardless of the SB type, each switching sequence is zero-mean and has a first-order highpass-shaped power spectral density (PSD) that peaks at fin/2. It is generated in two's complement format by the logic shown in FIG. 4C, wherein dk,r[nt] is generated within each SB and is well-modeled as a two-level white random sequence that takes on values of 0 and 1 with equal probability and is independent of the dk,r[nt] sequences in the other SBs.


Extension to Multi-Rate Segmented DEM


Now suppose that the smallest practical FCE frequency step size is Δmin=28Δ. As the lower 16 FCEs in the example above all have frequency step sizes smaller than Δmin, the bottom 16 outputs of the DEM encoder can no longer drive FCEs directly. The preferred multi-rate DEM architecture 500 in the DCO control logic 501 shown in FIG. 5 addresses this situation, where a bottom 4 FCEs make up a fractional FCE bank 502, the top 18 FCEs make up an integer FCE bank 504, and wt=pt−1 is a Tfast-delayed version of pt, where Tfast=1/ffast. As in FIG. 1, nt=g(pt) changes synchronously with pt.


A slow DEM encoder 506 is a modified version of the DEM encoder in FIG. 3. Its outputs c17[nt], c18[nt], . . . , c34[nt] are identical to those in FIG. 3, and instead of outputs c1[nt], c2[nt], . . . , c16[nt] it has an output, xf[nt], supplied to a second order digital ΔΣ modulator 508, given by











x
f



[

n
t

]


=

Δ





i
=
1

16





K
i



(



c
i



[

n
t

]


-

1
/
2


)


.







(
21
)







Each ci[nt] takes on values of 0 and 1, so (19) and (21) imply that |xf[nt]|≤255Δ and xf[nt] is restricted to multiples of Δ.


The slow DEM encoder could be implemented from the DEM encoder of FIG. 3 directly by combining c1[nt], c2[nt], . . . , c16[nt] as in (21), but the preferred structure of FIG. 6 provides a simpler and more elegant approach. As implied by FIG. 4B, the sum of the outputs of each non-segmenting SB is equal to the SB's input, so it follows from (21), FIG. 3 and FIG. 4A that xf[nt] can be computed directly from the bottom outputs of S16,1, S15,1, . . . , S9,1 as











x
f



[

n
t

]


=

Δ





k
=
9

16




2

16
-
k






s

k
,
1




[

n
t

]


.








(
22
)







Hence, as shown in FIG. 6, S1,1, S1,2, . . . , S1,8 are not necessary in the slow DEM encoder 506.


The Δ scale factor shown in FIG. 6 is not an actual multiplier; it just denotes that the subsequent digital logic should interpret the LSB of xf[nt] to represent a DCO frequency step size of Δ.


As shown in FIG. 5, xf[nt] is sampled at a rate of ffast by the second-order digital 4E modulator 508, whose functional diagram is shown in FIG. 7. The dither sequence, dΔΣ[pt], is generated such that it can be well-modeled as a two-level white random sequence that is independent of d[nt] and xf[nt] and takes on values of 0 and A with equal probability. It ensures that the ΔΣ modulator's 508 quantization noise is asymptotically independent of xf[nt] and dΔΣ[pt], and has a PSD equal to that of the output of a filter with transfer function (1−z−1)2 driven by white noise with a variance of Δmin2/12. See, S. Pamarti, J. Welz, and I. Galton, “Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 3, pp. 492-503, March 2007. The ΔΣ modulator output is quantized to values in the set {−2Δmin, −Δmin, 0, Δmin, 2Δmin} and is given by






y
ΔΣ[pt]=xf[nt]+eΔΣ[pt],  (23)


where eΔΣ[pt] is second-order highpass-shaped quantization noise plus dΔΣ[pt].


In FIG. 5, a fast DEM encoder 510 can be a conventional mismatch-shaping non-segmented DEM encoder with a clock rate of ffast. It is implemented as a tree of non-segmenting SBs, and it maps yΔΣ[pt] to four 1-bit sequences, each of which drives an FCE with a frequency step size of Δmin.


Each bi[wt] in FIG. 5, for i=1, 2, 3, 4, is clocked at a rate of ffast and toggles rapidly enough such that the FCE frequency transitions from the fractional FCE bank introduce high-frequency error components to the DCO phase error. Such components are lowpass filtered by the DCO, so ffast can be chosen so that they are not a problem in practice. Consequently, the frequency transitions of the FCEs from the fractional FCE bank 502 are modeled as ideal, so that fi(t) is given by (11) for i=1, 2, 3, 4.


It follows that






f
F(t)=αFyΔΣ[wt]+eF(t),  (24)


where αF is the average of αi for i=1, 2, 3, 4 and eF(t) is a function of the errors introduced by the fractional FCE bank 502 and the switching sequences from the fast DEM encoder 510. The fast DEM encoder 510 ensures that eF(t) is free of nonlinear distortion, uncorrelated with yΔΣ[wt], and has a first-order highpass-shaped PSD that peaks at ffast/2, so ffast can be chosen so that this term is not a problem in practice. Thus, substituting (23) into (24) and neglecting eF(t) gives






f
F(t)=αFxf[g(wt)]+αFeΔΣ[wt].  (25)


As shown in FIG. 5, the c17[nt], c18[nt], . . . , c34[nt] outputs of the slow DEM encoder 506 drive the same FCEs as those of the DEM encoder of FIG. 3. This implies that fI(t) is given by












f
I



(
t
)


=




α
I



(
t
)




d


[

g


(

w
t

)


]



+



γ
I



(
t
)




d


[

g


(


w
t

-
1

)


]



+


e
I



(
t
)




,




(
26
)





where













e
I



(
t
)


=

Δ





k
,
r







{




α

k
,
r




(
t
)





s

k
,
r




[

g


(

w
t

)


]



+



γ

k
,
r




(
t
)





s

k
,
r




[

g


(


w
t

-
1

)


]




}




,




(
27
)







αI(t), γI(t), αk,r(t) and γk,r(t) (defined in Appendix A below) are Tfast-periodic waveforms that depend on the errors introduced by the integer FCE bank 504, and the summation indices indicate the summation over all k and r values corresponding to the SBs within the slow DEM encoder 506.


The contribution to the DCO frequency from both FCE banks 502 and 504 is ftune(t)=fI(t)+fF(t), so (25) and (26) imply that






f
tune(t)=αI(t)d[g(wt)]+γI(t)d[g(wt−1)]+αFeΔΣ[wt]+eM(t),  (28)





where






e
M(t)=eI(t)+αFxf[g(wt)]  (29)


is called FCE mismatch error. eM(t) is a linear combination of the switching sequences from the slow DEM encoder whose coefficients depend on the errors introduced by both FCE banks 502 and 504.


The γI(t)d[g(wt−1)] term in (28) is proportional to a Tfast-delayed version of d[g(wt)], so it represents a linear filtering operation. This term tends to be much smaller than the desired signal component, αI(t)d[g(wt)], so it is not a problem in practice. The αFeΔΣ[wt] term is proportional to ΔΣ quantization noise plus dither so it is free of nonlinear distortion, is uncorrelated with the other terms in (28), and has a highpass-shaped PSD. The eM(t) term also has these properties because it is a linear combination of the switching sequences from the slow DEM encoder. The PSD of αFeΔΣ[wt] peaks at ffast/2, whereas the PSD of eM(t) peaks at fin/2. Hence, ffast can be increased to make the DCO phase error introduced by αFeΔΣ[wt] negligible, but this would not reduce the DCO phase error contribution from eM(t). Therefore, eM(t) is the only problematic term in (28).


Substituting (22) and (27) into (29) yields












e
M



(
t
)


=

Δ





k
,
r







{



δ

k
,
r





s

k
,
r




[

g


(

w
t

)


]



+



γ

k
,
r




(
t
)




(



s

k
,
r




[

g


(


w
t

-
1

)


]


-


s

k
,
r




[

g


(

w
t

)


]



)



}




,




(
30
)










where

















δ

k
,
r


=

{








α

k
,
r




(
t
)


+


γ

k
,
r




(
t
)


+


α
F



2

16
-
k




,






if





k


9

,

r
=
1










α

k
,
r




(
t
)


+


γ

k
,
r




(
t
)



,



otherwise



,







(
31
)







is constant for each k and r, even though neither αk,r(t) nor γk,r(t) are constant. The non-constant terms in each αk,r(t) are equal in magnitude but opposite in sign to the corresponding terms in γk,r(t), so αk,r(t)+γk,r(t), and hence δk,r, are constant. Therefore, the terms proportional to δk,r, in (30) represent the DCO frequency error contribution from FCE static gain errors, whereas the terms proportional to γk,r(t) in (30) represent the DCO frequency error contribution from non-ideal FCE frequency transitions.


Adaptive FCE Mismatch Noise Cancellation

The purpose of the present MNC is to cancel most of the DCO phase error that would otherwise be caused by eM(t). To do this, the sequence












e
MNC



[

p
t

]


=

Δ





k
,
r







{



α

k
,
r





s

k
,
r




[

n
t

]



+


b

k
,
r




(



s

k
,
r




[

g


(

w
t

)


]


-


s

k
,
r




[

n
t

]



)



}




,




(
32
)







where ak,r, and bk,r are called the MNC coefficients, is injected into the fractional path of the multi-rate DEM encoder. The ideal MNC coefficient values, i.e., the values of ak,r, and bk,r, for which the DCO phase error contribution of eM(t) is minimized, are estimated with a least-mean-square (LMS)-like algorithm. The algorithm is similar to a conventional LMS algorithm in the sense that it consists of a set of coefficients that are updated over time based on how strongly known signals are correlated to an error measurement.


We next explain how eMNC[pt] affects the DCO's phase error, how the FCE mismatch error is measured, and how the MNC coefficients are adaptively computed from the FCE mismatch error measurement.


MNC Sequence Application



FIG. 8 shows the fractional path of the multi-rate DEM encoder shown in FIG. 5 modified to accommodate MNC. The eMNC[pt] sequence (determined by FIGS. 11A-11C, discussed below) is subtracted from xf[nt] prior to the ΔΣ modulator, and the output range of the ΔΣ modulator 508, the range of the fast DEM encoder 510, and the number of FCEs of the FCE bank 502 driven by the fast DEM encoder 510 are all four times those of the original FIG. 5 system to accommodate the resulting dynamic range increase. Thus, fF(t) is still given by (24), but now γΔΣ[pt] is given by the right side of (23) minus eMNC[pt]. Despite having the same qualitative properties as before, αF and eF(t) in (24) are slightly different in the modified system because of the additional FCEs.


An analysis shows that ftime(t) is now given by






f
tune(t)=αI(t)a[g(wt)]+γI(t)d[g(wt−1)]+αFeΔΣ[wt]+eR(t),  (33)





where






e
R(t)=eM(t)−αFeMNC[wt]  (34)


is the residual FCE mismatch error, i.e., what is left of eM(t) when eMNC[pt] is applied. It follows from (30), (32) and (34) that












e
R



(
t
)


=

Δ





k
,
r







{



δ

k
,

r
-
res






s

k
,
r




[

g


(

w
t

)


]



+



γ

k
,

r
-
res





(
t
)




(



s

k
,
r




[

g


(


w
t

-
1

)


]


-


s

k
,
r




[

g


(

w
t

)


]



)



}




,




(
35
)







respectively.


Given that δk,r is constant, there exists an ak,r that causes δk,r-res=0. In contrast, there is no bk,r that causes γk,r-res(t) to vanish completely, because γk,r(t) is not constant. However, γk,r(t) is Tfast-periodic so there exists a bk,r that makes the DC component of γk,r-res(t) zero, such that γk,r-res(t) is a linear combination of sinusoids with frequencies that are non-zero multiples of ffast. Therefore, it follows from Error! Reference source not found. that if











a

k
,
r


=




δ

k
,
r



α
F







and






b

k
,
r



=


1


α
F



T
fast







0

T
fast






γ

k
,
r




(
τ
)



d





τ





,




(
36
)







for each k and r, then





δk,r-res=0 and ∫0Tfastγk,r-res(τ)dτ=0.  (37)


In the absence of FCE static mismatches, ak,r=0, and if the FCE frequency transitions are ideal, bk,r=0.


Phase error is the integral of frequency error, so the DCO phase error introduced by eR(t) is given by





θR(t)=∫0teR(τ)dτ.  (38)


If (37) is satisfied, then (35) and (38) imply that












θ
R



(
t
)


=

Δ





k
,
r








(



s

k
,
r




[

g


(


w
t

-
1

)


]


-


s

k
,
r




[

g


(

w
t

)


]



)





0

t
-


p
t



T
fast








γ

k
,

r
-
res





(
u
)



du






,




(
39
)







where t−ptTfast=t−└ffastt┘Tfast<Tfast. The term within the parenthesis in (39) equals zero when g(wt)−g(wt−1)=0 and sk,r[g(wt)−1] sk,r[g(wt)] otherwise. Given that g(wt)−g(wt−1) can only take on values from the set {0, 1}, then






s
k,r[g(wt−1)]−sk,r[g(wt)]=(g(wt)−g(wt−1))(sk,r[g(wt)−1]−sk,r[g(wt)]).  (40)


Furthermore, g(wt) is a Tfast-delayed version of nt, which increases by one unit every Tin=1/fin, so g(wt)−g(wt−1) is Tin-periodic and is given by











g


(

w
t

)


=


g


(


w
t

-
1

)


=




k
=

-







r


(

t
-

kT

i





n



)





,




(
41
)







where r(t)=1 for t∈[Tfast, 2Tfast) and 0 otherwise. It follows from (41) that the Fourier expansion of g(wt)−g(wt−1) is











f

i





n



f
fast


+




m
=
1






2

m





π




sin


(

m





π



f

i





n



f
fast



)





cos


(

2

π







mf

i





n




[

t
-


3
2



T
fast



]



)


.







(
42
)







Thus, if the conditions shown in (37) are satisfied, (39), (40) and (42) imply that θR(t) would be given by second-order shaped noise multiplied by a Tin-periodic waveform and a DC-free Tfast-periodic waveform. Consequently, eR(t) would introduce components with frequencies around fn,m=nffast±mfin to the DCO's phase error, where n=1, 2, 3, . . . and m=0, 1, 2, . . . . It follows from (42) that the power of the components around frequencies fn,m with m near multiples of ffast/fin is very low. Therefore, θR(t) would not be a problem if ffast is large enough because eR(t) would only introduce high-frequency components to the DCO's phase error that would be lowpass filtered by the DCO. Simulation results also suggest that θR(t) is not a problem provided the conditions shown in (37) are satisfied and ffast is large enough.


FCE Mismatch Error Measurement


The ideal MNC coefficient values are estimated as part of a feedback loop in a digital fractional-N PLL that incorporates the DCO. This is done during the PLL's normal operation by adaptively adjusting ak,r, and bk,r, such that the conditions shown in (37) are satisfied for each k and r, thereby minimizing eR(t).


The purpose of a fractional-N PLL is to generate a periodic output signal, vPLL(t), with frequency fPLL=(N+α)fref, where N is a positive integer, α is a fractional value and fref is the frequency of a reference oscillator waveform, vref(t). The general form of a digital fractional-N PLL without MNC is shown in FIG. 9. It consists of a phase-error-to-digital converter (PEDC) 902, a lowpass digital loop filter (DLF) 904, and a DCO 906. The PEDC's 902 output is an fref-rate digital sequence of the form






p[n]=−θPLL[n]+ep[n],  (43)


where θPLL[n] is an estimate of the PLL's phase error and ep[n] is additive error that includes quantization error from the PEDC's 902 digitization process as well as error from circuit noise and other non-ideal circuit behavior in both the PEDC and reference oscillator.


A modified version of the DCO 906 contains the preferred multi-rate DEM structure of FIG. 5 with the MNC correction of FIG. 8 with fin=fref. Typically, ffast-clk is a divided-down version of vPLL(t). Given that fPLL=(N+α)fref, fref and ffast are incommensurate frequencies when α≠0, it is not possible for nt to change synchronously with pt=└ffastt┘ if nt=└freft┘. Therefore, as shown in FIGS. 10A & 10B, in practice the DCO input is synchronized to ffast-clk so (4) is satisfied, i.e., so nt only changes at times μn, which are multiples of Tfast, instead of times nTref, where Tref=1/fref is the reference period. It is common practice in digital PLLs to synchronize the DLF 904 output to the clock signal of the fractional path, so this is not a special requirement of the proposed system. A conventional circuit to avoid metastability issues is also needed as part of the synchronization circuit shown in FIG. 10A, but it has been omitted for simplicity.


A requirement of a PLL is to suppress low-frequency DCO error, which is achieved by subjecting additive frequency error introduced by the DCO to a highpass filter that has at least one zero at DC. In the following, the impulse response of this filter is denoted as h[n], and its running sum, i.e., h[0]+h[1]+ . . . +h[n], is denoted as l[n]. p[n] can be written as






p[n]=pideal[n]+pR[n],  (44)


where pideal[n] represents the contribution to p[n] of all noise sources except FCE mismatches and pR[n] is the contribution to p[n] from eR(t). Specifically, pR[n] (with references to definitions in Appendix B) is given by












p
R



[
n
]


=


Δα
F



T
fast






i
=
0


n
-
1







k
,
r








{



y

k
,

r
-
a





[
i
]


+


y

k
,

r
-
b





[
i
]



}



l


[

n
-
1
-
i

]







,




(
45
)







where yk,r-a[t]+yk,r-b[i] is proportional to the PLL's frequency error introduced by the sk,r[n] sequences. If ak,r and bk,r in (32) are replaced by ak,r[nt] and bk,r[nt], respectively, then






y
k,r-a[i]=(qi−1−3)sk,r[i−1]ak,r-error[i−1]+3sk,r[i]ak,r-error[i]  (46)





and






a
k,r-b[i]=(sk,r[i−1]−sk,r[i])bk,r-error[i],  (47)


where qi−1 is the number of Tfast periods between times μi−1 and μi, and






a
k,r-error[n]=ak,r[n]−ak,r and bk,r-error[n]=bk,r[n]bk,r   (48)


are the MNC coefficient errors at sample time n.


The term proportional to sk,r[i] in (46) arises because the time at which the PEDC 902 samples the PLL's phase error, which is given by μn+4Tfast in the design example, is not equal to the time at which the integer FCE bank's inputs are updated, i.e., μn+Tfast. Accordingly, the integer FCE bank's inputs are updated three Tfast before the PLL's phase error is sampled, which causes yk,r-a[i] to depend on sk,r[i−1] and also on sk,r[i]. As implied by (44)-(47), the PEDC's 902 output has information regarding the MNC coefficient errors. The MNC coefficient estimation process described next is based on this result and on the properties of the switching sequences.


MNC Coefficients Estimation


A digital fractional-N PLL with the multi-rate DEM encoder and MNC technique is shown in FIG. 11A. The details of MNC logic 1102 are shown in FIG. 11B and FIG. 11C, wherein











t

k
,
r




[
n
]


=




i
=
0

n




s

k
,
r




[
i
]







(
49
)







is the running sum of sk,r[n], and Ka and Kb are called the MNC gains. The MNC logic block consists of an adder and 25 sk,r[nt] residue estimators 1104.


It follows from FIG. 4 that each sk,r[n] sequence is a concatenation of sequences of the form 1, 0, . . . , 0, −1, 0, . . . , 0 or −1, 0, . . . , 0, 1, 0, . . . , 0, where each 0 is present only when the input of the sk,r[n] generator is zero. Thus, |sk,r[n]|≤1, |sk,r[n]|≤1 and |sk,r[n]−sk,r[n−1]|≤2 for all n, so the multipliers in FIG. 11(c) are simple in terms of hardware.


The sk,r[nt] residue estimators 1104 are responsible for the computation of the MNC coefficients. At each sample time, the MNC coefficient errors are measured and ak,r[nt] and bk,r[nt] are updated such that they approach the values shown in (36). The measurement of the MNC coefficient errors is based on the statistical properties of the switching sequences.


Although each sk,r[n] sequence depends on the input of its corresponding SB, when it is non-zero, its sign depends on dk,r[n]. Given that the dk,r[n] sequences are independent of the dk,r[n] sequences in the other SBs, this provides enough randomization for the sk,r[n] sequences to be uncorrelated with each other. Furthermore, as the dk,r[n] sequences are also independent of all electronic device noise sources in the PLL, each sk,r[n] sequence is uncorrelated with all such sources as well, and it is also uncorrelated with the PEDC's 902 quantization noise in PLLs where such noise source is uncorrelated with the PLL's phase error.


Hence, in such cases, the sk,r[n] sequences are uncorrelated with all PLL noise except the terms in p[n] arising from eR(t), i.e., pR[n].


The yk,r-a[i] and yk,r-b[i] terms in p[n] depend on the MNC coefficient errors, and such terms are proportional to functions of the sk,r[n] sequences. Specifically, it can be seen from (44)-(47) that p[n] has information about an accumulated version of





(qn−2−3)sk,r[n−2]ak,r-error[n−2],  (50)


and that p[n]−p[n−1] has information about





(sk,r[n−2]sk,r[n−1])bk,r-error[n−1].  (51)


Therefore, it follows that the accumulator inputs in FIG. 11C, i.e., −p[n]tk,r[n−2] and (p[n−1]−p[n])(sk,r[n−2]−sk,r[n−1]), when non-zero, are noisy estimates of ak,r-error[n] and bk,r-error[n], respectively, so they can be used to adaptively compute the ideal MNC coefficients. In practice, the top and bottom branches within each sk,r[nt] residue estimator 1104 interfere with each other in a way that makes the accumulator inputs have information about both MNC coefficient errors. However, extensive simulations indicate that the MNC coefficient values converge to their ideal values regardless of such interferences provided the MNC gains are set properly to avoid instability in the feedback loops.


It would also be possible to correlate p[n−1]−p[n] by sk,r[n−2] to get an estimate of ak,r-error[n]. However, as ak,r[n] is only updated when the accumulator input is non-zero, correlating p[n−1]−p[n] against sk,r[n−2] instead of −p[n] against tk,r[n−2] would significantly decrease the convergence speed of ak,r[n] because normally sk,r[n−2] is zero more often than tk,r[n−2]. Although correlating −p[n] against tk,r[n−2] effectively increases the error variance of ak,r[n], as explained next, this problem can be mitigated by reducing Ka.


As is common in most LMS-like algorithms, the choice of Ka and Kb represents a tradeoff. The larger the MNC gains, the faster the convergence, but the larger the error variance of ak,r[n] and bk,r[n]. Also, as the sk,r[nt] residue estimators comprise two LMS-like loops in parallel that interfere with each other, Ka and Kb each affect the convergence time and error variance of both ak,r[n] and bk,r[n]. Although it might be possible to develop closed-form expressions that quantify these tradeoffs, the authors currently use simulations to assist the design process and to choose the values of Ka and Kb.


Simulation Results

The multi-rate DEM and the MNC methods of the preferred embodiments described above were tested in an event-driven behavioral simulation of a modified version of the ΔΣ frequency-to-digital converter based fractional-N PLL presented in [C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015; C. Weltin-Wu, G. Zhao, and I. Galton, “A 3.5 GHz Digital Fractional-N Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2988-3002, December 2015]. As explained in [C. Weltin-Wu, E. Familier, and I. Galton, “A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], p[n] is given by (43) where ep[n] is first-order shaped quantization noise that is uncorrelated with the PLL's phase error plus error from both the PEDC and reference oscillator.


The DLF consists of two single-pole IIR stages and a proportional-integral stage. Its transfer function is











L


(
z
)


=



K
M



(


K
P

+


K
I


1
-

z

-
1





)







i
=
0

1




λ
i


1
-


(

1
-

λ
i


)



z

-
1








,




(
52
)







where KM, KP, KI, λ0 and λ1 are constant loop filter parameters. The DCO consists of an LC oscillator core with a power-of-two-weighted coarse capacitor bank, an integer FCE bank 502 and a fractional FCE bank 504 in accordance with FIG. 5. The latter two are driven by the multi-rate DEM encoder 500 shown in FIG. 5 and modified as shown in FIG. 8 with ffast=fPLL/8 and Δmin=40 kHz (i.e., Δ=156.25 Hz).


The static gain error of the ith FCE was modeled as an additive zero-mean Gaussian random variable with a standard deviation of 5% of Δi divided by the square root of Δimin. The FCE frequency transitions were modeled as second-order transients that settle within one Tfast period. The parameters of these transients, such as the damping factor and the natural frequency, are modelled as random variables with means and standard deviations determined from transistor-level simulation results. FIG. 12 shows example frequency transients used in the simulation.


The simulated noise parameters of the DCO and the reference oscillator, as well as the PEDC internal parameters were fref=26 MHz, N=134 and α=0.0003846153, so that fPLL=3.484 GHz and ffast=435.5 MHz. The DLF parameters used were KM=1.25, KP=24, KI=2−4, λ0=2−3 and λ1=2−2, and the MNC gains were set to Ka=2−3 and Kb=2−5. The simulated PLL has a bandwidth of 206 kHz and a phase margin of 63 degrees.



FIG. 13A shows the simulated PLL phase noise PSD with the multi-rate DEM technique disabled, i.e., with the flip-flops in both the slow and fast DEM encoders frozen. The two curves in FIG. 13A were obtained from two different simulations: one in which dI[nt] is constant and another one in which dI[nt] changes frequently. Although the DCO input sequence does not vary significantly in the short term once the PLL is locked, its moving average drifts over time such that dI[nt] eventually begins to change frequently, at which point it degrades the PLL's phase noise as shown in FIG. 13A. Once the multi-rate DEM technique is enabled, whether or not dI[nt] changes has no significant effect on the DCO's frequency, so spectral breathing no longer occurs.



FIG. 13B shows the simulated PLL phase noise PSD with the multi-rate DEM technique enabled for two cases: one case with just static gain errors, and the other case with just non-ideal frequency transitions. FIG. 13C shows the simulated PLL phase noise PSD considering both sources of error with the multi-rate DEM technique enabled and with the MNC technique disabled and enabled. The theoretical PLL phase noise PSD for ideal FCEs, which was computed using the linearized model presented in [C. Weltin-Wu, E. Familier, and I. Galton, “A Linearized Model for the Design of Fractional-N PLLs based on Dual-Mode Ring Oscillator FDCs,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015], is also plotted as the dashed curves in FIGS. 13A-13C to provide a comparison baseline.


As shown in FIG. 13A, when the MNC technique is enabled the resulting phase noise PSD matches the theoretically-predicted phase noise PSD for ideal FCEs after 13·107 reference periods (5 seconds) from a cold start. This implies a phase noise improvement of more than 20 dB at an offset frequency around 10 MHz. As the FCE mismatches are mostly determined by circuit component mismatches, they are not expected to change significantly over time. Hence, once obtained, the MNC coefficients can be stored in memory and used subsequently by the PLL, thereby avoiding future convergence time delays.



FIG. 14 shows the evolution of the MNC coefficient errors over time from the simulation used to generate the curves in FIG. 13C. As shown in FIG. 14, some bk,r[n] coefficients initially move away from their ideal values. As explained above, this happens because the top and bottom branches of each sk,r[nt] residue estimator interfere with each other so that the error estimate at the input of each accumulator is biased by the MNC coefficient error of the opposite branch. If the MNC gains are set as in FIGS. 14A and 14B, this is not a problem because this effect becomes less significant as either one or both MNC coefficients approach their ideal values.


It follows from (46) and (47) that the terms proportional to ak,r-error[n] in p[n] are qn−3 times larger than those proportional to bk,r-error[n] (e.g., qn≅16 in the design example), so for Ka=Kb, the error variance of each bk,r[n] is expected to be larger than that of ak,r[n]. Therefore, in order to make the error variance of the bk,r[n] coefficients comparable to that of the ak,r[n] coefficients, Kb has to be smaller than Ka. As shown in FIGS. 14A & 14B, this causes the bk,r[n] coefficients to converge to their ideal values at a slower rate than the ak,r[n] coefficients, so the convergence speed of the MNC technique is limited by Kb. Nonetheless, it follows from FIGS. 14A & 14B that the ak,r[n] coefficients get close to their ideal values in less than 107 reference periods (˜0.4 seconds). Hence, as the most significant sources of phase noise are the FCE static gain errors, the MNC method allows for a considerable phase noise improvement in less than half a second.


To reduce the cold-start convergence time of the MNC technique, large MNC gains can be used initially and decreased over time. See, W. Y. Chen and R. A. Haddad, “A Variable Step Size LMS Algorithm,” Proc. 33rd Midwest Symp. Circuits and Systems, pp. 423-426, August 1990. FIGS. 15A and 15B shows the evolution of the MNC coefficient errors over time for 7.8.107 reference periods (3 seconds) for an example case in which Ka and Kb are initially set to 2−1 and 2−2, respectively, and then divided by two at the times indicated by the vertical dashed lines. In this case, the MNC coefficients reach the final values shown in FIGS. 14A & 14B in roughly 3 seconds, and the ak,r[n] coefficients get close to their ideal values in less than 2·106 reference periods (˜0.08 seconds), which is five times faster than in FIGS. 14A & 14B.


Appendix A

It follows from FIG. 5 and (17) that











f
I



(
t
)


=




i
=
5

22




[



(



b
i



[

w
t

]


-

1
/
2


)




α
i



(
t
)




Δ
i


+


(



b
i



[


w
t

-
1

]


-

1
/
2


)




γ
i



(
t
)




]

.






(
53
)







Expressions for each bi[wt]=ci+12[g(wt)] in terms of d[g(wt)] and the switching sequences can be found by tracing through the tree of FIG. 6 and applying (20) and the expressions shown in FIG. 4(a) and FIG. 4(b). This leads to













c
i



[

g


(

w
t

)


]


-

1
/
2


=



m
i




d


[

g


(

w
t

)


]


/
Δ


+




k
,
r








κ

k
,
r
,
i





s

k
,
r




[

g


(

w
t

)


]






,




(
54
)







where






m
i=0 for 17≤i≤26 and mi=2−16 for 27≤i≤34,  (55)


and each xk,r,i is one of 0, −½, ½, 2−k or 2−k. Combining (4)(19) and (53)-(55) yields (26) and (27), where αI(t) and γI(t) are the averages of αi(t) and (2−13/Δ)γi(t) for i=15, 16, . . . , 22, respectively,











α

k
,
r




(
t
)


=





i
=
5

22





α
i



(
t
)




K

i
+
12




κ

k
,
r
,

i
+
12








and







γ

k
,
r




(
t
)




=




i
=
5

22






γ
i



(
t
)


Δ




κ

k
,
r
,

i
+
12



.








(
56
)







Each αI(t), γI(t), αk,r(t) and γk,r(t) is Tfast-periodic, because it is a linear combination of αI(t) and γi(t), which are Tfast-periodic.


Appendix B

The phase error of the digital PLL shown of FIG. 9 is given by





θPLL(t)=∫0tψvPLL(u)du,  (57)


where ψPLL(t) is the PLL's frequency error at time t. The θPLL[n] term in (43) is a sampled version of θPLL(t) given by





θPLL[n]=θPLLn),  (58)


where τn=nTref+ and λn is a small implementation-dependent deviation of τn from its ideal value. It follows from (43), (57) and (58) that











p


[
n
]


=


p


[
0
]


-


T
ref






i
=
1

n




ψ
PLL



[
i
]




+


e
p



[
n
]




,




(
59
)







where











ψ
PLL



[
i
]


=


1

T
ref







τ

i
-
1



τ
i






ψ
PLL



(
u
)



du







(
60
)







is the PLL's average frequency error over the time interval [τi,1, τi] and p[0] is the initial value of p[n]. FIG. 9 and (60) imply that eR(t) causes a term in ψPLL[i] given by












{


e
R

*
h

}



[
i
]


=




j
=
0






h


[
j
]





e
R



[

i
-
j

]





,




(
61
)





where












e
R



[
i
]


=


1

T
ref







τ

i
-
1



τ
i






e
R



(
u
)



du







(
62
)







and h[j] is the impulse response of the highpass filtering operation imposed by the PLL on the DCO's additive frequency error as discussed in the description above.


In the design example of the example embodiment λn=4.2Tfast+⅛Tfastv[n], where v[n] is an integer-valued sequence restricted to the set {−6, 5, . . . , 5, 6}, so τn=nTref+4.2Tfast+⅛Tfastv[n]. As the magnitude of ⅛Tfastv[n] is at most ¾Tfast, its effect is negligible. Furthermore, for the sake of simplicity, τn is assumed to be given by





τnn+4Tfast,  (63)


where μn, as shown FIG. 10B, is a multiple of Tfast. Given that 0<μn−nTref≤Tfast for all n and that Tfast is a small fraction of Tref, this approximation does not significantly affect the following results. Substituting Error! Reference source not found. with ak,r and bk,r replaced by ak,r[g(wt)] and bk,r[g(wt)], respectively, into (35), and the result of this operation and (63) into (62) yields











e
R



[
i
]


=


Δ

T
ref








μ

i
-
1


+

4


T
fast





μ
i

+

4


T
fast







{



(


δ

k
,
r


-


α
F




a

k
,
r




[

g


(

w
t

)


]




)




s

k
,
r




[

g


(

w
t

)


]



+


(



γ

k
,
r




(
t
)


-


α
F




b

k
,
r




[

g


(

w
t

)


]




)



(



s

k
,
r




[

g


(


w
t

-
1

)


]


-


s

k
,
r




[

g


(

w
t

)


]



)



}



dt
.








(
64
)







Given that t∈[μn, μn+1) implies g(pt)=n−1, it follows that g(wt)=i−2 for t∈[μi−1+Tfast, μi+Tfast) and g(wt)=i−1 for t∈[μi+Tfast, μi+Tfast), so (64) can be written as












e
R



[
i
]


=


-
Δ





α
F



T
fast



T
ref







k
,
r







{



γ

k
,

r
-
a





[

i
-
1

]


+


y

k
,

r
-
b





[

i
-
1

]



}




,




(
65
)







where yk,r-a[i] and yk,r-b[i] are given by (46) and (47), respectively, and it has been assumed that qi=(μi+1−μi)/Tfast is greater than 3 for all i (e.g., qi≅16 in the design example). Substituting (65) into (61) and the result into (59), rearranging terms and considering that sk,r[n]=0 for n<0 gives (44) and (45)


While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.


Various features of the invention are set forth in the appended claims.

Claims
  • 1. A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC), comprising: a phase error to digital converter;a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator;a digitally controlled oscillator (DCO) with a multi-rate DEM encoder driving an integer bank of frequency control elements and a fractional bank of frequency control elements; andadaptive mismatch-noise cancellation logic operating to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero FCE static and dynamic mismatch error.
  • 2. The digital fractional-N phase locked loop of claim 1, wherein the updating of the MNC coefficient values is conducted once for each time the phase error of the PLL is measured.
  • 3. The digital fractional-N phase locked loop of claim 1, wherein the multi-rate DEM comprises: a slow DEM encoder that drives the integer bank of frequency control elements and a second order ΔΣ modulator; and a fractional path, wherein the fractional path includes the second-order digital ΔΣ modulator driving a fast DEM encoder that drives the fractional bank of frequency control elements, wherein the second-order digital ΔΣ modulator and fast DEM encoder are clocked at a higher frequency compared to that of the slow DEM encoder.
  • 4. The digital fractional-N phase locked loop of claim 3, wherein the ΔΣ modulator's quantization noise is asymptotically independent of its input and dither sequences used in the ΔΣ modulator.
  • 5. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic injects an MNC correction sequence, which is computed from the MNC coefficient values and the switching sequences generated inside the slow DEM encoder, into the fractional path.
  • 6. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients with a least-mean-square (LMS)-like algorithm.
  • 7. The digital fractional-N phase locked loop of claim 3, wherein the adaptive mismatch-noise cancellation logic estimates the ideal MNC coefficients based on the statistical properties of switching sequences generated inside the slow DEM encoder.
PRIORITY CLAIM AND REFERENCE TO RELATED APPLICATION

The application claims priority under 35 U.S.C. § 119 and all applicable statutes and treaties from prior provisional application Ser. No. 62/722,276, which was filed Aug. 24, 2018, and is incorporated by reference herein.

STATEMENT OF GOVERNMENT INTEREST

This invention was made with government support under grant number 1617545 awarded by National Science Foundation. The government has certain rights in the invention.

Provisional Applications (1)
Number Date Country
62722276 Aug 2018 US