Patent Application
20230221742
The present application claims priority to India Provisional Patent Application No. 202241001907, which was filed Jan. 13, 2022, is titled “GATE ENHANCEMENT DETECTION SCHEME FOR POWER FET WITH MULTIPLE SEGMENTS AND INDIVIDUAL GATE CONTROLS,” and is hereby incorporated herein by reference in its entirety.
Some transistors, such as field effect transistors (FETs) are implemented in application environments in which a comparatively large amount of current flows through the FETs. The large current flow causes a corresponding large amount of power dissipation by the FETs. An example of such a FET is a power FET. As power dissipation increases, so too does temperature. As the temperature of a power FET increases, the possibility of potentially catastrophic thermal runaway in the power FET increases.
In some examples, an apparatus includes a field effect transistor (FET) having first and second segments, in which the first segment has a first gate, a first source and a first drain, the second segment has a second gate, a second source and a second drain, the first and second sources are coupled together, and the first and second drains are coupled together. The apparatus also includes first and second voltage-to-current circuits, the first voltage-to-current circuit coupled to the first gate, and the second voltage-to-current circuit coupled to the second gate. The apparatus also includes a current selection circuit having a current selection circuit output and first and second current selection inputs, the first current selection circuit input coupled to the first voltage-to-current circuit, and the second current selection circuit input coupled to the second voltage-to-current circuit. The apparatus also includes a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the current selection circuit output, and the comparator configured to receive a reference signal at the second comparator input.
In some examples, an apparatus includes voltage-to-current circuits coupled to respective gates of a multi-segment FET, the voltage-to-current circuits configured to convert voltages from the gates of the FET into respective currents. The apparatus also includes a current selection circuit coupled to the voltage-to-current circuits, the current selection circuit configured to select a highest value current from among the respective currents. The apparatus also includes a comparator coupled to the current selection circuit, the comparator configured to compare the selected highest current to a reference current.
In some examples, a system includes a multi-segment FET having first and second segments, each of the first and second segments having a respective gate, source, and drain, wherein the source of the first segment and the source of the second segment are coupled together, and the drain of the first segment and the drain of the second segment are coupled together. The system also includes an enhancement detection circuit coupled to the multi-segment FET. The enhancement detection circuit includes first and second voltage-to-current circuits, the first voltage-to-current circuit coupled to the gate of the first segment, and the second voltage-to-current circuit coupled to the gate of the second segment. The enhancement detection circuit also includes a current selection circuit having a current selection circuit output and first and second current selection inputs, the first current selection circuit coupled to the first voltage-to-current circuit and the second current selection circuit input coupled to the second voltage-to-current circuit. The enhancement detection circuit also includes a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the current selection circuit, and the second comparator input configured to receive a reference signal. The system also includes a protection circuit coupled to the comparator output and the multi-segment FET, the protection circuit configured to electrically decouple the multi-segment FET from a power source responsive to an asserted value at the comparator output, the asserted value indicating that the multi-segment FET is operating in a linear region of operation.
As described above, in some application environments power FETs are subject to conditions that may increase a possibility of thermal runaway. In an example, thermal runaway in a power FET occurs as a result of positive thermal feedback. For example, a rise in temperature of the power FET (such as due to current interacting with the power FET) induces an occurrence of a condition which causes further temperature rise, which further induces the condition, and so on and so forth such that the temperature of the power FET increases uncontrollably. A power FET that experiences thermal runaway may have degraded future performance after the thermal runaway, or may be destroyed or otherwise rendered unsuitable for its intended purpose. To protect against thermal runaway, junction temperature of the power FET, current flowing through the power FET, a region of operation of the power FET, or a combination thereof may be monitored. For power FETs that are large in surface area, such as to facilitate increased current flow, a temperature gradient may occur on the surface such that two points on the surface of power FET which are sufficiently spaced apart may have a considerable temperature difference. In some examples, the spacing may be about 50 micrometers (μm) or more and the temperature difference may be about 3 degrees Celsius or greater. As a result, a single-point temperature measurement may be inaccurate or have limited viability for such a power FET. Similarly, current densities across the power FET surface may vary between two points on the surface of the power FET which are sufficiently spaced apart. As a result, a single-point current measurement may be inaccurate or have limited viability for such a power FET.
To mitigate these challenges, a power FET may be divided into multiple segments. Each segment may have its own corresponding temperature and current monitoring. Each segment may also have its own independent control. For example, based on the monitoring, current through one segment may be modified based on the independent control without modifying current though another of the segments. The independent segment control may create additional challenges, such as synchronization among the segments and detection of a region of operation of each segment of the power FET. For example, at startup of the power FET each of the segments may be in a saturation region of operation and the power FET is deemed to have successfully started-up responsive to all segments of the power FET transitioning to operate in a linear region of operation. To make such a determination, a gate of each segment may be monitored to determine whether the gate is fully enhanced. In non-segmented power FETs, a gate to source voltage (Vgs) of the power FET may be compared to a programmed voltage to determine whether the gate is fully enhanced. Such an implementation includes a fixed reference source and a comparator. Thus, for a segmented power FET having N segments, N fixed reference sources and N comparators may be implemented to perform the detection. However, such an implementation may be size and power consumption prohibitive, making it infeasible for practical application environments.
Examples of this description include a gate enhancement detection circuit for multi-segment FETs. The gate enhancement detection circuit includes a voltage-to-current (V-I) circuit, a current selection circuit, and a comparator. In some examples, the gate enhancement detection circuit includes, or is coupled to, a reference generator circuit. The V-I circuit includes components suitable for detecting a voltage provided at each gate of the segments of the power FET and converting the voltages to currents to provide to the current selection circuit. In an example, the V-I circuit includes multiple separate V-I circuits, where each of the separate V-I circuits corresponds uniquely to the gate of one segment of the multi-segment power FET. The current selection circuit includes components suitable for selecting a current having a highest value from among the respective currents received by the current selection circuit from the V-I circuit. An output of the current selection circuit is provided to a first input of the comparator, where a current representative of a reference voltage (e.g., a programmed voltage) provided by the reference generator circuit is provided to a second input of the comparator. Responsive to the comparator providing a comparison result having an asserted value (e.g., the output of the current selection circuit being greater in value than the current representative of the reference voltage), the multi-segment power FET is determined to be in the linear region of operation. Responsive to the comparator providing the comparison result having a deasserted value (e.g., the output of the current selection circuit not being greater in value than the current representative of the reference voltage), the multi-segment power FET is determined to not be in the linear region of operation. Based on a determination of the power FET operating in the linear region of operation circuit safety or protection features may be activated, such as active current balancing.
In an example, the monitoring circuit 112 monitors the power FET 110 to determine whether each gate of the power FET 110 is in an enhanced state such that the power FET 110 is in a linear region of operation. To perform the monitoring, the monitoring circuit 112 includes a V-I circuit 114, a current selection circuit 116, a reference generator 118, a V-I circuit 119, and a comparator 120. A number of inputs and outputs of the V-I circuit 114 may be equal to a number of segments of the power FET 110. For example, for a power FET 110 having N segments, the V-I circuit 114 may include N inputs and outputs. Each V-I circuit 114 input is coupled to a respective gate of the power FET 110 and each V-I circuit 114 output is coupled to a respective input of the current selection circuit 116. The current selection circuit 116 has an output coupled to a first input of the comparator 120. The reference generator 118 has an output coupled to an input of the V-I circuit 119, which has an output coupled to a second input of the comparator 120. In various examples, the V-I circuit 119 has an architecture similar to the V-I circuit 114. The comparator 120 provides a comparison result at its output that indicates whether each gate of the power FET 110 is in an enhanced state, such that the power FET 110 may be determined to be in a linear region of operation. In an example, the controller 106 makes the determination that the power FET 110 is in the region of operation based on the comparison result having an asserted value (e.g., indicating that an output signal of the current selection circuit 116 is greater in value than an output signal of reference generator 118).
In an example, each resistor 202 is coupled between a power supply (not shown) and a source of a respective PMOS 204. The power supply may be a same power supply as is coupled to the power FET 110. For example, the power supply may be the power supply 102. An output of a respective branch of the V-I circuit 114 is provided at a drain of the PMOS 204 of that respective branch. In an example, the V-I circuit 114 is configured to convert a voltage value to a current representation. For example, for each gate of the power FET 110, the V-I circuit 114 provides a corresponding signal having a current representative of a voltage provided at the gate of the power FET 110. In at least some implementations, as the gate voltage (Vg) of a gate of a segment of the power FET 110 increases, a gate to source voltage (Vgs) of a PMOS 204 coupled to that gate decreases. As Vgs of a PMOS 204 decreases, current flowing through that PMOS 204 correspondingly decreases. Conversely, as Vg of a gate of a segment of the power FET 110 increases, Vgs of a PMOS 204 coupled to that gate increases. As Vgs of a PMOS 204 increases, current flowing through that PMOS 204 correspondingly increases. As an amount of enhancement of a gate of the power FET 110 increases, a current flowing through a branch of the V-I circuit 114 coupled to that respective gate decreases, and vice versa. Thus, a segment of the power FET 110 that is most enhanced from among all segments of the power FET 110 will correspond to a branch of the V-I circuit 114 that provides a signal having a lowest value current from among all output signals of the V-I circuit 114. Conversely, a segment of the power FET 110 that is least enhanced from among all segments of the power FET 110 will correspond to a branch of the V-I circuit 114 that provides a signal having a highest value current from among all output signals of the V-I circuit 114.
In an example, a quiescent current of the V-I circuit 114 is reduced resulting from the PMOS architecture of the V-I circuit 114. For example, as the power FET 110 reaches steady-state (e.g., a voltage provided at a gate of the power FET 110 reaches its largest value in the system 100), the gate and source of the PMOS 204 are at approximately a same potential, thus causing approximately no current to flow through the PMOS 204.
In an example of operation, the each branch of the current selection circuit 116 compares the input currents received from the V-I circuit 114 and selects a current having a highest value from among the received currents. The current having the highest value is mirrored to a transistor 306, which has a gate coupled to the gates of the transistors 302, a source coupled to the ground terminal, and at which an output signal of the current selection circuit 116 is provided. For example, the transistors 302 are arranged in a current mirror arrangement such that the gates of the transistors 302 are coupled together. The current mirror is enabled through transistors 304, which are coupled in a source follower arrangement. Accordingly, a gate voltage of each transistor 302 has an approximately same value and is determined according to a highest value current flowing between the drain and source of a transistor 302 of the current selection circuit 116. Resulting from the source follower arrangement, a value provided at the gates of the transistors 304 is also provided at the source of the transistors 304, and therefore at the gates of the transistors 302. Because the transistor 306 has a gate coupled to the gates of the transistor 302, the highest value current at the gates of the transistors 304 and flowing between the drain and source of a corresponding transistor 304 is mirrored to flow through the transistor 306.
In an example, to provide the reference signal, the reference generator 118 includes a resistor 402 and a transistor 404. The resistor 402 is coupled between a drain of the transistor 404 and terminal 406 at which a reference current (IREF) is received. In some examples, the reference current is received from a reference source, such as a bandgap reference circuit (not shown). The transistor 404 has a gate coupled to its drain and a source coupled to the source of the power FET 110. In an example, the reference generator 118 is configured to provide VREF at the terminal 406. In some examples, the transistor 404 is a replica of the power FET 110 such that the power FET 110 and the transistor 404 have an approximately same threshold voltage (Vt). In an example, VREF has a value determined according to Vt and the output voltage of the power FET (VOUT), as described above, such as according to the following equation 1. In an example, the resistor 402 has a resistance value such that a voltage provided at the gate of the transistor 404 is 1.4 volts (V).
VREF=VOUT+Vt+1.4 (1)
In an example, an output stage 502 of the monitoring circuit 112 includes the comparator 120, a resistor 504, and a resistor 506. The resistor 504 is coupled between a first input (e.g., a non-inverting input) of the comparator 120 and the ground terminal. The resistor 506 is coupled between a second input (e.g., an inverting input) of the comparator 120 and the ground terminal. An output signal of the current selection circuit 116 is provided to the first input of the comparator 120. In some examples, a current mirror 508 mirrors the current from the transistor 306 to the first input of the comparator 120. An output signal of the V-I circuit 119 is provided to the second input of the comparator 120. The comparator 120 compares the signals received at its first and second inputs and provides a comparison result having a value determined based on the comparison. For example, responsive to the signal received at the first input of the comparator 120 having a value that exceeds a value of the signal received at the second input of the comparator 120, the comparator 120 provides the comparison result having an asserted value. Responsive to the signal received at the first input of the comparator 120 having a value that does not exceed the value of the signal received at the second input of the comparator 120, the comparator 120 provides the comparison result having a deasserted value. In some examples, the comparison result having the asserted value indicates that the power FET 110 is operating in the linear region of operation (and each gate of the power FET 110 is in an enhanced state). Conversely, the comparison result having the deasserted value indicates that the power FET 110 is not operating in the linear region of operation (and at least one gate of the power FET 110 is not in an enhanced state).
At operation 602, gate voltages of a multi-segment power FET are received. In an example, the gate voltages are received by a V-I circuit, such as the V-I circuit 114, as described above herein. At operation 604, current representations of the gate voltages are provided. In some examples, the V-I circuit is configured to convert the gate voltages to currents to form the current representations. At operation 606, a current representation having a highest value current from among the current representations is selected. In an example, the selection is performed by a current selection circuit, such as the current selection circuit 116, as described above herein. At operation 608, the selected highest current is compared to a reference current. In an example, the comparison is performed by a comparator, such as the comparator 120, as described above herein. At operation 610, the comparator provides a comparison result indicating whether the multi-segment power FET is operating in the linear region of operation (e.g., each gate of the multi-segment power FET is in an enhanced state).
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof
A circuit or device that is described herein as including certain components may instead be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture by an end-user and/or a third-party.
While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
Uses of the phrase “ground voltage potential” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 20241001907 | Jan 2022 | IN | national |
