Claims
- 1. In a computer network having a multi-set cache structure which includes a small first level cache and a large second level cache supporting a central processor, said second level cache providing a set of Tag RAMs holding address words of two bytes each with two status bits V,R, while also providing a set of corresponding parity RAMs for storing a parity bit (P1, P2) for each byte of each address words and a parity bit Ps for each set of status bits V,R, a predictive logic generation system for generating, during each processor operation (OP), the proper status bits V,R and the proper parity bit (Ps) for each pair of status bits V,R for each address word in said cache structure comprising:
- (a) said second level cache including multiple sets of RAMs where each set has a Tag RAM holding said address words and a Parity RAM for holding a parity value P1, P2 for each of said two address word bytes and a parity value Ps for said two status bits V,R;
- (b) means to sense the value of each of said two status bits V,R and the type of OP cycle being executed in order to simultaneously generate, concurrently with the processor operation, the exactly proper status bits V,R, and the parity bit Ps values for each address word in each set of Tag RAMs;
- (c) means to place said exactly proper status bits V, R and parity values, Ps into the correspondingly addressed location in each set of said Tag and Parity RAMs.
- 2. The system of claim 1 wherein said two status bits V,R in each address word include:
- (i) a valid bit V which indicates the validity/invalidity of each address word in each Tag RAM set of said second level cache;
- (ii) a Reflection bit R which indicates whether said first level cache holds a copy of an address word residing in said second level cache.
- 3. The system of claim 1 wherein said means to sense includes:
- (a) programmable array logic means connected to each cache set of said multi-set cache structure, including:
- (a1) means to read out the value of each one of said two status bits V,R in each said address word in said Tag RAM;
- (a2) means to sense the type of OP being executed by said central processor;
- (a3) means to reset the two status bits V,R for each address word in said Tag RAM during execution of the processor OP;
- (a4) means to predict the proper parity value for said two status bits V,R of each addressed word according to the type of processor OP involved, including:
- (a4a) means to generate and place, in said Parity RAM, the proper parity bit value Ps for said status bits (V,R);
- (a4b) means to generate and place in said Tag RAM, the proper status bits V,R for each address word involved in a processor OP.
- 4. In a computer network with central processor having a multi-set cache structure which includes a small first level cache holding a data word of two bytes plus a validity bit, V, and a large second level cache providing a set of Tag RAMs and associated Parity RAMs which also support said central processor, wherein each Tag RAM location in said second level cache holds an address data word of two bytes with two status bits (V,R) and wherein said second level cache also provides a separate parity RAM for each Tag RAM for holding the parity values (P1,P2) associated with each address word and a parity bit, Ps, for each set of the two status bits, (V,R), each said Tag RAM and parity RAM connected to a predictive logic means which predicts, creates and controls parity operations, a method for predictively generating the two status bits (V,R) and the proper parity bit Ps for each set of the two status bits occurring in each address data word of said cache RAM structure which is involved in a processor OP, said method comprising the steps of:
- (a) receiving, by said predictive logic means, a signal indicating the current processor bus operation (OP);
- (b) receiving, by said predictive logic means, a signal indicating that it is to be checking for "hits" in the Tag RAM;
- (c) receiving, by said predictive logic means, of a "hit" signal indicating that a requested address has been located in the Tag RAM;
- (d) receiving, by said predictive logic means, of an invalid signal indicating the occurrence of an invalidation operation to determine if the valid bit, V, should be turned off at a given address;
- (e) sensing the values of the said two status bits V,R, before the processor OP completion;
- (f) generating a new set of predicted status bits (V,R) simultaneously during a processor OP and simultaneously generating a new parity bit (Ps) for the status bits (V,R).
- 5. In a computer network having a central processor connected via a datapath array to dual system busses supporting a main memory module and I/O module, said network having a multi-set cache structure which includes a small first level cache holding an address data word of two bytes plus a validity bit, V, and a large second level cache including a set of Tag RAMs and a set of Parity RAMs also supporting said central processor, wherein each Tag RAM location in said second level cache set holds an address data word of two bytes with two status bits V,R, where V represents the validity of the data and R indicates that the first level cache has duplicate address information to the second level cache location, a system for obviating the need to calculate parity values and status bit values during processor operations comprising:
- (a) said multi-set cache structure including n sets of first level cache units and n sets of second level cache units wherein each of said second level cache units includes a Tag RAM for holding address data words of two bytes with two status bits V,R for each address data word and includes a parity RAM for holding parity bits P1, P2, associated with each byte of said address data word and a parity bit Ps for each set of status bits (V,R);
- (b) means to connect said central processor to each of said Tag RAMs and parity RAMs;
- (c) predictive logic means connected to each of said Tag RAMs and parity RAMs, said predictive logic means including:
- (c1) means to sense the processor OP initiated by said central processor;
- (c2) means to create the status bits V,R for each address word in said Tag RAM, simultaneously and by prediction from the type of processor OP occurring;
- (c3) means, simultaneously with the processor OP, to create the predicted proper parity bit Ps for each set of status bits (V,R);
- (d) parity check means for checking the parity of each address data word which is read out from said Tag RAM;
- (e) said data path array means connecting said dual system busses from a main memory module and I/O module to said central processor, and to said predictive logic means and to said n sets of second level cache units;
- (e) spy logic means connected to said dual system busses for transmitting address data word signals to said second level cache for invalidation operations if a hit should occur.
- 6. The system of claim 5 wherein said predictive logic means includes:
- (a) a programmable logic array programmed to simultaneously generate the necessary status bits V,R, and parity bit, Ps, for each type of processor OP occurring for each prior status condition of an address data word operated on by said processor OP.
- 7. The system of claim 5 wherein said predictive logic means includes:
- (i) means to write the generated status bits V,R, into the location of the addressed data word;
- (ii) means to write the generated parity bit, Ps,.to the Parity RAM location corresponding to the addressed data word.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to two co-pending applications, the first of which is U.S. Ser. No. 592,092 filed Jan. 26,1996 and entitled "Smart Fill Logic Allowing Full Efficiency of Multi-Way Cache System". This application is also related to another pending patent application, U.S. Ser. No. 592,093 filed Jan. 26,1996 and entitled "Processor Bus Traffic Optimization System for Multi-Level Cache Utilizing Reflection Status Bit."
US Referenced Citations (8)