FIELD OF THE INVENTION
This invention relates to wireless communication systems and, more particularly, to methods and apparatus for individually controlling the transmitted power level of each signal burst in wireless systems. The invention is particularly useful in TDSCDMA wireless systems, but is not limited to TDSCDMA systems.
BACKGROUND OF THE INVENTION
TDSCDMA (Time Division Synchronous Code Division Multiple Access) is one of the third generation wireless communications standards. Different from WCDMA and CDMA 2000, which adopt a frequency division multiplex, TDSCDMA is designed for time division duplex/multiple access (TDD/TDMA) operation with synchronous CDMA technology.
The TDSCDMA system uses time domain duplexing in combination with multiple access techniques to support both symmetrical and asymmetrical traffic. The variable allocation of time slots for uplink or downlink traffic allows TDSCDMA to meet asymmetric traffic requirements and to support a variety of users. In TDSCDMA systems, multiple access techniques employ both unique codes and time slots to separate the users in a given cell. The TDSCDMA standard defines a frame structure with three layers: the radio frame, the subframe and the time slot. The radio frame is 10 milliseconds. The subframe is 5 milliseconds and is divided into seven time slots. A time slot has four parts: a midamble, two data fields on each side of the midamble and a guard period. The receiver uses the midamble to perform channel estimation.
High data rate services in TDSCDMA systems require that user equipment (UE) be capable of transmitting multiple consecutive time slots per subframe. Each time slot may require a different transmission power level due to different quality of service (QoS), spreading factors, number of physical channels, etc. However, abrupt changes in transmitted power level can produce spurious outputs and distortion of the signal waveform.
Prior art systems such as GSM/EDGE wireless systems have used an approach where a gain control signal is ramped on and ramped off during a signal burst. As shown in FIG. 6, signal bursts 10 and 12 are controlled by gain control signals 14 and 16, respectively. The signal bursts have relatively fast rise and fall times, and the gain control signals for each signal burst are ramped on and ramped off during the signal bursts. Output signal bursts 18 and 20 are ramped as a result of the ramped gain control signal. This approach adds complexity and is not satisfactory in some applications.
Accordingly, there is a need for improved methods and apparatus for wireless uplink transmission power control.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method is provided for controlling transmitted power in a wireless system. The method comprises generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts.
According to a second aspect of the invention, apparatus is provided for controlling transmitted power in a wireless system. The apparatus comprises a signal generation unit configured to generate a series of signal bursts, with a time interval between successive signal bursts, an amplifier configured to control individually a power level of each of said signal bursts in response to a power control signal to provide output signal bursts to be transmitted, and a power control circuit configured to generate the power control signal in response to a power value and timing information that correspond to each of the signal bursts, a new power value of the power control signal being asserted during the time interval preceding each signal burst.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference and in which:
FIG. 1 is a simplified block diagram of a TDSCDMA transmitter;
FIG. 2 is a schematic representation of the TDSCDMA data (slot) structure;
FIG. 3 is a simplified block diagram of power control apparatus in accordance with an embodiment of the invention;
FIG. 4 is a timing diagram that illustrates uplink transmission power control in accordance with an embodiment of the invention;
FIG. 5 is a simplified block diagram of a portion of a TDSCDMA transmitter, illustrating possible locations for transmission power control; and
FIG. 6 is a timing diagram that illustrates transmission power control in accordance with the prior art.
DETAILED DESCRIPTION
A simplified block diagram of an uplink transmitter 30 for a TDSCDMA wireless device is shown in FIG. 1. A digital baseband (DBB) circuit 40 generates a digital uplink signal to be transmitted to a base station. The digital baseband circuit 40 may include a control processor such as a programmable digital signal processor (DSP). The DSP may include a core processor, a memory, a DMA controller and various interface circuits. The digital baseband circuit 40 may also include one or more coprocessors. As discussed below, digital baseband circuit 40 generates a digital uplink signal to be transmitted, in the form of signal bursts. The digital uplink signal is supplied to an analog baseband (ABB) circuit 44, which processes the digital uplink signal in the analog domain and supplies an analog uplink signal to a radio 50. The analog uplink signal is transmitted by radio 50 via an antenna 52.
A schematic representation of the TDSCDMA data structure is shown in FIG. 2. Data is transmitted as a series of radio frames 60, 62, etc., each having a duration of 10 milliseconds. Each radio frame is divided into two subframes 64 and 66, each having a duration of 5 milliseconds. Each subframe is made up of seven time slots 70, 72, etc., each having a duration of 0.675 millisecond, and a special time interval 80 between time slots TSO and TS1. Each time slot includes four parts, a midamble with 144 chips duration, two data fields with 352 chips duration before and after the midamble, followed by a guard period of 16 chips. The midamble contains known data and is used by the receiver to perform channel estimation.
The seven time slots in each subframe may be divided between uplink and downlink traffic, according to the traffic in each direction. According to the TDSCDMA protocol, first time slot TSO is always a downlink time slot, second time slot TS1 is always an uplink time slot, and the remaining five time slots TS2-TS6 can be used for uplink or downlink traffic, with the restriction that the subframe cannot include more than two transitions between uplink and downlink time slots. The first transition is in the special time interval 80.
A simplified block diagram of power control apparatus in accordance with an embodiment of the invention is shown in FIG. 3. A signal generation unit 100 generates an uplink signal for transmission to a base station. The uplink signal includes a series of signal bursts, which may be time slots of a TDSCDMA subframe, as shown in FIG. 2 and described above. However, other communication protocols may be utilized within the scope of the invention. The signal generation unit 100 may be incorporated into digital baseband circuit 40, analog baseband circuit 44, or both, shown in FIG. 1 and described above. The signal bursts are processed by an amplifier 110 to provide a controlled output. The amplifier 110 may be incorporated into analog baseband circuit 44 or radio 50 shown in FIG. 1. The controlled output may be supplied to antenna 52 for transmission or may undergo further processing before transmission.
A power control circuit 120 supplies a power control signal to amplifier 110. The power control signal is based on a power value and timing information received from signal generation unit 100. The power control signal may be a gain control signal for amplifier 110. The power control circuit 120 may be incorporated into digital baseband circuit 40 or analog baseband circuit 44. The magnitude of the power control signal is based on the power value received from the signal generation unit 100, and the timing of the power control signal is based on the timing information received from signal generation unit 100. Details of the power control signal are described below in connection with FIG. 4.
Several consecutive uplink time slots TS1, TS2 and TS3 of a TDSCDMA subframe are shown in FIG. 4. An uplink signal 200 includes a signal burst 202 during time slot TS1, a signal burst 204 during next time slot TS2, and a signal burst 206 during next time slot TS3. Each signal burst contains information to be transmitted, such as data or voice signals. Signal bursts 202, 204 and 206 may be generated by signal generation unit 100 shown in FIG. 3. Signal burst 202 includes a ramp-up portion 202a and a ramp-down portion 202b, and signal burst 204 includes a ramp-up portion 204a and a ramp-down portion 204b. The ramp-up portions 202a and 204a and the ramp-down portions 202b and 204b are characteristic of TDSCDMA signal generation.
The signal bursts are generated in a manner to produce a time interval between successive signal bursts. Thus, a time interval 210 precedes signal burst 202, a time interval 212 precedes signal burst 204, and a time interval 214 precedes signal burst 206. During time intervals 210 and 212, no signal is generated or transmitted. The time intervals 210, 212 and 214 occur at the boundaries between time slots of the TDSCDMA subframe and may have a duration of only a few chips.
A power control signal 240 shown in FIG. 4 is used to control the power level of the uplink signal. Power control signal 240 includes a segment 242 in time slot TS1, a segment 244 in time slot TS2, and a segment 246 in time slot 206. As shown, segment 242 has a power value A1, which corresponds to a first power level, segment 244 has a power value A2, which corresponds to a second power level, and segment 246 has a power value A3, which corresponds to a third power level. Thus, the power level of each of the signal bursts in the subframe is individually controlled by the power control signal. As also shown in FIG. 4, segment 242 of power control signal 240 having power value Al is asserted during time interval 210 preceding signal burst 202; segment 244 of power control signal 240 having power value A2 is asserted during time interval 212 preceding signal burst 204; and segment 246 of power control signal 240 having power value A3 is asserted during time interval 214 preceding signal burst 206. In particular, a new power value of the power control signal 240 is asserted during a transition time between time slots of the subframe when the transmitted power is at or near zero. In some embodiments, the power control signal is asserted when the transmitted signal is at least 20 dB less than the nominal power. In operation, the new power value may differ from the power value of the previous time slot or may be the same as the power value of the previous time slot. Furthermore, the power control signal may have a zero power value or a “don't care” condition in downlink time slots.
The power control signal 240 is generated by power control circuit 120 shown in FIG. 3 and responds to power values and timing information provided by signal generation unit 100. In particular, signal generation unit 100 may specify power values A1, A2 and A3 of segments 242, 244 and 246, respectively. The timing information provided by signal generation unit 100 defines the time intervals between signal bursts when the new power value of the power control signal 240 may be asserted. As shown, segments 242, 244 and 246 of power control signal 240 remain constant during respective time slots TS1 and TS2, with no ramping of the power control signal.
A controlled output 260 generated by amplifier 110 (FIG. 3) is shown in FIG. 4. Controlled output 260 includes an output signal burst 262 during time slot TS1, an output signal burst 264 during time slot TS2, and an output signal burst 266 during slot TS3. Output signal burst 262 has a power level P1, which corresponds to power value A1, output signal burst 264 has a power level P2, which corresponds to power value A2, and output signal burst 266 has a power level P3, which corresponds to power value A3. As further shown in FIG. 4, output signal burst 262 includes a ramp-up portion 262a and a ramp-down portion 262b, and output signal burst 264 includes a ramp-up portion 264a and a ramp-down portion 264b. The ramp-up and ramp-down portions of the output signal bursts correspond to the respective ramp-up and ramp-down portions of signal bursts 202 and 204, since power control signal 240 is not ramped. Because the controlled output 260 includes ramp-up portions and ramp-down portions, without abrupt changes in power level, spurious signal generation is limited. In addition, since a constant power control signal is maintained during each time slot, signal distortion is limited.
In the embodiment of FIG. 3, the power level of each signal burst in an uplink signal is controlled individually by applying a power control signal to an amplifier in the form of a gain control signal. In other embodiments, the power level can be controlled at other points in the uplink transmitter. A schematic representation of uplink transmitter 30 is shown in FIG. 5. An uplink bit rate processor and chip rate processor 310 supplies signal bursts through a digital baseband low pass filter 312 and an analog baseband low pass filter 314 to a digital-to-analog converter 320. The digital-to-analog converter 320 converts the digital uplink signal to an analog waveform and thereby serves as an interface between the digital domain and the analog domain. The output of digital-to-analog converter 320 is supplied through an analog baseband low pass filter 322 and an RF low pass filter 324 for transmission. Different locations for controlling the power level of transmitted signal bursts are illustrated schematically and include the analog domain waveform level, the digital domain waveform level and the digital domain chip rate level. In each case, a new power value of the power control signal is asserted during the time interval preceding each signal burst when the transmitted power is at or near zero.
In the embodiments described above, new power values of the power control signal are asserted without ramping of the power control signal. In other embodiments, the power control signal can employ ramping. However, in each case, the new power value of the power control signal is asserted during the time interval preceding each signal burst when the transmitted power is at or near zero.
In the embodiments described above, the power level of each signal burst in an uplink signal is controlled individually. However, the invention is not limited to uplink signals. In other embodiments, the power level of each signal burst in a downlink signal, transmitted from a base station to a wireless device, is controlled individually.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.
Patent Application
20090081973
