Low Noise Amplifiers are circuits for amplifying weak signals such as those received from antennas. It is important that they not introduce much noise given the weak power levels of the received signal. Otherwise, the signal to noise ratio (SNR) of the signal would be unacceptable for data recovery. The effect of the injected noise may be reduced by the gain of the LNA. As such, there is a need for improved LNAs, including those for use in direct conversion transceivers.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed invention, and explain various principles and advantages of those embodiments.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
With reference to
The output of the cascaded LNA stages is further processed in a receiver, such as a polar receiver 110. Additional details of the polar receiver may be found in the application U.S. application Ser. No. 16/840,478, now U.S. Pat. No. 8,929,486, filed Mar. 15, 2013, entitled POLAR RECEIVER ARCHITECTURE AND SIGNAL PROCESSING METHODS. Other well-known receiver architectures may also be used. Each stage of the two LNA stages 104, 108 may be tuned to exhibit a bandpass response. The two center frequencies, one from each stage, may be offset to provide an overall wider frequency bandwidth, yet still providing a high degree of off-band selectivity so as to reject adjacent channels.
With reference to
With reference to
With reference to
Again with respect to
The bandpass filter also include cross-coupled transistors M6, M7 to complete the bandpass load. Note the cross-coupled compensation transistor pair M8, M9. These cross-coupled compensation transistors are biased in a sub-threshold region.
In small signal analysis the two currents flowing into M6 (I1) and M8 (I2) can be written as:
I1=gmM6,1·VRF OUT−+gmM6,2·VRF OUT−2+gmM6,3·VRF OUT−3,
I2=gmM8,1·VRF OUT−+gmM8,2·VRF OUT−2+gmM8,3·VRF OUT−3.
Where gmM6,1, gmM6,2, gmM6,3, gmM8,1, gmM8,2 and gmM8,3 are respectively the first, second and third terms in the Taylor expansion of the current for transistors M6 and M8. The first order term corresponds to the regular small signal gm. For a transistor biased in saturation, the third order term is negative. So if the amplitude of the input signal increases, the current starts to compress. On the contrary, for a transistor biased in the sub-threshold region, the third order term is positive. So if the amplitude of the input signal increases, the current increases accordingly. In
Itot=I1+I2=(gmM6,1+gmM8,1)·Vin+(gmM6,2+gmM8,2)·Vin2.
Because the signals applied to the two branches are differential, the second order term (gmM6,2 gmM8,2)·Vin2 is canceled. In this way, the linear range of the cross-coupled transistor pair M6, M7 is extended by the cross-coupled compensation pair M8, M9.
The quality factor Q of the bandpass load may also be adjusted. In one embodiment, the bias on transistor M10 is adjusted. A very high Q may be used, even as high as 400 or 500, while still maintaining a linearized response from the bandpass load at high output swing (100 mVp). The high-Q tank, or bandpass load, presents a large resistance to the transconductance gain stage, which will therefore produce a large gain from a small current signal. Note also that the high Q provides narrow band selection and high rejection of adjacent bands or channels. The Q may also be reduced by selectively inserting resistances in the tank circuit under the control of the LNA control circuit. Such as resistor bank may be realized as depicted in
Because the high quality factor Q becomes extremely sensitive to the value of transconductance of the cross-coupled pair, −gm/2, small variations of gm may result in a large variation of Q. Thus, linearizing the transconductance of M6 and M7 with the insertion of the sub-threshold biased cross-coupled compensation transistor pair greatly increases the dynamic range of the LNA stages. Without this compensation, a decrease in the Q factor due to large output swing will reduce the gain and increase the response bandwidth, and result in less adjacent channel rejection.
Note also that while the addition of the cross-coupled compensation transistor pair may generate some additional noise, the compensation pair is part of the load, and any additional noise is relatively insignificant because it is not passing through the amplification stage. That is, the noise is injected at the output of the amplifier rather than the input, and thus has a minor impact, especially in a very high gain LNA.
With reference to
The LNA controller 1200 may include a finite state machine to control the circuits and/or modules of the controller. The LNA may be driven to oscillation during one or more steps of the calibration. A frequency detector may comprise a digital divide by M to divide a clock signal, and an analog divide by 4 (or other number) circuit to reduce the frequency of the monitored oscillations from the LNA bandpass load in the form of an LC tank.
The LNA controller may be configured to provide a control output signal on the frequency control output line corresponding to the most significant bits from the coarse tuning circuit, and corresponding to the least significant bits from the fine tuning control circuit. These bits may be used to switch a capacitor bank to alter the resonant frequency of the bandpass load. In the coarse tuning mode, the Q of the LNA may be increased to point of causing the LNA to oscillate. The frequency at which the LNA resonates is related to the peak of the frequency response when not in oscillation. Thus, the oscillatory condition induced in the LNA may be used to coarsely adjust the tank circuit capacitance. In the fine tuning mode, the controller generates one or more tones and measures the amplitudes to determine both a 3 dB point (which measures the Q) as well as the frequency at which a peak output may be obtained, which corresponds to the center frequency of the bandpass filter. Other tones and measurements may also be used to determine a fine calibration of the LNA.
The control output may include multiple parallel bits for controlling the Q factor of the LNA stages. The LNA controller may responsively adjust the Q by altering a bias current in the bandpass load circuit.
With reference to LNA variable gain transconductance stage 400, the variable gain may be achieved by switching either ON or OFF additional transistor devices. One such variable transconductance stage is shown in
In one embodiment, the apparatus comprises a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal, a tunable bandpass filter connected as a load to the variable gain amplifier stage, and a controller circuit configured to tune the bandpass filter. The bandpass filter includes a resonant tank, a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region. That compensation configuration adds a transconductance component when the load driving signal is of a magnitude large enough to decrease the transconductance of the cross-coupled transistor pair. Further, it may include a controller circuit configured to tune the bandpass filter. The bandpass filter may comprise a capacitor bank, and the controller circuit may be configured to adjust the capacitor bank to alter the center frequency of the bandpass filter. The controller circuit may be configured to alter a bias point of the cross-coupled transistors to vary the Q of the tank, to induce an oscillation in the bandpass filter, to measure the resonant frequency of the oscillation, and to adjust the resonant frequency of the bandpass filter. The variable gain stage amplifier may be a transconductance amplifier stage that has a plurality of parallel connected transconductance cells. In addition, the at least one cross-coupled compensation transistor pair may comprise a plurality of parallel-connected cross-coupled compensation transistor pairs. Each of the plurality of parallel-connected cross-coupled compensation transistor pairs may be biased at a different sub-threshold voltage. In an embodiment, a bias control circuit may be configured to adjust a sub-threshold bias voltage of the at least one cross-coupled compensation transistor pair. The control circuit may also be configured to adjust a quality factor Q of the first and second bandpass filters to obtain a desired adjacent channel rejection ratio.
With reference to
An additional method 1400 of
Referring now to
One method of reducing such coupling is to subdivide each inductive coil into two series-connected sub-coils that are wound in opposite directions, e.g. clockwise and counter-clockwise for a planar embodiment. Following conventional practice, each sub-coil may be comprised of one or more metallization layers each having one or more turns. In some embodiments, the multiple turns on a given metallization layer are configured in a helical pattern. In at least one embodiment, the two sub-coils are adjacently located as in a figure ‘8’, thus the term ‘figure-8 patterned inductor’ will be subsequently used to describe any such combination of two sub-coils, without implying limitation.
More specifically, as shown in
Also shown is injection locked oscillator 1540 and mixer with transinductance amplifier 1550. Also shown is analog to digital converter (ADC) 1560 and phase digitizer 1570.
Referring to
In one embodiment, each inductor of each resonant tank is located on a same plane. For example, a manufacturing die could be designed to enable a plane of tunable bandpass filters including inductors aligned on a same plane.
As shown in both
In one embodiment, the apparatus further includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load-driving signal.
In an embodiment, the compensation configuration adds a transconductance component when the load-driving signal is of a magnitude large enough to decrease the transconductance of the cross-coupled transistor pair. Further, it may include a controller circuit configured to tune the bandpass filter. Each bandpass filter may comprise a capacitor bank, and the controller circuit may be configured to adjust the capacitor bank to alter the center frequency of the bandpass filter. The controller circuit may be configured to alter a bias point of the cross-coupled transistors to vary the Q of the tank, to induce an oscillation in the bandpass filter, to measure the resonant frequency of the oscillation, and to adjust the resonant frequency of the bandpass filter. The variable gain stage amplifier may be a transconductance amplifier stage that has a plurality of parallel connected transconductance cells. In addition, the at least one cross-coupled compensation transistor pair may comprise a plurality of parallel-connected cross-coupled compensation transistor pairs. Each of the plurality of parallel-connected cross-coupled compensation transistor pairs may be biased at a different sub-threshold voltage. In an embodiment, a bias control circuit may be configured to adjust a sub-threshold bias voltage of the at least one cross-coupled compensation transistor pair. The control circuit may also be configured to adjust a quality factor Q of the first and second bandpass filters to obtain a desired adjacent channel rejection ratio.
Accordingly, some embodiment of an apparatus includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal, a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters, a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal, and, a controller circuit configured to tune each tunable bandpass filter.
In some embodiments, each inductor of each resonant tank is located on a same plane.
In some embodiments, each inductor is formed in a figure-8 type pattern, the longitudinal axes defining respective lengths of each inductor.
In some embodiments, each tunable bandpass filter includes a capacitor bank, and the controller circuit is configured to adjust the capacitor bank to alter the frequency response of each tunable bandpass filter.
In some embodiments, the controller circuit is configured to alter a bias point of the cross-coupled transistors to induce an oscillation in each tunable bandpass filter, to measure the resonant frequency of the oscillation, and to adjust the resonant frequency of each tunable bandpass filter.
In some embodiment, each variable gain stage amplifier is a transconductance amplifier stage have a plurality of parallel connected transconductance cells.
In one embodiment, the at least one cross-coupled compensation transistor pair comprises a plurality of parallel-connected cross-coupled compensation transistor pairs.
In some embodiments, the at least two variable gain amplifier stages includes a first low noise amplifier stage tuned to a first frequency and a second low noise amplifier stage having a second variable gain amplifier stage, the second low noise amplifier stage tuned to a second frequency and connected serially with the first low noise amplifier stage.
In some embodiments the first frequency and second frequency are selected in accordance with a desired channel frequency.
A method according to some embodiments includes adjusting the gain of at least two variable gain amplifier stages; adjusting a resonant frequency and a Q of each tunable bandpass filter connected as a load to the at least two variable gain amplifier stages, wherein each bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair and a resistor tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; and, biasing the at least one cross-coupled compensation transistor pair in a subthreshold region.
In some embodiments, the method includes adjusting a bias point of the cross-coupled transistors to induce an oscillation in each bandpass filter; measuring a resonant frequency of the respective oscillation; and, adjusting a respective resonant frequency of each bandpass filter.
In some embodiments, the method includes adjusting a bias point of the cross coupled transistors to adjust the Q in each bandpass filter.
Another method according to some embodiments includes adjusting, to a first frequency, a resonant frequency of a first low noise amplifier stage having a first variable gain amplifier stage and a first tunable bandpass filter; adjusting, to a second frequency offset from the first frequency, a resonant frequency of a second low noise amplifier stage having a second variable gain amplifier stage and a second tunable bandpass filter; biasing cross-coupled compensation transistor pairs in each of the first tunable bandpass filter and second tunable bandpass filter in a sub-threshold region; and orienting the first and second tunable bandpass filters to reduce mutual coupling by providing a resonant tank within each of the first and second tunable bandpass filters with an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters.
In some embodiments the first frequency and second frequency are selected in accordance with a desired channel frequency.
In some embodiments, the method includes adjusting a quality factor Q of the first and second bandpass filters to obtain a desired overall bandwidth and adjacent channel rejection ratio.
In some embodiments, each of the adjusting steps of the first and second bandpass filter resonant frequencies includes adjusting a bias point of the cross-coupled transistors to induce an oscillation in the respective bandpass filter; measuring the resonant frequency of the oscillation; and, adjusting the resonant frequency of the respective bandpass filter.
In the foregoing specification, specific embodiments have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings.
The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
Moreover in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has”, “having,” “includes”, “including,” “contains”, “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a”, “has . . . a”, “includes . . . a”, “contains . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms “a” and “an” are defined as one or more unless explicitly stated otherwise herein. The terms “substantially”, “essentially”, “approximately”, “about” or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting embodiment the term is defined to be within 10%, in another embodiment within 5%, in another embodiment within 1% and in another embodiment within 0.5%. The term “coupled” as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is “configured” in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
It will be appreciated that some embodiments may be comprised of one or more generic or specialized processors (or “processing devices”) such as microprocessors, digital signal processors, customized processors and field programmable gate arrays (FPGAs) and unique stored program instructions (including both software and firmware) that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of the method and/or apparatus described herein. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used.
Accordingly, some embodiments of the present disclosure, or portions thereof, may combine one or more processing devices with one or more software components (e.g., program code, firmware, resident software, micro-code, etc.) stored in a tangible computer-readable memory device, which in combination form a specifically configured apparatus that performs the functions as described herein. These combinations that form specially programmed devices may be generally referred to herein “modules”. The software component portions of the modules may be written in any computer language and may be a portion of a monolithic code base, or may be developed in more discrete code portions such as is typical in object-oriented computer languages. In addition, the modules may be distributed across a plurality of computer platforms, servers, terminals, and the like. A given module may even be implemented such that separate processor devices and/or computing hardware platforms perform the described functions.
Moreover, an embodiment can be implemented as a computer-readable storage medium having computer readable code stored thereon for programming a computer (e.g., comprising a processor) to perform a method as described and claimed herein. Examples of such computer-readable storage mediums include, but are not limited to, a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory) and a Flash memory. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
This present application is a Continuation of U.S. application Ser. No. 16/125,480, filed Sep. 7, 2018, entitled “MULTI-STAGE LNA WITH REDUCED MUTUAL COUPLING,” which is hereby incorporated by reference in its entirety.
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Number | Date | Country | |
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20200280293 A1 | Sep 2020 | US |
Number | Date | Country | |
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Parent | 16125480 | Sep 2018 | US |
Child | 16811883 | US |