The present disclosure relates generally to systems and methods for data packet processing. More particularly, the present disclosure relates to systems and methods for lower MAC protocol processing across multiple wireless standards and multiple radios.
With advanced compute capabilities and growing convergence of various wireless standards, it is desired to run multiple wireless standards, e.g., 4G, 5G, or Wi-Fi, on a single hardware together. Typical solutions include developing dedicated hardware accelerators for each wireless standard, for each radio per wireless standard, and even dedicated hardware for each direction (receiving/transmitting, also known as RX/TX). Such solutions may have disadvantages of high area, high power, and complex implementation due to excessive hardware interfaces.
Accordingly, what is needed are systems, devices and methods for data packet processing across multiple wireless standards and multiple radios to improve hardware resources utilization and efficiency in power consumption.
References will be made to embodiments of the disclosure, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the accompanying disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the disclosure to these particular embodiments. Items in the figures may not be to scale.
Figure (“FIG.”) 1A depicts layer architecture of an Open Systems Interconnection model (OSI model) with multiple layers.
In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the disclosure. It will be apparent, however, to one skilled in the art that the disclosure can be practiced without these details. Furthermore, one skilled in the art will recognize that embodiments of the present disclosure, described below, may be implemented in a variety of ways, such as a process, an apparatus, a system/device, or a method on a tangible computer-readable medium.
Components, or modules, shown in diagrams are illustrative of exemplary embodiments of the disclosure and are meant to avoid obscuring the disclosure. It shall also be understood that throughout this discussion that components may be described as separate functional units, which may comprise sub-units, but those skilled in the art will recognize that various components, or portions thereof, may be divided into separate components or may be integrated together, including, for example, being in a single system or component. It should be noted that functions or operations discussed herein may be implemented as components. Components may be implemented in software, hardware, or a combination thereof.
Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, data between these components may be modified, re-formatted, or otherwise changed by intermediary components. Also, additional or fewer connections may be used. It shall also be noted that the terms “coupled,” “connected,” “communicatively coupled,” “interfacing,” “interface,” or any of their derivatives shall be understood to include direct connections, indirect connections through one or more intermediary devices, and wireless connections. It shall also be noted that any communication, such as a signal, response, reply, acknowledgement, message, query, etc., may comprise one or more exchanges of information.
Reference in the specification to “one or more embodiments,” “preferred embodiment,” “an embodiment,” “embodiments,” or the like means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the disclosure and may be in more than one embodiment. Also, the appearances of the above-noted phrases in various places in the specification are not necessarily all referring to the same embodiment or embodiments.
The use of certain terms in various places in the specification is for illustration and should not be construed as limiting. The terms “include,” “including,” “comprise,” and “comprising” shall be understood to be open terms and any examples are provided by way of illustration and shall not be used to limit the scope of this disclosure.
A service, function, or resource is not limited to a single service, function, or resource; usage of these terms may refer to a grouping of related services, functions, or resources, which may be distributed or aggregated. The use of memory, database, information base, data store, tables, hardware, cache, and the like may be used herein to refer to system component or components into which information may be entered or otherwise recorded. The terms “data,” “information,” along with similar terms, may be replaced by other terminologies referring to a group of one or more bits, and may be used interchangeably. The terms “packet” or “frame” shall be understood to mean a group of one or more bits. The term “frame” or “packet” shall not be interpreted as limiting embodiments of the present invention to 5G networks. The terms “packet,” “frame,” “data,” or “data traffic” may be replaced by other terminologies referring to a group of bits, such as “datagram” or “cell.” The words “optimal,” “optimize,” “optimization,” and the like refer to an improvement of an outcome or a process and do not require that the specified outcome or process has achieved an “optimal” or peak state.
It shall be noted that: (1) certain steps may optionally be performed; (2) steps may not be limited to the specific order set forth herein; (3) certain steps may be performed in different orders; and (4) certain steps may be done concurrently.
A. OSI Model and MAC Layer
Within the data link layer 120, the LLC sublayer 124 provides flow control and multiplexing for the logical link, while the MAC sublayer 122 provides flow control and multiplexing for the transmission medium. When sending data to another device on the network, the MAC sublayer may encapsulate higher-level frames into frames appropriate for the transmission medium. For example, the MAC sublayer may add a preamble and also padding if necessary, add a frame check sequence to identify transmission errors, and then forward the data to the physical layer as soon as the appropriate channel access method permits it.
In a telecommunication system, the protocol structure may be different from the OSI model.
The MAC and LLC layers of IEEE 802 networks, e.g., 802.11 Wi-Fi, operate at the data link layer 120. Among the three types of MAC frames in IEEE 802.11, data frame, control frame, and management frame, only data frames comprises high layer data.
In telecommunications under an LTE protocol, the MAC layer connects the upper layer with the lower layer and transfers data and controlling radio resource. The MAC layer is responsible for mapping between logical channels and transport channels, multiplexing of MAC SDUs from one or different logical channels onto transport blocks (TB) to be delivered to the physical layer on transport channels, etc. An LTE MAC PDU is a bit string of multiple of 8 bits.
In telecommunications under 5G NR protocol, the MAC layer provides data transfer and radio resource allocation to upper layers. Also, the MAC layer is responsible for mapping between logical and transport channels (downlink and uplink), multiplexing of MAC SDUs onto TBs in uplink (UL) or demultiplexing of MAC SDUs from TBs in downlink (DL), etc.
In a 5G NR, a MAC sub-PDU always starts with a sub-header, which is followed by a MAC SDU, a MAC CE or padding (optional). When a set of MAC sub-PDUs doesn't exactly fill a TB, a MAC sub-PDU with padding is included. A MAC sub-PDU with only a sub-header may imply zero-length padding. The order of sub-PDUs in a MAC PDU may be defined. In an uplink, the order of concatenation is MAC SDU(s), CEs, and padding. In a downlink, the concatenation order is MAC CEs, SDU(s) and padding.
One skilled in the art shall understand that although only WLAN, LTE and 5G NR are shown in
As shown above, different wireless standards have different protocols and requirements for MAC layer frame. It is desired to run multiple wireless standards, e.g., 4G, 5G, or Wi-Fi, on a single hardware together. Typical solutions include developing dedicated hardware accelerators for each wireless standard, for each radio per wireless standard, and even dedicated hardware for each direction (RX/TX). Such solutions may have disadvantages of high area, high power, and complex implementation due to excessive hardware interfaces.
Described hereinafter are system and method embodiments for lower MAC protocol processing across multiple wireless standards and multiple radios to achieve low area and low power MAC hardware.
B. Embodiments for Lower MAC Protocol Processing
A lower MAC layer implementation of a wireless standards involves many components, e.g., an interface to the physical layer, an interface to a higher MAC layer (software, hardware, or a combination of both), a lower MAC layer protocol processing unit to implement functions such as encapsulation/decapsulation of packets (e.g., PSDUs/aggregated mac PDUs in Wi-Fi, TBs in NR/LTE, etc.), frame check sequence (FCS)/cyclic redundancy check (CRC), scrambling/descrambling, and processing of decapsulated packet headers and deriving metadata.
While there are variations in each wireless standard, many of the control and hardware accelerations in the lower MAC layer may have commonality. For example, the interface to the physical layer is in units of codeblock, which may be memory mapped. The interface to the higher MAC is in terms of free buffer lists (for RX), filled buffers (RX/TX), etc. Furthermore, the functionality of a specific wireless standard across different users is common. Infrastructure components for reading/writing of data from/to internal/external memories are common. The processing flow of packets may be implemented to have at least few commonalities across wireless standards. When these resources may be managed to leverage these commonalities, the efficiency in power consumption and hardware resources utilization may be improved.
In this section, embodiments for lower MAC protocol processing across multiple wireless standards and multiple radios. In embodiments, a common hardware is used for processing lower MAC flows across multiple wireless standards (e.g., WLAN, 5G NR, or LTE, etc.), multiple radios within a wireless standard, multiple users within a wireless standard (e.g., Physical Layer Convergence Protocol (PLCP) Service Data Units (PSDUs) in WLAN, TBs in NR/LTE), and/or different directions of radio (RX/TX). The implementation may support partial data processing of a flow, switching across flows, and context saving/restoring of flows. With the implementation of one or more embodiments, support for multiple flows with a common hardware may be achieved. Furthermore, for better performance, looking ahead of flows and prefetching of context and data may also be implemented. Embodiments of the present patent disclosure may result in a very area-efficient and power-efficient hardware implementation for lower MAC protocol processing.
In one or more embodiments, common hardware architecture, with save/restore of needed hardware context in an internal memory which is per wireless standard, per user in a wireless standard and per direction (RX/TX), is used to achieve an area-efficient and power-efficient hardware with common interfaces to the block.
In one or more embodiments, the hardware 305 may comprise one or more blocks or units for data processing in RX/TX directions. The hardware 305 is described in separate diagrams in RX direction in
In the MAC/L2 layer 320, the plurality of decoder codeblocks 312 and the plurality of RX configuration blocks 314 are processed to output one or more decapsulated packets 332, along with packet metadata 334, and an overall status 336 for each of the multiple RX flows. In one or more embodiments, the packet metadata 334 across the multiple RX flows may be transmitted in a packer header queue for further processing in a higher layer 330, which is a layer or a sublayer high than the MAC/L2 layer 320. For example, the higher layer 330 may be a LLC sublayer within a data link layer, higher MAC data plane stage in WLAN implementation, an RLC layer or PDCP layer in NR/LTE implementation, or a network layer. The PHY 310, the MAC/L2 layer 320, and the higher layer 330 are all within a communication device 302, e.g., a wireless phone, a laptop, a router, an access point, a network interface controller (NIC), a base station, etc.
In one or more embodiments, the MAC layer 320 comprises a flow context memory 322, a header memory 324, and a payload memory 326. The flow context memory 322 may be used for storing hardware context or fetching stored hardware context for at least one of the multiple RX flows. The header memory 324 may be used for storing header or sub-header data or fetching stored header or sub-header data for at least one of the multiple RX flows. The payload memory 326 may couple to the packet writer 368 to provide one or more decapsulated packets 332, e.g., payload data linked list per RX flow.
As a short summary for RX flow processing, in the MAC/L2 layer 320, the plurality of decoder codeblocks 312 are processed to output one or more decapsulated packets 332, along with packet metadata 334, and a flow status 336 for each of the multiple RX flows. In one or more embodiments, the packet metadata 334 across the multiple RX flows may be stored in a packer header queue for further processing in a higher layer 330.
Components in the hardware 305 for TX flow processing may comprise a context switch control unit 372, a framer 374, and a packet reading and processing unit 376. The context switch control unit 372 performs codeblock descriptor reading for the plurality of codeblock descriptors 436 and switching operation across different TX data flows. The packet parsing and processing unit 376 performs parsing and processing operations for the data packets, fetched from the packet data fragment buffer 434, to generate one or more processed data packets 378. The framer 374 performs framing operation for the one or more processed data packets 378 to form one or more encoder codeblocks 412 across multiple TX flows. The framer 374 is coupled to a flow context memory 322 to save TX flow information to the flow context memory 322 or fetch saved TX flow information from the flow context memory 322. The saved TX flow information may be information needed to resume TX flow processing from where the processing is stored and may comprise one or more from a group comprising a header, a sub-header, a padding, a CRC, a scrambler state, payload buffer state, or remaining flow size, etc.
In one or more embodiments, one or more components in the hardware 305 may be configured for both TX flow processing and RX flow processing. For example, the framer 374 and the de-framer 364 may be the same hardware and be configured for de-framing operation when handling RX flows and for framing operation when handling TX flows.
As a short summary for TX flow processing, in the MAC layer 320, the plurality of packets 432, the plurality of codeblock descriptors 436, and the plurality of TX configuration blocks 438 are processed to generate one or more encoder codeblocks 412 for each of the multiple TX flows, along with a flow status 414 for each TX flow towards the PHY 310.
In one or more embodiments, for RX or TX direction, each flow may be active at a time for a codeblock unit. In a codeblock sequence, the MAC/L2 layer may temporarily suspend or stop processing a first data flow and switch to process a second data flow based on one or more constraints.
In step 610, when the MAC/L2 layer resumes processing the first data flow, the MAC layer retrieves the saved at least part of the first data flow and the associated information from the one or more memories (when the first data flow is a RX flow), or data fetching of the first data flow from the packet data buffers 434 resumes (when the first data flow is a TX flow) from where the data fetching stopped. In step 615, the MAC layer resumes processing the first data flow to generate one or more desired outputs based at least on the saved at least part of the first data flow and associated information. In one example, the first data flow may be a Wi-Fi data flow comprising one or more data packets. The MAC/L2 layer may be running a CRC for the first data flow and finishes checking for only part of the one or more data packets when the MAC/L2 layer stops processing the first data flow. The MAC/L2 layer may save an end point of the CRC to a memory (e.g., the flow context memory 322). When the MAC/L2 layer resumes processing the first data flow, the MAC/L2 layer fetches the end point and restarts the CRC from the end point instead of running CRC for the entire data flow again.
In certain situations, the MAC/L2 layer may look ahead beyond a currently processing data flow and actively pre-fetch at least part (e.g., payload, header, or sub-header, etc.) of one or more flows subsequent to the current processing data flow, which may further improve the efficiency for the MAC layer to process multiple data flows.
It shall be noted that a higher layer may be a layer or sublayer for RLC, PDCP or Network Layer for NR/LTE, and for WLAN, the higher layer may be one or more stages in a MAC data plane, an LLC layer, or a Network Layer. The aforementioned embodiments for shared hardware across multiple wireless technologies or users may be applied for various applications. For example, crypto implementation may be a common one where the same crypto hardware may be shared since Advanced Encryption Standard (AES) may be common across various wireless standards. Service Data Unit (SDU) processing hardware for packets interfacing with a Network Layer may also be shared across multiple wireless standards. Such variations or extensions are also within the true spirit and scope of the present disclosure.
Aspects of the present disclosure may be encoded upon one or more non-transitory computer-readable media with instructions for one or more processors or processing units to cause steps to be performed. It shall be noted that non-transitory computer-readable media shall include volatile and/or non-volatile memory. It shall be noted that alternative implementations are possible, including a hardware implementation or a software/hardware implementation. Hardware-implemented functions may be realized using ASIC(s), programmable arrays, digital signal processing circuitry, or the like. Accordingly, the “means” terms in any claims are intended to cover both software and hardware implementations. Similarly, the term “computer-readable medium or media” as used herein includes software and/or hardware having a program of instructions embodied thereon, or a combination thereof. With these implementation alternatives in mind, it is to be understood that the figures and accompanying description provide the functional information one skilled in the art would require to write program code (i.e., software) and/or to fabricate circuits (i.e., hardware) to perform the processing required.
It shall be noted that embodiments of the present disclosure may further relate to computer products with a non-transitory, tangible computer-readable medium that has computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present disclosure, or they may be of the kind known or available to those having skill in the relevant arts. Examples of tangible computer-readable media include, for example: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CDs and holographic devices; magneto-optical media; and hardware devices that are specially configured to store or to store and execute program code, such as ASICs, PLDs, flash memory devices, other non-volatile memory devices, and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Embodiments of the present disclosure may be implemented in whole or in part as machine-executable instructions that may be in program modules that are executed by one or more processing devices. Examples of program modules include libraries, programs, routines, objects, components, and data structures. In distributed computing environments, program modules may be physically located in settings that are local, remote, or both.
One skilled in the art will recognize no computing system or programming language is critical to the practice of the present disclosure. One skilled in the art will also recognize that a number of the elements described above may be physically and/or functionally separated into modules and/or sub-modules or combined together.
It will be appreciated to those skilled in the art that the preceding examples and embodiments are exemplary and not limiting to the scope of the present disclosure. It is intended that all permutations, enhancements, equivalents, combinations, and improvements thereto that are apparent to those skilled in the art upon a reading of the specification and a study of the drawings are included within the true spirit and scope of the present disclosure. It shall also be noted that elements of any claims may be arranged differently, including having multiple dependencies, configurations, and combinations.