Joy et al., "Multi-Port Asymmetrical Memory Cell," IBM Tech. Disc. Bul., vol. 23, No. 7A, 12/80, p. 2822. |
Catt et al. "A High-Speed Integrated Circuit Scratchpad Memory," Proceedings-Fall Joint Computer Conf., vol. 29, pp. 315-331, 11/7-10/66. |
Reinert et al., "A 32x9 ECL Dual Address Register Using an Interleaving Cell Technique," IEEE 5SSCC 77, 2/16/77, pp. 72-73. |
Cretelli et al., "Dual Schottky Diode Cell," IBM Tech. Disc. Bul., vol. 22, No. 4, 9/79, pp. 1489-1492. |
Cavaliere et al., "Memory Cell Adapted for Different Combinations of Simultaneous Read and Write Operations," IBM Tech. Disc. Bul., vol. 23, No. 1, 6/80, pp. 180-186. |
Stopper et al., "Eine Integrierte Schaltung zur Realiserung eines Halbleiterspeichers," Proc. of the IFAC/IFIP Symp, 10/21-23/65, pp. 259-273. |
Dennison et al., "Multi-Port Array Cell," IBM Tech. Disc. Bul., vol. 22, No. 10, 3/80, pp. 4553-4554. |
Chang, "Multiple-Read Single-Write Memory and Its Applications," IEEE Trans. on Computers, vol. C-29, No. 8, 8/80, pp. 689-694. |
Price, "Simultaneous Access Memory," IBM Tech. Disc. Bul., vol. 23, No. 2, 7/80, pp. 657-658. |